162306a36Sopenharmony_ci[
262306a36Sopenharmony_ci    {
362306a36Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
462306a36Sopenharmony_ci        "EventCode": "0x5C",
562306a36Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0",
662306a36Sopenharmony_ci        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
762306a36Sopenharmony_ci        "SampleAfterValue": "2000003",
862306a36Sopenharmony_ci        "UMask": "0x1"
962306a36Sopenharmony_ci    },
1062306a36Sopenharmony_ci    {
1162306a36Sopenharmony_ci        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
1262306a36Sopenharmony_ci        "CounterMask": "1",
1362306a36Sopenharmony_ci        "EdgeDetect": "1",
1462306a36Sopenharmony_ci        "EventCode": "0x5C",
1562306a36Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0_TRANS",
1662306a36Sopenharmony_ci        "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
1762306a36Sopenharmony_ci        "SampleAfterValue": "100007",
1862306a36Sopenharmony_ci        "UMask": "0x1"
1962306a36Sopenharmony_ci    },
2062306a36Sopenharmony_ci    {
2162306a36Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
2262306a36Sopenharmony_ci        "EventCode": "0x5C",
2362306a36Sopenharmony_ci        "EventName": "CPL_CYCLES.RING123",
2462306a36Sopenharmony_ci        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
2562306a36Sopenharmony_ci        "SampleAfterValue": "2000003",
2662306a36Sopenharmony_ci        "UMask": "0x2"
2762306a36Sopenharmony_ci    },
2862306a36Sopenharmony_ci    {
2962306a36Sopenharmony_ci        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
3062306a36Sopenharmony_ci        "EventCode": "0x63",
3162306a36Sopenharmony_ci        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
3262306a36Sopenharmony_ci        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
3362306a36Sopenharmony_ci        "SampleAfterValue": "2000003",
3462306a36Sopenharmony_ci        "UMask": "0x1"
3562306a36Sopenharmony_ci    }
3662306a36Sopenharmony_ci]
37