1// SPDX-License-Identifier: GPL-2.0 2/* 3 * x86 instruction nmemonic table to parse disasm lines for annotate. 4 * This table is searched twice - one for exact match and another for 5 * match without a size suffix (b, w, l, q) in case of AT&T syntax. 6 * 7 * So this table should not have entries with the suffix unless it's 8 * a complete different instruction than ones without the suffix. 9 */ 10static struct ins x86__instructions[] = { 11 { .name = "adc", .ops = &mov_ops, }, 12 { .name = "add", .ops = &mov_ops, }, 13 { .name = "addsd", .ops = &mov_ops, }, 14 { .name = "and", .ops = &mov_ops, }, 15 { .name = "andpd", .ops = &mov_ops, }, 16 { .name = "andps", .ops = &mov_ops, }, 17 { .name = "bsr", .ops = &mov_ops, }, 18 { .name = "bt", .ops = &mov_ops, }, 19 { .name = "btr", .ops = &mov_ops, }, 20 { .name = "bts", .ops = &mov_ops, }, 21 { .name = "call", .ops = &call_ops, }, 22 { .name = "cmovbe", .ops = &mov_ops, }, 23 { .name = "cmove", .ops = &mov_ops, }, 24 { .name = "cmovae", .ops = &mov_ops, }, 25 { .name = "cmp", .ops = &mov_ops, }, 26 { .name = "cmpxch", .ops = &mov_ops, }, 27 { .name = "cmpxchg", .ops = &mov_ops, }, 28 { .name = "cs", .ops = &mov_ops, }, 29 { .name = "dec", .ops = &dec_ops, }, 30 { .name = "divsd", .ops = &mov_ops, }, 31 { .name = "divss", .ops = &mov_ops, }, 32 { .name = "gs", .ops = &mov_ops, }, 33 { .name = "imul", .ops = &mov_ops, }, 34 { .name = "inc", .ops = &dec_ops, }, 35 { .name = "ja", .ops = &jump_ops, }, 36 { .name = "jae", .ops = &jump_ops, }, 37 { .name = "jb", .ops = &jump_ops, }, 38 { .name = "jbe", .ops = &jump_ops, }, 39 { .name = "jc", .ops = &jump_ops, }, 40 { .name = "jcxz", .ops = &jump_ops, }, 41 { .name = "je", .ops = &jump_ops, }, 42 { .name = "jecxz", .ops = &jump_ops, }, 43 { .name = "jg", .ops = &jump_ops, }, 44 { .name = "jge", .ops = &jump_ops, }, 45 { .name = "jl", .ops = &jump_ops, }, 46 { .name = "jle", .ops = &jump_ops, }, 47 { .name = "jmp", .ops = &jump_ops, }, 48 { .name = "jna", .ops = &jump_ops, }, 49 { .name = "jnae", .ops = &jump_ops, }, 50 { .name = "jnb", .ops = &jump_ops, }, 51 { .name = "jnbe", .ops = &jump_ops, }, 52 { .name = "jnc", .ops = &jump_ops, }, 53 { .name = "jne", .ops = &jump_ops, }, 54 { .name = "jng", .ops = &jump_ops, }, 55 { .name = "jnge", .ops = &jump_ops, }, 56 { .name = "jnl", .ops = &jump_ops, }, 57 { .name = "jnle", .ops = &jump_ops, }, 58 { .name = "jno", .ops = &jump_ops, }, 59 { .name = "jnp", .ops = &jump_ops, }, 60 { .name = "jns", .ops = &jump_ops, }, 61 { .name = "jnz", .ops = &jump_ops, }, 62 { .name = "jo", .ops = &jump_ops, }, 63 { .name = "jp", .ops = &jump_ops, }, 64 { .name = "jpe", .ops = &jump_ops, }, 65 { .name = "jpo", .ops = &jump_ops, }, 66 { .name = "jrcxz", .ops = &jump_ops, }, 67 { .name = "js", .ops = &jump_ops, }, 68 { .name = "jz", .ops = &jump_ops, }, 69 { .name = "lea", .ops = &mov_ops, }, 70 { .name = "lock", .ops = &lock_ops, }, 71 { .name = "mov", .ops = &mov_ops, }, 72 { .name = "movapd", .ops = &mov_ops, }, 73 { .name = "movaps", .ops = &mov_ops, }, 74 { .name = "movdqa", .ops = &mov_ops, }, 75 { .name = "movdqu", .ops = &mov_ops, }, 76 { .name = "movsd", .ops = &mov_ops, }, 77 { .name = "movslq", .ops = &mov_ops, }, 78 { .name = "movss", .ops = &mov_ops, }, 79 { .name = "movupd", .ops = &mov_ops, }, 80 { .name = "movups", .ops = &mov_ops, }, 81 { .name = "movzbl", .ops = &mov_ops, }, 82 { .name = "movzwl", .ops = &mov_ops, }, 83 { .name = "mulsd", .ops = &mov_ops, }, 84 { .name = "mulss", .ops = &mov_ops, }, 85 { .name = "nop", .ops = &nop_ops, }, 86 { .name = "or", .ops = &mov_ops, }, 87 { .name = "orps", .ops = &mov_ops, }, 88 { .name = "pand", .ops = &mov_ops, }, 89 { .name = "paddq", .ops = &mov_ops, }, 90 { .name = "pcmpeqb", .ops = &mov_ops, }, 91 { .name = "por", .ops = &mov_ops, }, 92 { .name = "rcl", .ops = &mov_ops, }, 93 { .name = "ret", .ops = &ret_ops, }, 94 { .name = "sbb", .ops = &mov_ops, }, 95 { .name = "sete", .ops = &mov_ops, }, 96 { .name = "sub", .ops = &mov_ops, }, 97 { .name = "subsd", .ops = &mov_ops, }, 98 { .name = "test", .ops = &mov_ops, }, 99 { .name = "tzcnt", .ops = &mov_ops, }, 100 { .name = "ucomisd", .ops = &mov_ops, }, 101 { .name = "ucomiss", .ops = &mov_ops, }, 102 { .name = "vaddsd", .ops = &mov_ops, }, 103 { .name = "vandpd", .ops = &mov_ops, }, 104 { .name = "vmovdqa", .ops = &mov_ops, }, 105 { .name = "vmovq", .ops = &mov_ops, }, 106 { .name = "vmovsd", .ops = &mov_ops, }, 107 { .name = "vmulsd", .ops = &mov_ops, }, 108 { .name = "vorpd", .ops = &mov_ops, }, 109 { .name = "vsubsd", .ops = &mov_ops, }, 110 { .name = "vucomisd", .ops = &mov_ops, }, 111 { .name = "xadd", .ops = &mov_ops, }, 112 { .name = "xbegin", .ops = &jump_ops, }, 113 { .name = "xchg", .ops = &mov_ops, }, 114 { .name = "xor", .ops = &mov_ops, }, 115 { .name = "xorpd", .ops = &mov_ops, }, 116 { .name = "xorps", .ops = &mov_ops, }, 117}; 118 119static bool amd__ins_is_fused(struct arch *arch, const char *ins1, 120 const char *ins2) 121{ 122 if (strstr(ins2, "jmp")) 123 return false; 124 125 /* Family >= 15h supports cmp/test + branch fusion */ 126 if (arch->family >= 0x15 && (strstarts(ins1, "test") || 127 (strstarts(ins1, "cmp") && !strstr(ins1, "xchg")))) { 128 return true; 129 } 130 131 /* Family >= 19h supports some ALU + branch fusion */ 132 if (arch->family >= 0x19 && (strstarts(ins1, "add") || 133 strstarts(ins1, "sub") || strstarts(ins1, "and") || 134 strstarts(ins1, "inc") || strstarts(ins1, "dec") || 135 strstarts(ins1, "or") || strstarts(ins1, "xor"))) { 136 return true; 137 } 138 139 return false; 140} 141 142static bool intel__ins_is_fused(struct arch *arch, const char *ins1, 143 const char *ins2) 144{ 145 if (arch->family != 6 || arch->model < 0x1e || strstr(ins2, "jmp")) 146 return false; 147 148 if (arch->model == 0x1e) { 149 /* Nehalem */ 150 if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) || 151 strstr(ins1, "test")) { 152 return true; 153 } 154 } else { 155 /* Newer platform */ 156 if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) || 157 strstr(ins1, "test") || 158 strstr(ins1, "add") || 159 strstr(ins1, "sub") || 160 strstr(ins1, "and") || 161 strstr(ins1, "inc") || 162 strstr(ins1, "dec")) { 163 return true; 164 } 165 } 166 167 return false; 168} 169 170static int x86__cpuid_parse(struct arch *arch, char *cpuid) 171{ 172 unsigned int family, model, stepping; 173 int ret; 174 175 /* 176 * cpuid = "GenuineIntel,family,model,stepping" 177 */ 178 ret = sscanf(cpuid, "%*[^,],%u,%u,%u", &family, &model, &stepping); 179 if (ret == 3) { 180 arch->family = family; 181 arch->model = model; 182 arch->ins_is_fused = strstarts(cpuid, "AuthenticAMD") ? 183 amd__ins_is_fused : 184 intel__ins_is_fused; 185 return 0; 186 } 187 188 return -1; 189} 190 191static int x86__annotate_init(struct arch *arch, char *cpuid) 192{ 193 int err = 0; 194 195 if (arch->initialized) 196 return 0; 197 198 if (cpuid) { 199 if (x86__cpuid_parse(arch, cpuid)) 200 err = SYMBOL_ANNOTATE_ERRNO__ARCH_INIT_CPUID_PARSING; 201 } 202 203 arch->initialized = true; 204 return err; 205} 206