162306a36Sopenharmony_ciC LB+fencembonceonce+ctrlonceonce 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci(* 462306a36Sopenharmony_ci * Result: Never 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * This litmus test demonstrates that lightweight ordering suffices for 762306a36Sopenharmony_ci * the load-buffering pattern, in other words, preventing all processes 862306a36Sopenharmony_ci * reading from the preceding process's write. In this example, the 962306a36Sopenharmony_ci * combination of a control dependency and a full memory barrier are enough 1062306a36Sopenharmony_ci * to do the trick. (But the full memory barrier could be replaced with 1162306a36Sopenharmony_ci * another control dependency and order would still be maintained.) 1262306a36Sopenharmony_ci *) 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci{} 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciP0(int *x, int *y) 1762306a36Sopenharmony_ci{ 1862306a36Sopenharmony_ci int r0; 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci r0 = READ_ONCE(*x); 2162306a36Sopenharmony_ci if (r0) 2262306a36Sopenharmony_ci WRITE_ONCE(*y, 1); 2362306a36Sopenharmony_ci} 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciP1(int *x, int *y) 2662306a36Sopenharmony_ci{ 2762306a36Sopenharmony_ci int r0; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci r0 = READ_ONCE(*y); 3062306a36Sopenharmony_ci smp_mb(); 3162306a36Sopenharmony_ci WRITE_ONCE(*x, 1); 3262306a36Sopenharmony_ci} 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciexists (0:r0=1 /\ 1:r0=1) 35