1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* CPU model specific register (MSR) numbers. */ 8 9/* x86-64 specific MSRs */ 10#define MSR_EFER 0xc0000080 /* extended feature register */ 11#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19 20/* EFER bits: */ 21#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22#define _EFER_LME 8 /* Long mode enable */ 23#define _EFER_LMA 10 /* Long mode active (read-only) */ 24#define _EFER_NX 11 /* No execute enable */ 25#define _EFER_SVME 12 /* Enable virtualization */ 26#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ 29 30#define EFER_SCE (1<<_EFER_SCE) 31#define EFER_LME (1<<_EFER_LME) 32#define EFER_LMA (1<<_EFER_LMA) 33#define EFER_NX (1<<_EFER_NX) 34#define EFER_SVME (1<<_EFER_SVME) 35#define EFER_LMSLE (1<<_EFER_LMSLE) 36#define EFER_FFXSR (1<<_EFER_FFXSR) 37#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) 38 39/* Intel MSRs. Some also available on other CPUs */ 40 41#define MSR_TEST_CTRL 0x00000033 42#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 43#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 44 45#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 46#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 47#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 48#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 49#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 50#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 51#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 52#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 53 54/* A mask for bits which the kernel toggles when controlling mitigations */ 55#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 56 | SPEC_CTRL_RRSBA_DIS_S) 57 58#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 59#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 60#define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 61 62#define MSR_PPIN_CTL 0x0000004e 63#define MSR_PPIN 0x0000004f 64 65#define MSR_IA32_PERFCTR0 0x000000c1 66#define MSR_IA32_PERFCTR1 0x000000c2 67#define MSR_FSB_FREQ 0x000000cd 68#define MSR_PLATFORM_INFO 0x000000ce 69#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 70#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 71 72#define MSR_IA32_UMWAIT_CONTROL 0xe1 73#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 74#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 75/* 76 * The time field is bit[31:2], but representing a 32bit value with 77 * bit[1:0] zero. 78 */ 79#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 80 81/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 82#define MSR_IA32_CORE_CAPS 0x000000cf 83#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 84#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 85#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 86#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 87 88#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 89#define NHM_C3_AUTO_DEMOTE (1UL << 25) 90#define NHM_C1_AUTO_DEMOTE (1UL << 26) 91#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 92#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 93#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 94 95#define MSR_MTRRcap 0x000000fe 96 97#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 98#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 99#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 100#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 101#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 102#define ARCH_CAP_SSB_NO BIT(4) /* 103 * Not susceptible to Speculative Store Bypass 104 * attack, so no Speculative Store Bypass 105 * control required. 106 */ 107#define ARCH_CAP_MDS_NO BIT(5) /* 108 * Not susceptible to 109 * Microarchitectural Data 110 * Sampling (MDS) vulnerabilities. 111 */ 112#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 113 * The processor is not susceptible to a 114 * machine check error due to modifying the 115 * code page size along with either the 116 * physical address or cache type 117 * without TLB invalidation. 118 */ 119#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 120#define ARCH_CAP_TAA_NO BIT(8) /* 121 * Not susceptible to 122 * TSX Async Abort (TAA) vulnerabilities. 123 */ 124#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 125 * Not susceptible to SBDR and SSDP 126 * variants of Processor MMIO stale data 127 * vulnerabilities. 128 */ 129#define ARCH_CAP_FBSDP_NO BIT(14) /* 130 * Not susceptible to FBSDP variant of 131 * Processor MMIO stale data 132 * vulnerabilities. 133 */ 134#define ARCH_CAP_PSDP_NO BIT(15) /* 135 * Not susceptible to PSDP variant of 136 * Processor MMIO stale data 137 * vulnerabilities. 138 */ 139#define ARCH_CAP_FB_CLEAR BIT(17) /* 140 * VERW clears CPU fill buffer 141 * even on MDS_NO CPUs. 142 */ 143#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 144 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 145 * bit available to control VERW 146 * behavior. 147 */ 148#define ARCH_CAP_RRSBA BIT(19) /* 149 * Indicates RET may use predictors 150 * other than the RSB. With eIBRS 151 * enabled predictions in kernel mode 152 * are restricted to targets in 153 * kernel. 154 */ 155#define ARCH_CAP_PBRSB_NO BIT(24) /* 156 * Not susceptible to Post-Barrier 157 * Return Stack Buffer Predictions. 158 */ 159#define ARCH_CAP_GDS_CTRL BIT(25) /* 160 * CPU is vulnerable to Gather 161 * Data Sampling (GDS) and 162 * has controls for mitigation. 163 */ 164#define ARCH_CAP_GDS_NO BIT(26) /* 165 * CPU is not vulnerable to Gather 166 * Data Sampling (GDS). 167 */ 168 169#define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 170 * IA32_XAPIC_DISABLE_STATUS MSR 171 * supported 172 */ 173 174#define MSR_IA32_FLUSH_CMD 0x0000010b 175#define L1D_FLUSH BIT(0) /* 176 * Writeback and invalidate the 177 * L1 data cache. 178 */ 179 180#define MSR_IA32_BBL_CR_CTL 0x00000119 181#define MSR_IA32_BBL_CR_CTL3 0x0000011e 182 183#define MSR_IA32_TSX_CTRL 0x00000122 184#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 185#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 186 187#define MSR_IA32_MCU_OPT_CTRL 0x00000123 188#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 189#define RTM_ALLOW BIT(1) /* TSX development mode */ 190#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 191#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ 192#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ 193 194#define MSR_IA32_SYSENTER_CS 0x00000174 195#define MSR_IA32_SYSENTER_ESP 0x00000175 196#define MSR_IA32_SYSENTER_EIP 0x00000176 197 198#define MSR_IA32_MCG_CAP 0x00000179 199#define MSR_IA32_MCG_STATUS 0x0000017a 200#define MSR_IA32_MCG_CTL 0x0000017b 201#define MSR_ERROR_CONTROL 0x0000017f 202#define MSR_IA32_MCG_EXT_CTL 0x000004d0 203 204#define MSR_OFFCORE_RSP_0 0x000001a6 205#define MSR_OFFCORE_RSP_1 0x000001a7 206#define MSR_TURBO_RATIO_LIMIT 0x000001ad 207#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 208#define MSR_TURBO_RATIO_LIMIT2 0x000001af 209 210#define MSR_SNOOP_RSP_0 0x00001328 211#define MSR_SNOOP_RSP_1 0x00001329 212 213#define MSR_LBR_SELECT 0x000001c8 214#define MSR_LBR_TOS 0x000001c9 215 216#define MSR_IA32_POWER_CTL 0x000001fc 217#define MSR_IA32_POWER_CTL_BIT_EE 19 218 219/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 220#define MSR_INTEGRITY_CAPS 0x000002d9 221#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 222#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 223#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 224#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 225 226#define MSR_LBR_NHM_FROM 0x00000680 227#define MSR_LBR_NHM_TO 0x000006c0 228#define MSR_LBR_CORE_FROM 0x00000040 229#define MSR_LBR_CORE_TO 0x00000060 230 231#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 232#define LBR_INFO_MISPRED BIT_ULL(63) 233#define LBR_INFO_IN_TX BIT_ULL(62) 234#define LBR_INFO_ABORT BIT_ULL(61) 235#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 236#define LBR_INFO_CYCLES 0xffff 237#define LBR_INFO_BR_TYPE_OFFSET 56 238#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 239 240#define MSR_ARCH_LBR_CTL 0x000014ce 241#define ARCH_LBR_CTL_LBREN BIT(0) 242#define ARCH_LBR_CTL_CPL_OFFSET 1 243#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 244#define ARCH_LBR_CTL_STACK_OFFSET 3 245#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 246#define ARCH_LBR_CTL_FILTER_OFFSET 16 247#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 248#define MSR_ARCH_LBR_DEPTH 0x000014cf 249#define MSR_ARCH_LBR_FROM_0 0x00001500 250#define MSR_ARCH_LBR_TO_0 0x00001600 251#define MSR_ARCH_LBR_INFO_0 0x00001200 252 253#define MSR_IA32_PEBS_ENABLE 0x000003f1 254#define MSR_PEBS_DATA_CFG 0x000003f2 255#define MSR_IA32_DS_AREA 0x00000600 256#define MSR_IA32_PERF_CAPABILITIES 0x00000345 257#define PERF_CAP_METRICS_IDX 15 258#define PERF_CAP_PT_IDX 16 259 260#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 261#define PERF_CAP_PEBS_TRAP BIT_ULL(6) 262#define PERF_CAP_ARCH_REG BIT_ULL(7) 263#define PERF_CAP_PEBS_FORMAT 0xf00 264#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 265#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 266 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 267 268#define MSR_IA32_RTIT_CTL 0x00000570 269#define RTIT_CTL_TRACEEN BIT(0) 270#define RTIT_CTL_CYCLEACC BIT(1) 271#define RTIT_CTL_OS BIT(2) 272#define RTIT_CTL_USR BIT(3) 273#define RTIT_CTL_PWR_EVT_EN BIT(4) 274#define RTIT_CTL_FUP_ON_PTW BIT(5) 275#define RTIT_CTL_FABRIC_EN BIT(6) 276#define RTIT_CTL_CR3EN BIT(7) 277#define RTIT_CTL_TOPA BIT(8) 278#define RTIT_CTL_MTC_EN BIT(9) 279#define RTIT_CTL_TSC_EN BIT(10) 280#define RTIT_CTL_DISRETC BIT(11) 281#define RTIT_CTL_PTW_EN BIT(12) 282#define RTIT_CTL_BRANCH_EN BIT(13) 283#define RTIT_CTL_EVENT_EN BIT(31) 284#define RTIT_CTL_NOTNT BIT_ULL(55) 285#define RTIT_CTL_MTC_RANGE_OFFSET 14 286#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 287#define RTIT_CTL_CYC_THRESH_OFFSET 19 288#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 289#define RTIT_CTL_PSB_FREQ_OFFSET 24 290#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 291#define RTIT_CTL_ADDR0_OFFSET 32 292#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 293#define RTIT_CTL_ADDR1_OFFSET 36 294#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 295#define RTIT_CTL_ADDR2_OFFSET 40 296#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 297#define RTIT_CTL_ADDR3_OFFSET 44 298#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 299#define MSR_IA32_RTIT_STATUS 0x00000571 300#define RTIT_STATUS_FILTEREN BIT(0) 301#define RTIT_STATUS_CONTEXTEN BIT(1) 302#define RTIT_STATUS_TRIGGEREN BIT(2) 303#define RTIT_STATUS_BUFFOVF BIT(3) 304#define RTIT_STATUS_ERROR BIT(4) 305#define RTIT_STATUS_STOPPED BIT(5) 306#define RTIT_STATUS_BYTECNT_OFFSET 32 307#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 308#define MSR_IA32_RTIT_ADDR0_A 0x00000580 309#define MSR_IA32_RTIT_ADDR0_B 0x00000581 310#define MSR_IA32_RTIT_ADDR1_A 0x00000582 311#define MSR_IA32_RTIT_ADDR1_B 0x00000583 312#define MSR_IA32_RTIT_ADDR2_A 0x00000584 313#define MSR_IA32_RTIT_ADDR2_B 0x00000585 314#define MSR_IA32_RTIT_ADDR3_A 0x00000586 315#define MSR_IA32_RTIT_ADDR3_B 0x00000587 316#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 317#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 318#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 319 320#define MSR_MTRRfix64K_00000 0x00000250 321#define MSR_MTRRfix16K_80000 0x00000258 322#define MSR_MTRRfix16K_A0000 0x00000259 323#define MSR_MTRRfix4K_C0000 0x00000268 324#define MSR_MTRRfix4K_C8000 0x00000269 325#define MSR_MTRRfix4K_D0000 0x0000026a 326#define MSR_MTRRfix4K_D8000 0x0000026b 327#define MSR_MTRRfix4K_E0000 0x0000026c 328#define MSR_MTRRfix4K_E8000 0x0000026d 329#define MSR_MTRRfix4K_F0000 0x0000026e 330#define MSR_MTRRfix4K_F8000 0x0000026f 331#define MSR_MTRRdefType 0x000002ff 332 333#define MSR_IA32_CR_PAT 0x00000277 334 335#define MSR_IA32_DEBUGCTLMSR 0x000001d9 336#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 337#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 338#define MSR_IA32_LASTINTFROMIP 0x000001dd 339#define MSR_IA32_LASTINTTOIP 0x000001de 340 341#define MSR_IA32_PASID 0x00000d93 342#define MSR_IA32_PASID_VALID BIT_ULL(31) 343 344/* DEBUGCTLMSR bits (others vary by model): */ 345#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 346#define DEBUGCTLMSR_BTF_SHIFT 1 347#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 348#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 349#define DEBUGCTLMSR_TR (1UL << 6) 350#define DEBUGCTLMSR_BTS (1UL << 7) 351#define DEBUGCTLMSR_BTINT (1UL << 8) 352#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 353#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 354#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 355#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 356#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 357#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 358 359#define MSR_PEBS_FRONTEND 0x000003f7 360 361#define MSR_IA32_MC0_CTL 0x00000400 362#define MSR_IA32_MC0_STATUS 0x00000401 363#define MSR_IA32_MC0_ADDR 0x00000402 364#define MSR_IA32_MC0_MISC 0x00000403 365 366/* C-state Residency Counters */ 367#define MSR_PKG_C3_RESIDENCY 0x000003f8 368#define MSR_PKG_C6_RESIDENCY 0x000003f9 369#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 370#define MSR_PKG_C7_RESIDENCY 0x000003fa 371#define MSR_CORE_C3_RESIDENCY 0x000003fc 372#define MSR_CORE_C6_RESIDENCY 0x000003fd 373#define MSR_CORE_C7_RESIDENCY 0x000003fe 374#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 375#define MSR_PKG_C2_RESIDENCY 0x0000060d 376#define MSR_PKG_C8_RESIDENCY 0x00000630 377#define MSR_PKG_C9_RESIDENCY 0x00000631 378#define MSR_PKG_C10_RESIDENCY 0x00000632 379 380/* Interrupt Response Limit */ 381#define MSR_PKGC3_IRTL 0x0000060a 382#define MSR_PKGC6_IRTL 0x0000060b 383#define MSR_PKGC7_IRTL 0x0000060c 384#define MSR_PKGC8_IRTL 0x00000633 385#define MSR_PKGC9_IRTL 0x00000634 386#define MSR_PKGC10_IRTL 0x00000635 387 388/* Run Time Average Power Limiting (RAPL) Interface */ 389 390#define MSR_VR_CURRENT_CONFIG 0x00000601 391#define MSR_RAPL_POWER_UNIT 0x00000606 392 393#define MSR_PKG_POWER_LIMIT 0x00000610 394#define MSR_PKG_ENERGY_STATUS 0x00000611 395#define MSR_PKG_PERF_STATUS 0x00000613 396#define MSR_PKG_POWER_INFO 0x00000614 397 398#define MSR_DRAM_POWER_LIMIT 0x00000618 399#define MSR_DRAM_ENERGY_STATUS 0x00000619 400#define MSR_DRAM_PERF_STATUS 0x0000061b 401#define MSR_DRAM_POWER_INFO 0x0000061c 402 403#define MSR_PP0_POWER_LIMIT 0x00000638 404#define MSR_PP0_ENERGY_STATUS 0x00000639 405#define MSR_PP0_POLICY 0x0000063a 406#define MSR_PP0_PERF_STATUS 0x0000063b 407 408#define MSR_PP1_POWER_LIMIT 0x00000640 409#define MSR_PP1_ENERGY_STATUS 0x00000641 410#define MSR_PP1_POLICY 0x00000642 411 412#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 413#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 414#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 415 416/* Config TDP MSRs */ 417#define MSR_CONFIG_TDP_NOMINAL 0x00000648 418#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 419#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 420#define MSR_CONFIG_TDP_CONTROL 0x0000064B 421#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 422 423#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 424#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 425 426#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 427#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 428#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 429#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 430 431#define MSR_CORE_C1_RES 0x00000660 432#define MSR_MODULE_C6_RES_MS 0x00000664 433 434#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 435#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 436 437#define MSR_ATOM_CORE_RATIOS 0x0000066a 438#define MSR_ATOM_CORE_VIDS 0x0000066b 439#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 440#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 441 442#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 443#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 444#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 445 446/* Control-flow Enforcement Technology MSRs */ 447#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 448#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 449#define CET_SHSTK_EN BIT_ULL(0) 450#define CET_WRSS_EN BIT_ULL(1) 451#define CET_ENDBR_EN BIT_ULL(2) 452#define CET_LEG_IW_EN BIT_ULL(3) 453#define CET_NO_TRACK_EN BIT_ULL(4) 454#define CET_SUPPRESS_DISABLE BIT_ULL(5) 455#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 456#define CET_SUPPRESS BIT_ULL(10) 457#define CET_WAIT_ENDBR BIT_ULL(11) 458 459#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 460#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 461#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 462#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 463#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 464 465/* Hardware P state interface */ 466#define MSR_PPERF 0x0000064e 467#define MSR_PERF_LIMIT_REASONS 0x0000064f 468#define MSR_PM_ENABLE 0x00000770 469#define MSR_HWP_CAPABILITIES 0x00000771 470#define MSR_HWP_REQUEST_PKG 0x00000772 471#define MSR_HWP_INTERRUPT 0x00000773 472#define MSR_HWP_REQUEST 0x00000774 473#define MSR_HWP_STATUS 0x00000777 474 475/* CPUID.6.EAX */ 476#define HWP_BASE_BIT (1<<7) 477#define HWP_NOTIFICATIONS_BIT (1<<8) 478#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 479#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 480#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 481 482/* IA32_HWP_CAPABILITIES */ 483#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 484#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 485#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 486#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 487 488/* IA32_HWP_REQUEST */ 489#define HWP_MIN_PERF(x) (x & 0xff) 490#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 491#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 492#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 493#define HWP_EPP_PERFORMANCE 0x00 494#define HWP_EPP_BALANCE_PERFORMANCE 0x80 495#define HWP_EPP_BALANCE_POWERSAVE 0xC0 496#define HWP_EPP_POWERSAVE 0xFF 497#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 498#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 499 500/* IA32_HWP_STATUS */ 501#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 502#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 503 504/* IA32_HWP_INTERRUPT */ 505#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 506#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 507 508#define MSR_AMD64_MC0_MASK 0xc0010044 509 510#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 511#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 512#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 513#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 514 515#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 516 517/* These are consecutive and not in the normal 4er MCE bank block */ 518#define MSR_IA32_MC0_CTL2 0x00000280 519#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 520 521#define MSR_P6_PERFCTR0 0x000000c1 522#define MSR_P6_PERFCTR1 0x000000c2 523#define MSR_P6_EVNTSEL0 0x00000186 524#define MSR_P6_EVNTSEL1 0x00000187 525 526#define MSR_KNC_PERFCTR0 0x00000020 527#define MSR_KNC_PERFCTR1 0x00000021 528#define MSR_KNC_EVNTSEL0 0x00000028 529#define MSR_KNC_EVNTSEL1 0x00000029 530 531/* Alternative perfctr range with full access. */ 532#define MSR_IA32_PMC0 0x000004c1 533 534/* Auto-reload via MSR instead of DS area */ 535#define MSR_RELOAD_PMC0 0x000014c1 536#define MSR_RELOAD_FIXED_CTR0 0x00001309 537 538/* 539 * AMD64 MSRs. Not complete. See the architecture manual for a more 540 * complete list. 541 */ 542#define MSR_AMD64_PATCH_LEVEL 0x0000008b 543#define MSR_AMD64_TSC_RATIO 0xc0000104 544#define MSR_AMD64_NB_CFG 0xc001001f 545#define MSR_AMD64_PATCH_LOADER 0xc0010020 546#define MSR_AMD_PERF_CTL 0xc0010062 547#define MSR_AMD_PERF_STATUS 0xc0010063 548#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 549#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 550#define MSR_AMD64_OSVW_STATUS 0xc0010141 551#define MSR_AMD_PPIN_CTL 0xc00102f0 552#define MSR_AMD_PPIN 0xc00102f1 553#define MSR_AMD64_CPUID_FN_1 0xc0011004 554#define MSR_AMD64_LS_CFG 0xc0011020 555#define MSR_AMD64_DC_CFG 0xc0011022 556 557#define MSR_AMD64_DE_CFG 0xc0011029 558#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 559#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 560#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 561 562#define MSR_AMD64_BU_CFG2 0xc001102a 563#define MSR_AMD64_IBSFETCHCTL 0xc0011030 564#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 565#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 566#define MSR_AMD64_IBSFETCH_REG_COUNT 3 567#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 568#define MSR_AMD64_IBSOPCTL 0xc0011033 569#define MSR_AMD64_IBSOPRIP 0xc0011034 570#define MSR_AMD64_IBSOPDATA 0xc0011035 571#define MSR_AMD64_IBSOPDATA2 0xc0011036 572#define MSR_AMD64_IBSOPDATA3 0xc0011037 573#define MSR_AMD64_IBSDCLINAD 0xc0011038 574#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 575#define MSR_AMD64_IBSOP_REG_COUNT 7 576#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 577#define MSR_AMD64_IBSCTL 0xc001103a 578#define MSR_AMD64_IBSBRTARGET 0xc001103b 579#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 580#define MSR_AMD64_IBSOPDATA4 0xc001103d 581#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 582#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 583#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 584#define MSR_AMD64_SEV_ES_GHCB 0xc0010130 585#define MSR_AMD64_SEV 0xc0010131 586#define MSR_AMD64_SEV_ENABLED_BIT 0 587#define MSR_AMD64_SEV_ES_ENABLED_BIT 1 588#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 589#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 590#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 591#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 592 593/* SNP feature bits enabled by the hypervisor */ 594#define MSR_AMD64_SNP_VTOM BIT_ULL(3) 595#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) 596#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) 597#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) 598#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) 599#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) 600#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) 601#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) 602#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) 603#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) 604#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) 605#define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) 606#define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) 607 608/* SNP feature bits reserved for future use. */ 609#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) 610#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) 611#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) 612 613#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 614 615/* AMD Collaborative Processor Performance Control MSRs */ 616#define MSR_AMD_CPPC_CAP1 0xc00102b0 617#define MSR_AMD_CPPC_ENABLE 0xc00102b1 618#define MSR_AMD_CPPC_CAP2 0xc00102b2 619#define MSR_AMD_CPPC_REQ 0xc00102b3 620#define MSR_AMD_CPPC_STATUS 0xc00102b4 621 622#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 623#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 624#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 625#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 626 627#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 628#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 629#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 630#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 631 632/* AMD Performance Counter Global Status and Control MSRs */ 633#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 634#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 635#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 636 637/* AMD Last Branch Record MSRs */ 638#define MSR_AMD64_LBR_SELECT 0xc000010e 639 640/* Fam 17h MSRs */ 641#define MSR_F17H_IRPERF 0xc00000e9 642 643#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 644#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 645 646/* Fam 16h MSRs */ 647#define MSR_F16H_L2I_PERF_CTL 0xc0010230 648#define MSR_F16H_L2I_PERF_CTR 0xc0010231 649#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 650#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 651#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 652#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 653 654/* Fam 15h MSRs */ 655#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 656#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 657#define MSR_F15H_PERF_CTL 0xc0010200 658#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 659#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 660#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 661#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 662#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 663#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 664 665#define MSR_F15H_PERF_CTR 0xc0010201 666#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 667#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 668#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 669#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 670#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 671#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 672 673#define MSR_F15H_NB_PERF_CTL 0xc0010240 674#define MSR_F15H_NB_PERF_CTR 0xc0010241 675#define MSR_F15H_PTSC 0xc0010280 676#define MSR_F15H_IC_CFG 0xc0011021 677#define MSR_F15H_EX_CFG 0xc001102c 678 679/* Fam 10h MSRs */ 680#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 681#define FAM10H_MMIO_CONF_ENABLE (1<<0) 682#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 683#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 684#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 685#define FAM10H_MMIO_CONF_BASE_SHIFT 20 686#define MSR_FAM10H_NODE_ID 0xc001100c 687 688/* K8 MSRs */ 689#define MSR_K8_TOP_MEM1 0xc001001a 690#define MSR_K8_TOP_MEM2 0xc001001d 691#define MSR_AMD64_SYSCFG 0xc0010010 692#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 693#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 694#define MSR_K8_INT_PENDING_MSG 0xc0010055 695/* C1E active bits in int pending message */ 696#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 697#define MSR_K8_TSEG_ADDR 0xc0010112 698#define MSR_K8_TSEG_MASK 0xc0010113 699#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 700#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 701#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 702 703/* K7 MSRs */ 704#define MSR_K7_EVNTSEL0 0xc0010000 705#define MSR_K7_PERFCTR0 0xc0010004 706#define MSR_K7_EVNTSEL1 0xc0010001 707#define MSR_K7_PERFCTR1 0xc0010005 708#define MSR_K7_EVNTSEL2 0xc0010002 709#define MSR_K7_PERFCTR2 0xc0010006 710#define MSR_K7_EVNTSEL3 0xc0010003 711#define MSR_K7_PERFCTR3 0xc0010007 712#define MSR_K7_CLK_CTL 0xc001001b 713#define MSR_K7_HWCR 0xc0010015 714#define MSR_K7_HWCR_SMMLOCK_BIT 0 715#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 716#define MSR_K7_HWCR_IRPERF_EN_BIT 30 717#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 718#define MSR_K7_FID_VID_CTL 0xc0010041 719#define MSR_K7_FID_VID_STATUS 0xc0010042 720 721/* K6 MSRs */ 722#define MSR_K6_WHCR 0xc0000082 723#define MSR_K6_UWCCR 0xc0000085 724#define MSR_K6_EPMR 0xc0000086 725#define MSR_K6_PSOR 0xc0000087 726#define MSR_K6_PFIR 0xc0000088 727 728/* Centaur-Hauls/IDT defined MSRs. */ 729#define MSR_IDT_FCR1 0x00000107 730#define MSR_IDT_FCR2 0x00000108 731#define MSR_IDT_FCR3 0x00000109 732#define MSR_IDT_FCR4 0x0000010a 733 734#define MSR_IDT_MCR0 0x00000110 735#define MSR_IDT_MCR1 0x00000111 736#define MSR_IDT_MCR2 0x00000112 737#define MSR_IDT_MCR3 0x00000113 738#define MSR_IDT_MCR4 0x00000114 739#define MSR_IDT_MCR5 0x00000115 740#define MSR_IDT_MCR6 0x00000116 741#define MSR_IDT_MCR7 0x00000117 742#define MSR_IDT_MCR_CTRL 0x00000120 743 744/* VIA Cyrix defined MSRs*/ 745#define MSR_VIA_FCR 0x00001107 746#define MSR_VIA_LONGHAUL 0x0000110a 747#define MSR_VIA_RNG 0x0000110b 748#define MSR_VIA_BCR2 0x00001147 749 750/* Transmeta defined MSRs */ 751#define MSR_TMTA_LONGRUN_CTRL 0x80868010 752#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 753#define MSR_TMTA_LRTI_READOUT 0x80868018 754#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 755 756/* Intel defined MSRs. */ 757#define MSR_IA32_P5_MC_ADDR 0x00000000 758#define MSR_IA32_P5_MC_TYPE 0x00000001 759#define MSR_IA32_TSC 0x00000010 760#define MSR_IA32_PLATFORM_ID 0x00000017 761#define MSR_IA32_EBL_CR_POWERON 0x0000002a 762#define MSR_EBC_FREQUENCY_ID 0x0000002c 763#define MSR_SMI_COUNT 0x00000034 764 765/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 766#define MSR_IA32_FEAT_CTL 0x0000003a 767#define FEAT_CTL_LOCKED BIT(0) 768#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 769#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 770#define FEAT_CTL_SGX_LC_ENABLED BIT(17) 771#define FEAT_CTL_SGX_ENABLED BIT(18) 772#define FEAT_CTL_LMCE_ENABLED BIT(20) 773 774#define MSR_IA32_TSC_ADJUST 0x0000003b 775#define MSR_IA32_BNDCFGS 0x00000d90 776 777#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 778 779#define MSR_IA32_XFD 0x000001c4 780#define MSR_IA32_XFD_ERR 0x000001c5 781#define MSR_IA32_XSS 0x00000da0 782 783#define MSR_IA32_APICBASE 0x0000001b 784#define MSR_IA32_APICBASE_BSP (1<<8) 785#define MSR_IA32_APICBASE_ENABLE (1<<11) 786#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 787 788#define MSR_IA32_UCODE_WRITE 0x00000079 789#define MSR_IA32_UCODE_REV 0x0000008b 790 791/* Intel SGX Launch Enclave Public Key Hash MSRs */ 792#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 793#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 794#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 795#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 796 797#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 798#define MSR_IA32_SMBASE 0x0000009e 799 800#define MSR_IA32_PERF_STATUS 0x00000198 801#define MSR_IA32_PERF_CTL 0x00000199 802#define INTEL_PERF_CTL_MASK 0xffff 803 804/* AMD Branch Sampling configuration */ 805#define MSR_AMD_DBG_EXTN_CFG 0xc000010f 806#define MSR_AMD_SAMP_BR_FROM 0xc0010300 807 808#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 809 810#define MSR_IA32_MPERF 0x000000e7 811#define MSR_IA32_APERF 0x000000e8 812 813#define MSR_IA32_THERM_CONTROL 0x0000019a 814#define MSR_IA32_THERM_INTERRUPT 0x0000019b 815 816#define THERM_INT_HIGH_ENABLE (1 << 0) 817#define THERM_INT_LOW_ENABLE (1 << 1) 818#define THERM_INT_PLN_ENABLE (1 << 24) 819 820#define MSR_IA32_THERM_STATUS 0x0000019c 821 822#define THERM_STATUS_PROCHOT (1 << 0) 823#define THERM_STATUS_POWER_LIMIT (1 << 10) 824 825#define MSR_THERM2_CTL 0x0000019d 826 827#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 828 829#define MSR_IA32_MISC_ENABLE 0x000001a0 830 831#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 832 833#define MSR_MISC_FEATURE_CONTROL 0x000001a4 834#define MSR_MISC_PWR_MGMT 0x000001aa 835 836#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 837#define ENERGY_PERF_BIAS_PERFORMANCE 0 838#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 839#define ENERGY_PERF_BIAS_NORMAL 6 840#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 841#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 842#define ENERGY_PERF_BIAS_POWERSAVE 15 843 844#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 845 846#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 847#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 848#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 849 850#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 851 852#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 853#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 854#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 855#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 856 857/* Thermal Thresholds Support */ 858#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 859#define THERM_SHIFT_THRESHOLD0 8 860#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 861#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 862#define THERM_SHIFT_THRESHOLD1 16 863#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 864#define THERM_STATUS_THRESHOLD0 (1 << 6) 865#define THERM_LOG_THRESHOLD0 (1 << 7) 866#define THERM_STATUS_THRESHOLD1 (1 << 8) 867#define THERM_LOG_THRESHOLD1 (1 << 9) 868 869/* MISC_ENABLE bits: architectural */ 870#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 871#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 872#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 873#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 874#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 875#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 876#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 877#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 878#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 879#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 880#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 881#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 882#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 883#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 884#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 885#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 886#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 887#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 888#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 889#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 890 891/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 892#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 893#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 894#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 895#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 896#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 897#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 898#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 899#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 900#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 901#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 902#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 903#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 904#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 905#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 906#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 907#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 908#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 909#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 910#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 911#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 912#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 913#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 914#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 915#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 916#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 917#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 918#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 919#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 920#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 921#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 922 923/* MISC_FEATURES_ENABLES non-architectural features */ 924#define MSR_MISC_FEATURES_ENABLES 0x00000140 925 926#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 927#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 928#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 929 930#define MSR_IA32_TSC_DEADLINE 0x000006E0 931 932 933#define MSR_TSX_FORCE_ABORT 0x0000010F 934 935#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 936#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 937#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 938#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 939#define MSR_TFA_SDV_ENABLE_RTM_BIT 2 940#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 941 942/* P4/Xeon+ specific */ 943#define MSR_IA32_MCG_EAX 0x00000180 944#define MSR_IA32_MCG_EBX 0x00000181 945#define MSR_IA32_MCG_ECX 0x00000182 946#define MSR_IA32_MCG_EDX 0x00000183 947#define MSR_IA32_MCG_ESI 0x00000184 948#define MSR_IA32_MCG_EDI 0x00000185 949#define MSR_IA32_MCG_EBP 0x00000186 950#define MSR_IA32_MCG_ESP 0x00000187 951#define MSR_IA32_MCG_EFLAGS 0x00000188 952#define MSR_IA32_MCG_EIP 0x00000189 953#define MSR_IA32_MCG_RESERVED 0x0000018a 954 955/* Pentium IV performance counter MSRs */ 956#define MSR_P4_BPU_PERFCTR0 0x00000300 957#define MSR_P4_BPU_PERFCTR1 0x00000301 958#define MSR_P4_BPU_PERFCTR2 0x00000302 959#define MSR_P4_BPU_PERFCTR3 0x00000303 960#define MSR_P4_MS_PERFCTR0 0x00000304 961#define MSR_P4_MS_PERFCTR1 0x00000305 962#define MSR_P4_MS_PERFCTR2 0x00000306 963#define MSR_P4_MS_PERFCTR3 0x00000307 964#define MSR_P4_FLAME_PERFCTR0 0x00000308 965#define MSR_P4_FLAME_PERFCTR1 0x00000309 966#define MSR_P4_FLAME_PERFCTR2 0x0000030a 967#define MSR_P4_FLAME_PERFCTR3 0x0000030b 968#define MSR_P4_IQ_PERFCTR0 0x0000030c 969#define MSR_P4_IQ_PERFCTR1 0x0000030d 970#define MSR_P4_IQ_PERFCTR2 0x0000030e 971#define MSR_P4_IQ_PERFCTR3 0x0000030f 972#define MSR_P4_IQ_PERFCTR4 0x00000310 973#define MSR_P4_IQ_PERFCTR5 0x00000311 974#define MSR_P4_BPU_CCCR0 0x00000360 975#define MSR_P4_BPU_CCCR1 0x00000361 976#define MSR_P4_BPU_CCCR2 0x00000362 977#define MSR_P4_BPU_CCCR3 0x00000363 978#define MSR_P4_MS_CCCR0 0x00000364 979#define MSR_P4_MS_CCCR1 0x00000365 980#define MSR_P4_MS_CCCR2 0x00000366 981#define MSR_P4_MS_CCCR3 0x00000367 982#define MSR_P4_FLAME_CCCR0 0x00000368 983#define MSR_P4_FLAME_CCCR1 0x00000369 984#define MSR_P4_FLAME_CCCR2 0x0000036a 985#define MSR_P4_FLAME_CCCR3 0x0000036b 986#define MSR_P4_IQ_CCCR0 0x0000036c 987#define MSR_P4_IQ_CCCR1 0x0000036d 988#define MSR_P4_IQ_CCCR2 0x0000036e 989#define MSR_P4_IQ_CCCR3 0x0000036f 990#define MSR_P4_IQ_CCCR4 0x00000370 991#define MSR_P4_IQ_CCCR5 0x00000371 992#define MSR_P4_ALF_ESCR0 0x000003ca 993#define MSR_P4_ALF_ESCR1 0x000003cb 994#define MSR_P4_BPU_ESCR0 0x000003b2 995#define MSR_P4_BPU_ESCR1 0x000003b3 996#define MSR_P4_BSU_ESCR0 0x000003a0 997#define MSR_P4_BSU_ESCR1 0x000003a1 998#define MSR_P4_CRU_ESCR0 0x000003b8 999#define MSR_P4_CRU_ESCR1 0x000003b9 1000#define MSR_P4_CRU_ESCR2 0x000003cc 1001#define MSR_P4_CRU_ESCR3 0x000003cd 1002#define MSR_P4_CRU_ESCR4 0x000003e0 1003#define MSR_P4_CRU_ESCR5 0x000003e1 1004#define MSR_P4_DAC_ESCR0 0x000003a8 1005#define MSR_P4_DAC_ESCR1 0x000003a9 1006#define MSR_P4_FIRM_ESCR0 0x000003a4 1007#define MSR_P4_FIRM_ESCR1 0x000003a5 1008#define MSR_P4_FLAME_ESCR0 0x000003a6 1009#define MSR_P4_FLAME_ESCR1 0x000003a7 1010#define MSR_P4_FSB_ESCR0 0x000003a2 1011#define MSR_P4_FSB_ESCR1 0x000003a3 1012#define MSR_P4_IQ_ESCR0 0x000003ba 1013#define MSR_P4_IQ_ESCR1 0x000003bb 1014#define MSR_P4_IS_ESCR0 0x000003b4 1015#define MSR_P4_IS_ESCR1 0x000003b5 1016#define MSR_P4_ITLB_ESCR0 0x000003b6 1017#define MSR_P4_ITLB_ESCR1 0x000003b7 1018#define MSR_P4_IX_ESCR0 0x000003c8 1019#define MSR_P4_IX_ESCR1 0x000003c9 1020#define MSR_P4_MOB_ESCR0 0x000003aa 1021#define MSR_P4_MOB_ESCR1 0x000003ab 1022#define MSR_P4_MS_ESCR0 0x000003c0 1023#define MSR_P4_MS_ESCR1 0x000003c1 1024#define MSR_P4_PMH_ESCR0 0x000003ac 1025#define MSR_P4_PMH_ESCR1 0x000003ad 1026#define MSR_P4_RAT_ESCR0 0x000003bc 1027#define MSR_P4_RAT_ESCR1 0x000003bd 1028#define MSR_P4_SAAT_ESCR0 0x000003ae 1029#define MSR_P4_SAAT_ESCR1 0x000003af 1030#define MSR_P4_SSU_ESCR0 0x000003be 1031#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 1032 1033#define MSR_P4_TBPU_ESCR0 0x000003c2 1034#define MSR_P4_TBPU_ESCR1 0x000003c3 1035#define MSR_P4_TC_ESCR0 0x000003c4 1036#define MSR_P4_TC_ESCR1 0x000003c5 1037#define MSR_P4_U2L_ESCR0 0x000003b0 1038#define MSR_P4_U2L_ESCR1 0x000003b1 1039 1040#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1041 1042/* Intel Core-based CPU performance counters */ 1043#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1044#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1045#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 1046#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1047#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1048#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1049#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1050#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1051 1052#define MSR_PERF_METRICS 0x00000329 1053 1054/* PERF_GLOBAL_OVF_CTL bits */ 1055#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1056#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1057#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1058#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1059#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1060#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1061 1062/* Geode defined MSRs */ 1063#define MSR_GEODE_BUSCONT_CONF0 0x00001900 1064 1065/* Intel VT MSRs */ 1066#define MSR_IA32_VMX_BASIC 0x00000480 1067#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1068#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1069#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1070#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1071#define MSR_IA32_VMX_MISC 0x00000485 1072#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1073#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1074#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1075#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1076#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1077#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1078#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1079#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1080#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1081#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1082#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1083#define MSR_IA32_VMX_VMFUNC 0x00000491 1084#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1085 1086/* VMX_BASIC bits and bitmasks */ 1087#define VMX_BASIC_VMCS_SIZE_SHIFT 32 1088#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1089#define VMX_BASIC_64 0x0001000000000000LLU 1090#define VMX_BASIC_MEM_TYPE_SHIFT 50 1091#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1092#define VMX_BASIC_MEM_TYPE_WB 6LLU 1093#define VMX_BASIC_INOUT 0x0040000000000000LLU 1094 1095/* Resctrl MSRs: */ 1096/* - Intel: */ 1097#define MSR_IA32_L3_QOS_CFG 0xc81 1098#define MSR_IA32_L2_QOS_CFG 0xc82 1099#define MSR_IA32_QM_EVTSEL 0xc8d 1100#define MSR_IA32_QM_CTR 0xc8e 1101#define MSR_IA32_PQR_ASSOC 0xc8f 1102#define MSR_IA32_L3_CBM_BASE 0xc90 1103#define MSR_IA32_L2_CBM_BASE 0xd10 1104#define MSR_IA32_MBA_THRTL_BASE 0xd50 1105 1106/* - AMD: */ 1107#define MSR_IA32_MBA_BW_BASE 0xc0000200 1108#define MSR_IA32_SMBA_BW_BASE 0xc0000280 1109#define MSR_IA32_EVT_CFG_BASE 0xc0000400 1110 1111/* MSR_IA32_VMX_MISC bits */ 1112#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1113#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1114#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1115/* AMD-V MSRs */ 1116 1117#define MSR_VM_CR 0xc0010114 1118#define MSR_VM_IGNNE 0xc0010115 1119#define MSR_VM_HSAVE_PA 0xc0010117 1120 1121/* Hardware Feedback Interface */ 1122#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1123#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1124 1125/* x2APIC locked status */ 1126#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1127#define LEGACY_XAPIC_DISABLED BIT(0) /* 1128 * x2APIC mode is locked and 1129 * disabling x2APIC will cause 1130 * a #GP 1131 */ 1132 1133#endif /* _ASM_X86_MSR_INDEX_H */ 1134