162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci#ifndef _TOOLS_LINUX_ASM_X86_BARRIER_H 362306a36Sopenharmony_ci#define _TOOLS_LINUX_ASM_X86_BARRIER_H 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci/* 662306a36Sopenharmony_ci * Copied from the Linux kernel sources, and also moving code 762306a36Sopenharmony_ci * out from tools/perf/perf-sys.h so as to make it be located 862306a36Sopenharmony_ci * in a place similar as in the kernel sources. 962306a36Sopenharmony_ci * 1062306a36Sopenharmony_ci * Force strict CPU ordering. 1162306a36Sopenharmony_ci * And yes, this is required on UP too when we're talking 1262306a36Sopenharmony_ci * to devices. 1362306a36Sopenharmony_ci */ 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#if defined(__i386__) 1662306a36Sopenharmony_ci/* 1762306a36Sopenharmony_ci * Some non-Intel clones support out of order store. wmb() ceases to be a 1862306a36Sopenharmony_ci * nop for these. 1962306a36Sopenharmony_ci */ 2062306a36Sopenharmony_ci#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 2162306a36Sopenharmony_ci#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 2262306a36Sopenharmony_ci#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 2362306a36Sopenharmony_ci#elif defined(__x86_64__) 2462306a36Sopenharmony_ci#define mb() asm volatile("mfence" ::: "memory") 2562306a36Sopenharmony_ci#define rmb() asm volatile("lfence" ::: "memory") 2662306a36Sopenharmony_ci#define wmb() asm volatile("sfence" ::: "memory") 2762306a36Sopenharmony_ci#define smp_rmb() barrier() 2862306a36Sopenharmony_ci#define smp_wmb() barrier() 2962306a36Sopenharmony_ci#define smp_mb() asm volatile("lock; addl $0,-132(%%rsp)" ::: "memory", "cc") 3062306a36Sopenharmony_ci#endif 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci#if defined(__x86_64__) 3362306a36Sopenharmony_ci#define smp_store_release(p, v) \ 3462306a36Sopenharmony_cido { \ 3562306a36Sopenharmony_ci barrier(); \ 3662306a36Sopenharmony_ci WRITE_ONCE(*p, v); \ 3762306a36Sopenharmony_ci} while (0) 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#define smp_load_acquire(p) \ 4062306a36Sopenharmony_ci({ \ 4162306a36Sopenharmony_ci typeof(*p) ___p1 = READ_ONCE(*p); \ 4262306a36Sopenharmony_ci barrier(); \ 4362306a36Sopenharmony_ci ___p1; \ 4462306a36Sopenharmony_ci}) 4562306a36Sopenharmony_ci#endif /* defined(__x86_64__) */ 4662306a36Sopenharmony_ci#endif /* _TOOLS_LINUX_ASM_X86_BARRIER_H */ 47