162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copied from the kernel sources: 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 662306a36Sopenharmony_ci * Copyright (C) 2002 Paul Mundt 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci#ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H 962306a36Sopenharmony_ci#define __TOOLS_LINUX_ASM_SH_BARRIER_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* 1262306a36Sopenharmony_ci * A brief note on ctrl_barrier(), the control register write barrier. 1362306a36Sopenharmony_ci * 1462306a36Sopenharmony_ci * Legacy SH cores typically require a sequence of 8 nops after 1562306a36Sopenharmony_ci * modification of a control register in order for the changes to take 1662306a36Sopenharmony_ci * effect. On newer cores (like the sh4a and sh5) this is accomplished 1762306a36Sopenharmony_ci * with icbi. 1862306a36Sopenharmony_ci * 1962306a36Sopenharmony_ci * Also note that on sh4a in the icbi case we can forego a synco for the 2062306a36Sopenharmony_ci * write barrier, as it's not necessary for control registers. 2162306a36Sopenharmony_ci * 2262306a36Sopenharmony_ci * Historically we have only done this type of barrier for the MMUCR, but 2362306a36Sopenharmony_ci * it's also necessary for the CCR, so we make it generic here instead. 2462306a36Sopenharmony_ci */ 2562306a36Sopenharmony_ci#if defined(__SH4A__) 2662306a36Sopenharmony_ci#define mb() __asm__ __volatile__ ("synco": : :"memory") 2762306a36Sopenharmony_ci#define rmb() mb() 2862306a36Sopenharmony_ci#define wmb() mb() 2962306a36Sopenharmony_ci#endif 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci#include <asm-generic/barrier.h> 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */ 34