162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copied from the kernel sources: 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright IBM Corp. 1999, 2009 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef __TOOLS_LINUX_ASM_BARRIER_H 1162306a36Sopenharmony_ci#define __TOOLS_LINUX_ASM_BARRIER_H 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* 1462306a36Sopenharmony_ci * Force strict CPU ordering. 1562306a36Sopenharmony_ci * And yes, this is required on UP too when we're talking 1662306a36Sopenharmony_ci * to devices. 1762306a36Sopenharmony_ci */ 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES 2062306a36Sopenharmony_ci/* Fast-BCR without checkpoint synchronization */ 2162306a36Sopenharmony_ci#define __ASM_BARRIER "bcr 14,0\n" 2262306a36Sopenharmony_ci#else 2362306a36Sopenharmony_ci#define __ASM_BARRIER "bcr 15,0\n" 2462306a36Sopenharmony_ci#endif 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0) 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci#define rmb() mb() 2962306a36Sopenharmony_ci#define wmb() mb() 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci#define smp_store_release(p, v) \ 3262306a36Sopenharmony_cido { \ 3362306a36Sopenharmony_ci barrier(); \ 3462306a36Sopenharmony_ci WRITE_ONCE(*p, v); \ 3562306a36Sopenharmony_ci} while (0) 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci#define smp_load_acquire(p) \ 3862306a36Sopenharmony_ci({ \ 3962306a36Sopenharmony_ci typeof(*p) ___p1 = READ_ONCE(*p); \ 4062306a36Sopenharmony_ci barrier(); \ 4162306a36Sopenharmony_ci ___p1; \ 4262306a36Sopenharmony_ci}) 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci#endif /* __TOOLS_LIB_ASM_BARRIER_H */ 45