162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copied from the kernel sources: 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci#ifndef _TOOLS_LINUX_ASM_POWERPC_BARRIER_H 862306a36Sopenharmony_ci#define _TOOLS_LINUX_ASM_POWERPC_BARRIER_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci/* 1162306a36Sopenharmony_ci * Memory barrier. 1262306a36Sopenharmony_ci * The sync instruction guarantees that all memory accesses initiated 1362306a36Sopenharmony_ci * by this processor have been performed (with respect to all other 1462306a36Sopenharmony_ci * mechanisms that access memory). The eieio instruction is a barrier 1562306a36Sopenharmony_ci * providing an ordering (separately) for (a) cacheable stores and (b) 1662306a36Sopenharmony_ci * loads and stores to non-cacheable memory (e.g. I/O devices). 1762306a36Sopenharmony_ci * 1862306a36Sopenharmony_ci * mb() prevents loads and stores being reordered across this point. 1962306a36Sopenharmony_ci * rmb() prevents loads being reordered across this point. 2062306a36Sopenharmony_ci * wmb() prevents stores being reordered across this point. 2162306a36Sopenharmony_ci * 2262306a36Sopenharmony_ci * *mb() variants without smp_ prefix must order all types of memory 2362306a36Sopenharmony_ci * operations with one another. sync is the only instruction sufficient 2462306a36Sopenharmony_ci * to do this. 2562306a36Sopenharmony_ci */ 2662306a36Sopenharmony_ci#define mb() __asm__ __volatile__ ("sync" : : : "memory") 2762306a36Sopenharmony_ci#define rmb() __asm__ __volatile__ ("sync" : : : "memory") 2862306a36Sopenharmony_ci#define wmb() __asm__ __volatile__ ("sync" : : : "memory") 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci#if defined(__powerpc64__) 3162306a36Sopenharmony_ci#define smp_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory") 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#define smp_store_release(p, v) \ 3462306a36Sopenharmony_cido { \ 3562306a36Sopenharmony_ci smp_lwsync(); \ 3662306a36Sopenharmony_ci WRITE_ONCE(*p, v); \ 3762306a36Sopenharmony_ci} while (0) 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#define smp_load_acquire(p) \ 4062306a36Sopenharmony_ci({ \ 4162306a36Sopenharmony_ci typeof(*p) ___p1 = READ_ONCE(*p); \ 4262306a36Sopenharmony_ci smp_lwsync(); \ 4362306a36Sopenharmony_ci ___p1; \ 4462306a36Sopenharmony_ci}) 4562306a36Sopenharmony_ci#endif /* defined(__powerpc64__) */ 4662306a36Sopenharmony_ci#endif /* _TOOLS_LINUX_ASM_POWERPC_BARRIER_H */ 47