1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9#ifndef __ASM_SYSREG_H 10#define __ASM_SYSREG_H 11 12#include <linux/bits.h> 13#include <linux/stringify.h> 14 15/* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25#define Op0_shift 19 26#define Op0_mask 0x3 27#define Op1_shift 16 28#define Op1_mask 0x7 29#define CRn_shift 12 30#define CRn_mask 0xf 31#define CRm_shift 8 32#define CRm_mask 0xf 33#define Op2_shift 5 34#define Op2_mask 0x7 35 36#define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41#define sys_insn sys_reg 42 43#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49#ifndef CONFIG_BROKEN_GAS_INST 50 51#ifdef __ASSEMBLY__ 52// The space separator is omitted so that __emit_inst(x) can be parsed as 53// either an assembler directive or an assembler macro argument. 54#define __emit_inst(x) .inst(x) 55#else 56#define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 57#endif 58 59#else /* CONFIG_BROKEN_GAS_INST */ 60 61#ifndef CONFIG_CPU_BIG_ENDIAN 62#define __INSTR_BSWAP(x) (x) 63#else /* CONFIG_CPU_BIG_ENDIAN */ 64#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 65 (((x) << 8) & 0x00ff0000) | \ 66 (((x) >> 8) & 0x0000ff00) | \ 67 (((x) >> 24) & 0x000000ff)) 68#endif /* CONFIG_CPU_BIG_ENDIAN */ 69 70#ifdef __ASSEMBLY__ 71#define __emit_inst(x) .long __INSTR_BSWAP(x) 72#else /* __ASSEMBLY__ */ 73#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 74#endif /* __ASSEMBLY__ */ 75 76#endif /* CONFIG_BROKEN_GAS_INST */ 77 78/* 79 * Instructions for modifying PSTATE fields. 80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 82 * for accessing PSTATE fields have the following encoding: 83 * Op0 = 0, CRn = 4 84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 85 * CRm = Imm4 for the instruction. 86 * Rt = 0x1f 87 */ 88#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 89#define PSTATE_Imm_shift CRm_shift 90 91#define PSTATE_PAN pstate_field(0, 4) 92#define PSTATE_UAO pstate_field(0, 3) 93#define PSTATE_SSBS pstate_field(3, 1) 94#define PSTATE_TCO pstate_field(3, 4) 95 96#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 97#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 98#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 99#define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 100 101#define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 102#define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 103#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 104 105#define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 107 108#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 109 110#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 111#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 112#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 113 114/* 115 * System registers, organised loosely by encoding but grouped together 116 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 117 */ 118#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 119#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 120#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 121#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 122#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 123#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 124#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 125#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 126#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 127#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 128#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 129#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 130#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 131#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 132#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 133#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 134#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 135#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 136#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 137#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 138#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 139#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 140 141#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 142#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 143#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 144 145#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 146#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 147#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 148#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 149#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 150#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 151#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 152#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 153#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 154#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 155#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 156#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 157 158#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 159#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 160#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 161#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 162#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 163#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 164#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 165 166#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 167#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 168#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 169 170#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 171#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 172#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 173 174#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 175#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 176 177#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 178#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 179 180#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 181#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 182 183#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 184#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 185#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 186 187#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 188#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 189#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 190#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 191#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 192 193#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 194#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 195 196#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 197#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 198#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 199 200#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 201#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 202#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 203#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 204 205#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 206#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 207#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 208#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 209 210#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 211#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 212 213#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 214#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 215 216#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 217 218#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 219#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 220#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 221 222#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 223#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 224#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 225#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 226#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 227#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 228#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 229#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 230#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 231#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 232 233#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 234#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 235 236#define SYS_PAR_EL1_F BIT(0) 237#define SYS_PAR_EL1_FST GENMASK(6, 1) 238 239/*** Statistical Profiling Extension ***/ 240/* ID registers */ 241#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 242#define SYS_PMSIDR_EL1_FE_SHIFT 0 243#define SYS_PMSIDR_EL1_FT_SHIFT 1 244#define SYS_PMSIDR_EL1_FL_SHIFT 2 245#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 246#define SYS_PMSIDR_EL1_LDS_SHIFT 4 247#define SYS_PMSIDR_EL1_ERND_SHIFT 5 248#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 249#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 250#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 251#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 252#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 253#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 254 255#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 256#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 257#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 258#define SYS_PMBIDR_EL1_P_SHIFT 4 259#define SYS_PMBIDR_EL1_F_SHIFT 5 260 261/* Sampling controls */ 262#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 263#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 264#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 265#define SYS_PMSCR_EL1_CX_SHIFT 3 266#define SYS_PMSCR_EL1_PA_SHIFT 4 267#define SYS_PMSCR_EL1_TS_SHIFT 5 268#define SYS_PMSCR_EL1_PCT_SHIFT 6 269 270#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 271#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 272#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 273#define SYS_PMSCR_EL2_CX_SHIFT 3 274#define SYS_PMSCR_EL2_PA_SHIFT 4 275#define SYS_PMSCR_EL2_TS_SHIFT 5 276#define SYS_PMSCR_EL2_PCT_SHIFT 6 277 278#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 279 280#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 281#define SYS_PMSIRR_EL1_RND_SHIFT 0 282#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 283#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 284 285/* Filtering controls */ 286#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) 287 288#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 289#define SYS_PMSFCR_EL1_FE_SHIFT 0 290#define SYS_PMSFCR_EL1_FT_SHIFT 1 291#define SYS_PMSFCR_EL1_FL_SHIFT 2 292#define SYS_PMSFCR_EL1_B_SHIFT 16 293#define SYS_PMSFCR_EL1_LD_SHIFT 17 294#define SYS_PMSFCR_EL1_ST_SHIFT 18 295 296#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 297#define SYS_PMSEVFR_EL1_RES0_8_2 \ 298 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 299 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 300#define SYS_PMSEVFR_EL1_RES0_8_3 \ 301 (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 302 303#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 304#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 305 306/* Buffer controls */ 307#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 308#define SYS_PMBLIMITR_EL1_E_SHIFT 0 309#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 310#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 311#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 312 313#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 314 315/* Buffer error reporting */ 316#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 317#define SYS_PMBSR_EL1_COLL_SHIFT 16 318#define SYS_PMBSR_EL1_S_SHIFT 17 319#define SYS_PMBSR_EL1_EA_SHIFT 18 320#define SYS_PMBSR_EL1_DL_SHIFT 19 321#define SYS_PMBSR_EL1_EC_SHIFT 26 322#define SYS_PMBSR_EL1_EC_MASK 0x3fUL 323 324#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 325#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 326#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 327 328#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 329#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 330 331#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 332#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 333 334#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 335 336/*** End of Statistical Profiling Extension ***/ 337 338/* 339 * TRBE Registers 340 */ 341#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) 342#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) 343#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) 344#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) 345#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) 346#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) 347#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) 348 349#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) 350#define TRBLIMITR_LIMIT_SHIFT 12 351#define TRBLIMITR_NVM BIT(5) 352#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) 353#define TRBLIMITR_TRIG_MODE_SHIFT 3 354#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) 355#define TRBLIMITR_FILL_MODE_SHIFT 1 356#define TRBLIMITR_ENABLE BIT(0) 357#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) 358#define TRBPTR_PTR_SHIFT 0 359#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) 360#define TRBBASER_BASE_SHIFT 12 361#define TRBSR_EC_MASK GENMASK(5, 0) 362#define TRBSR_EC_SHIFT 26 363#define TRBSR_IRQ BIT(22) 364#define TRBSR_TRG BIT(21) 365#define TRBSR_WRAP BIT(20) 366#define TRBSR_ABORT BIT(18) 367#define TRBSR_STOP BIT(17) 368#define TRBSR_MSS_MASK GENMASK(15, 0) 369#define TRBSR_MSS_SHIFT 0 370#define TRBSR_BSC_MASK GENMASK(5, 0) 371#define TRBSR_BSC_SHIFT 0 372#define TRBSR_FSC_MASK GENMASK(5, 0) 373#define TRBSR_FSC_SHIFT 0 374#define TRBMAR_SHARE_MASK GENMASK(1, 0) 375#define TRBMAR_SHARE_SHIFT 8 376#define TRBMAR_OUTER_MASK GENMASK(3, 0) 377#define TRBMAR_OUTER_SHIFT 4 378#define TRBMAR_INNER_MASK GENMASK(3, 0) 379#define TRBMAR_INNER_SHIFT 0 380#define TRBTRG_TRG_MASK GENMASK(31, 0) 381#define TRBTRG_TRG_SHIFT 0 382#define TRBIDR_FLAG BIT(5) 383#define TRBIDR_PROG BIT(4) 384#define TRBIDR_ALIGN_MASK GENMASK(3, 0) 385#define TRBIDR_ALIGN_SHIFT 0 386 387#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 388#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 389 390#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 391 392#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 393#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 394 395#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 396#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 397#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 398#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 399#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 400 401#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 402#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 403 404#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 405#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 406#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 407#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 408#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 409#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 410#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 411#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 412#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 413#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 414#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 415#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 416#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 417#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 418#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 419#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 420#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 421#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 422#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 423#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 424#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 425#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 426#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 427#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 428#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 429#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 430#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 431 432#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 433#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 434 435#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 436 437#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 438 439#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 440#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 441#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) 442#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 443 444#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 445 446#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 447#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 448 449#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 450#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 451 452#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 453#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 454#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 455#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 456#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 457#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 458#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 459#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 460#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 461#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 462#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 463#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 464#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 465 466#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 467#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 468 469#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 470 471/* Definitions for system register interface to AMU for ARMv8.4 onwards */ 472#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 473#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 474#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 475#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 476#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 477#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 478#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 479#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 480#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 481 482/* 483 * Group 0 of activity monitors (architected): 484 * op0 op1 CRn CRm op2 485 * Counter: 11 011 1101 010:n<3> n<2:0> 486 * Type: 11 011 1101 011:n<3> n<2:0> 487 * n: 0-15 488 * 489 * Group 1 of activity monitors (auxiliary): 490 * op0 op1 CRn CRm op2 491 * Counter: 11 011 1101 110:n<3> n<2:0> 492 * Type: 11 011 1101 111:n<3> n<2:0> 493 * n: 0-15 494 */ 495 496#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 497#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 498#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 499#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 500 501/* AMU v1: Fixed (architecturally defined) activity monitors */ 502#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 503#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 504#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 505#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 506 507#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 508 509#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 510#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 511#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 512 513#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 514#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 515 516#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 517#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 518#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 519 520#define __PMEV_op2(n) ((n) & 0x7) 521#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 522#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 523#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 524#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 525 526#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 527 528#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 529#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) 530#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) 531#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) 532#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 533#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 534#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 535#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 536#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 537#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 538#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 539#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 540#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 541#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 542#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 543#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 544#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 545#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 546 547#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 548#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 549#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 550#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 551#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 552#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 553 554#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 555#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 556#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 557#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 558#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 559 560#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 561#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 562#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 563#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 564#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 565#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 566#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 567#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 568 569#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 570#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 571#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 572#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 573#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 574#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 575#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 576#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 577#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 578 579#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 580#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 581#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 582#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 583#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 584#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 585#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 586#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 587#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 588 589/* VHE encodings for architectural EL0/1 system registers */ 590#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 591#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 592#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 593#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 594#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 595#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 596#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 597#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 598#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 599#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 600#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 601#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 602#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 603#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 604#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 605#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 606#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 607#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 608#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 609#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 610#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 611#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 612#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 613#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 614 615/* Common SCTLR_ELx flags. */ 616#define SCTLR_ELx_DSSBS (BIT(44)) 617#define SCTLR_ELx_ATA (BIT(43)) 618 619#define SCTLR_ELx_TCF_SHIFT 40 620#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) 621#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) 622#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) 623#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 624 625#define SCTLR_ELx_ENIA_SHIFT 31 626 627#define SCTLR_ELx_ITFSB (BIT(37)) 628#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 629#define SCTLR_ELx_ENIB (BIT(30)) 630#define SCTLR_ELx_ENDA (BIT(27)) 631#define SCTLR_ELx_EE (BIT(25)) 632#define SCTLR_ELx_IESB (BIT(21)) 633#define SCTLR_ELx_WXN (BIT(19)) 634#define SCTLR_ELx_ENDB (BIT(13)) 635#define SCTLR_ELx_I (BIT(12)) 636#define SCTLR_ELx_SA (BIT(3)) 637#define SCTLR_ELx_C (BIT(2)) 638#define SCTLR_ELx_A (BIT(1)) 639#define SCTLR_ELx_M (BIT(0)) 640 641/* SCTLR_EL2 specific flags. */ 642#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 643 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 644 (BIT(29))) 645 646#ifdef CONFIG_CPU_BIG_ENDIAN 647#define ENDIAN_SET_EL2 SCTLR_ELx_EE 648#else 649#define ENDIAN_SET_EL2 0 650#endif 651 652#define INIT_SCTLR_EL2_MMU_ON \ 653 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 654 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 655 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 656 657#define INIT_SCTLR_EL2_MMU_OFF \ 658 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 659 660/* SCTLR_EL1 specific flags. */ 661#define SCTLR_EL1_EPAN (BIT(57)) 662#define SCTLR_EL1_ATA0 (BIT(42)) 663 664#define SCTLR_EL1_TCF0_SHIFT 38 665#define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT) 666#define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT) 667#define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT) 668#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 669 670#define SCTLR_EL1_BT1 (BIT(36)) 671#define SCTLR_EL1_BT0 (BIT(35)) 672#define SCTLR_EL1_UCI (BIT(26)) 673#define SCTLR_EL1_E0E (BIT(24)) 674#define SCTLR_EL1_SPAN (BIT(23)) 675#define SCTLR_EL1_NTWE (BIT(18)) 676#define SCTLR_EL1_NTWI (BIT(16)) 677#define SCTLR_EL1_UCT (BIT(15)) 678#define SCTLR_EL1_DZE (BIT(14)) 679#define SCTLR_EL1_UMA (BIT(9)) 680#define SCTLR_EL1_SED (BIT(8)) 681#define SCTLR_EL1_ITD (BIT(7)) 682#define SCTLR_EL1_CP15BEN (BIT(5)) 683#define SCTLR_EL1_SA0 (BIT(4)) 684 685#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 686 (BIT(29))) 687 688#ifdef CONFIG_CPU_BIG_ENDIAN 689#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 690#else 691#define ENDIAN_SET_EL1 0 692#endif 693 694#define INIT_SCTLR_EL1_MMU_OFF \ 695 (ENDIAN_SET_EL1 | SCTLR_EL1_RES1) 696 697#define INIT_SCTLR_EL1_MMU_ON \ 698 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \ 699 SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \ 700 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 701 SCTLR_ELx_ATA | SCTLR_EL1_ATA0 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | \ 702 SCTLR_EL1_EPAN | SCTLR_EL1_RES1) 703 704/* MAIR_ELx memory attributes (used by Linux) */ 705#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 706#define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 707#define MAIR_ATTR_NORMAL_NC UL(0x44) 708#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 709#define MAIR_ATTR_NORMAL UL(0xff) 710#define MAIR_ATTR_MASK UL(0xff) 711 712/* Position the attr at the correct index */ 713#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 714 715/* id_aa64isar0 */ 716#define ID_AA64ISAR0_RNDR_SHIFT 60 717#define ID_AA64ISAR0_TLB_SHIFT 56 718#define ID_AA64ISAR0_TS_SHIFT 52 719#define ID_AA64ISAR0_FHM_SHIFT 48 720#define ID_AA64ISAR0_DP_SHIFT 44 721#define ID_AA64ISAR0_SM4_SHIFT 40 722#define ID_AA64ISAR0_SM3_SHIFT 36 723#define ID_AA64ISAR0_SHA3_SHIFT 32 724#define ID_AA64ISAR0_RDM_SHIFT 28 725#define ID_AA64ISAR0_ATOMICS_SHIFT 20 726#define ID_AA64ISAR0_CRC32_SHIFT 16 727#define ID_AA64ISAR0_SHA2_SHIFT 12 728#define ID_AA64ISAR0_SHA1_SHIFT 8 729#define ID_AA64ISAR0_AES_SHIFT 4 730 731#define ID_AA64ISAR0_TLB_RANGE_NI 0x0 732#define ID_AA64ISAR0_TLB_RANGE 0x2 733 734/* id_aa64isar1 */ 735#define ID_AA64ISAR1_I8MM_SHIFT 52 736#define ID_AA64ISAR1_DGH_SHIFT 48 737#define ID_AA64ISAR1_BF16_SHIFT 44 738#define ID_AA64ISAR1_SPECRES_SHIFT 40 739#define ID_AA64ISAR1_SB_SHIFT 36 740#define ID_AA64ISAR1_FRINTTS_SHIFT 32 741#define ID_AA64ISAR1_GPI_SHIFT 28 742#define ID_AA64ISAR1_GPA_SHIFT 24 743#define ID_AA64ISAR1_LRCPC_SHIFT 20 744#define ID_AA64ISAR1_FCMA_SHIFT 16 745#define ID_AA64ISAR1_JSCVT_SHIFT 12 746#define ID_AA64ISAR1_API_SHIFT 8 747#define ID_AA64ISAR1_APA_SHIFT 4 748#define ID_AA64ISAR1_DPB_SHIFT 0 749 750#define ID_AA64ISAR1_APA_NI 0x0 751#define ID_AA64ISAR1_APA_ARCHITECTED 0x1 752#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 753#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 754#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 755#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 756#define ID_AA64ISAR1_API_NI 0x0 757#define ID_AA64ISAR1_API_IMP_DEF 0x1 758#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 759#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 760#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 761#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 762#define ID_AA64ISAR1_GPA_NI 0x0 763#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 764#define ID_AA64ISAR1_GPI_NI 0x0 765#define ID_AA64ISAR1_GPI_IMP_DEF 0x1 766 767/* id_aa64pfr0 */ 768#define ID_AA64PFR0_CSV3_SHIFT 60 769#define ID_AA64PFR0_CSV2_SHIFT 56 770#define ID_AA64PFR0_DIT_SHIFT 48 771#define ID_AA64PFR0_AMU_SHIFT 44 772#define ID_AA64PFR0_MPAM_SHIFT 40 773#define ID_AA64PFR0_SEL2_SHIFT 36 774#define ID_AA64PFR0_SVE_SHIFT 32 775#define ID_AA64PFR0_RAS_SHIFT 28 776#define ID_AA64PFR0_GIC_SHIFT 24 777#define ID_AA64PFR0_ASIMD_SHIFT 20 778#define ID_AA64PFR0_FP_SHIFT 16 779#define ID_AA64PFR0_EL3_SHIFT 12 780#define ID_AA64PFR0_EL2_SHIFT 8 781#define ID_AA64PFR0_EL1_SHIFT 4 782#define ID_AA64PFR0_EL0_SHIFT 0 783 784#define ID_AA64PFR0_AMU 0x1 785#define ID_AA64PFR0_SVE 0x1 786#define ID_AA64PFR0_RAS_V1 0x1 787#define ID_AA64PFR0_RAS_V1P1 0x2 788#define ID_AA64PFR0_FP_NI 0xf 789#define ID_AA64PFR0_FP_SUPPORTED 0x0 790#define ID_AA64PFR0_ASIMD_NI 0xf 791#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 792#define ID_AA64PFR0_ELx_64BIT_ONLY 0x1 793#define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 794 795/* id_aa64pfr1 */ 796#define ID_AA64PFR1_MPAMFRAC_SHIFT 16 797#define ID_AA64PFR1_RASFRAC_SHIFT 12 798#define ID_AA64PFR1_MTE_SHIFT 8 799#define ID_AA64PFR1_SSBS_SHIFT 4 800#define ID_AA64PFR1_BT_SHIFT 0 801 802#define ID_AA64PFR1_SSBS_PSTATE_NI 0 803#define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 804#define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 805#define ID_AA64PFR1_BT_BTI 0x1 806 807#define ID_AA64PFR1_MTE_NI 0x0 808#define ID_AA64PFR1_MTE_EL0 0x1 809#define ID_AA64PFR1_MTE 0x2 810 811/* id_aa64zfr0 */ 812#define ID_AA64ZFR0_F64MM_SHIFT 56 813#define ID_AA64ZFR0_F32MM_SHIFT 52 814#define ID_AA64ZFR0_I8MM_SHIFT 44 815#define ID_AA64ZFR0_SM4_SHIFT 40 816#define ID_AA64ZFR0_SHA3_SHIFT 32 817#define ID_AA64ZFR0_BF16_SHIFT 20 818#define ID_AA64ZFR0_BITPERM_SHIFT 16 819#define ID_AA64ZFR0_AES_SHIFT 4 820#define ID_AA64ZFR0_SVEVER_SHIFT 0 821 822#define ID_AA64ZFR0_F64MM 0x1 823#define ID_AA64ZFR0_F32MM 0x1 824#define ID_AA64ZFR0_I8MM 0x1 825#define ID_AA64ZFR0_BF16 0x1 826#define ID_AA64ZFR0_SM4 0x1 827#define ID_AA64ZFR0_SHA3 0x1 828#define ID_AA64ZFR0_BITPERM 0x1 829#define ID_AA64ZFR0_AES 0x1 830#define ID_AA64ZFR0_AES_PMULL 0x2 831#define ID_AA64ZFR0_SVEVER_SVE2 0x1 832 833/* id_aa64mmfr0 */ 834#define ID_AA64MMFR0_ECV_SHIFT 60 835#define ID_AA64MMFR0_FGT_SHIFT 56 836#define ID_AA64MMFR0_EXS_SHIFT 44 837#define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 838#define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 839#define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 840#define ID_AA64MMFR0_TGRAN4_SHIFT 28 841#define ID_AA64MMFR0_TGRAN64_SHIFT 24 842#define ID_AA64MMFR0_TGRAN16_SHIFT 20 843#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 844#define ID_AA64MMFR0_SNSMEM_SHIFT 12 845#define ID_AA64MMFR0_BIGENDEL_SHIFT 8 846#define ID_AA64MMFR0_ASID_SHIFT 4 847#define ID_AA64MMFR0_PARANGE_SHIFT 0 848 849#define ID_AA64MMFR0_ASID_8 0x0 850#define ID_AA64MMFR0_ASID_16 0x2 851 852#define ID_AA64MMFR0_TGRAN4_NI 0xf 853#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 854#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 855#define ID_AA64MMFR0_TGRAN64_NI 0xf 856#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 857#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 858#define ID_AA64MMFR0_TGRAN16_NI 0x0 859#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 860#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf 861 862#define ID_AA64MMFR0_PARANGE_32 0x0 863#define ID_AA64MMFR0_PARANGE_36 0x1 864#define ID_AA64MMFR0_PARANGE_40 0x2 865#define ID_AA64MMFR0_PARANGE_42 0x3 866#define ID_AA64MMFR0_PARANGE_44 0x4 867#define ID_AA64MMFR0_PARANGE_48 0x5 868#define ID_AA64MMFR0_PARANGE_52 0x6 869 870#define ARM64_MIN_PARANGE_BITS 32 871 872#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 873#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 874#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 875#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 876 877#ifdef CONFIG_ARM64_PA_BITS_52 878#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 879#else 880#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 881#endif 882 883/* id_aa64mmfr1 */ 884#define ID_AA64MMFR1_ETS_SHIFT 36 885#define ID_AA64MMFR1_TWED_SHIFT 32 886#define ID_AA64MMFR1_XNX_SHIFT 28 887#define ID_AA64MMFR1_SPECSEI_SHIFT 24 888#define ID_AA64MMFR1_PAN_SHIFT 20 889#define ID_AA64MMFR1_LOR_SHIFT 16 890#define ID_AA64MMFR1_HPD_SHIFT 12 891#define ID_AA64MMFR1_VHE_SHIFT 8 892#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 893#define ID_AA64MMFR1_HADBS_SHIFT 0 894 895#define ID_AA64MMFR1_VMIDBITS_8 0 896#define ID_AA64MMFR1_VMIDBITS_16 2 897 898/* id_aa64mmfr2 */ 899#define ID_AA64MMFR2_E0PD_SHIFT 60 900#define ID_AA64MMFR2_EVT_SHIFT 56 901#define ID_AA64MMFR2_BBM_SHIFT 52 902#define ID_AA64MMFR2_TTL_SHIFT 48 903#define ID_AA64MMFR2_FWB_SHIFT 40 904#define ID_AA64MMFR2_IDS_SHIFT 36 905#define ID_AA64MMFR2_AT_SHIFT 32 906#define ID_AA64MMFR2_ST_SHIFT 28 907#define ID_AA64MMFR2_NV_SHIFT 24 908#define ID_AA64MMFR2_CCIDX_SHIFT 20 909#define ID_AA64MMFR2_LVA_SHIFT 16 910#define ID_AA64MMFR2_IESB_SHIFT 12 911#define ID_AA64MMFR2_LSM_SHIFT 8 912#define ID_AA64MMFR2_UAO_SHIFT 4 913#define ID_AA64MMFR2_CNP_SHIFT 0 914 915/* id_aa64dfr0 */ 916#define ID_AA64DFR0_MTPMU_SHIFT 48 917#define ID_AA64DFR0_TRBE_SHIFT 44 918#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 919#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 920#define ID_AA64DFR0_PMSVER_SHIFT 32 921#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 922#define ID_AA64DFR0_WRPS_SHIFT 20 923#define ID_AA64DFR0_BRPS_SHIFT 12 924#define ID_AA64DFR0_PMUVER_SHIFT 8 925#define ID_AA64DFR0_TRACEVER_SHIFT 4 926#define ID_AA64DFR0_DEBUGVER_SHIFT 0 927 928#define ID_AA64DFR0_PMUVER_8_0 0x1 929#define ID_AA64DFR0_PMUVER_8_1 0x4 930#define ID_AA64DFR0_PMUVER_8_4 0x5 931#define ID_AA64DFR0_PMUVER_8_5 0x6 932#define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 933 934#define ID_AA64DFR0_PMSVER_8_2 0x1 935#define ID_AA64DFR0_PMSVER_8_3 0x2 936 937#define ID_DFR0_PERFMON_SHIFT 24 938 939#define ID_DFR0_PERFMON_8_0 0x3 940#define ID_DFR0_PERFMON_8_1 0x4 941#define ID_DFR0_PERFMON_8_4 0x5 942#define ID_DFR0_PERFMON_8_5 0x6 943 944#define ID_ISAR4_SWP_FRAC_SHIFT 28 945#define ID_ISAR4_PSR_M_SHIFT 24 946#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 947#define ID_ISAR4_BARRIER_SHIFT 16 948#define ID_ISAR4_SMC_SHIFT 12 949#define ID_ISAR4_WRITEBACK_SHIFT 8 950#define ID_ISAR4_WITHSHIFTS_SHIFT 4 951#define ID_ISAR4_UNPRIV_SHIFT 0 952 953#define ID_DFR1_MTPMU_SHIFT 0 954 955#define ID_ISAR0_DIVIDE_SHIFT 24 956#define ID_ISAR0_DEBUG_SHIFT 20 957#define ID_ISAR0_COPROC_SHIFT 16 958#define ID_ISAR0_CMPBRANCH_SHIFT 12 959#define ID_ISAR0_BITFIELD_SHIFT 8 960#define ID_ISAR0_BITCOUNT_SHIFT 4 961#define ID_ISAR0_SWAP_SHIFT 0 962 963#define ID_ISAR5_RDM_SHIFT 24 964#define ID_ISAR5_CRC32_SHIFT 16 965#define ID_ISAR5_SHA2_SHIFT 12 966#define ID_ISAR5_SHA1_SHIFT 8 967#define ID_ISAR5_AES_SHIFT 4 968#define ID_ISAR5_SEVL_SHIFT 0 969 970#define ID_ISAR6_I8MM_SHIFT 24 971#define ID_ISAR6_BF16_SHIFT 20 972#define ID_ISAR6_SPECRES_SHIFT 16 973#define ID_ISAR6_SB_SHIFT 12 974#define ID_ISAR6_FHM_SHIFT 8 975#define ID_ISAR6_DP_SHIFT 4 976#define ID_ISAR6_JSCVT_SHIFT 0 977 978#define ID_MMFR0_INNERSHR_SHIFT 28 979#define ID_MMFR0_FCSE_SHIFT 24 980#define ID_MMFR0_AUXREG_SHIFT 20 981#define ID_MMFR0_TCM_SHIFT 16 982#define ID_MMFR0_SHARELVL_SHIFT 12 983#define ID_MMFR0_OUTERSHR_SHIFT 8 984#define ID_MMFR0_PMSA_SHIFT 4 985#define ID_MMFR0_VMSA_SHIFT 0 986 987#define ID_MMFR4_EVT_SHIFT 28 988#define ID_MMFR4_CCIDX_SHIFT 24 989#define ID_MMFR4_LSM_SHIFT 20 990#define ID_MMFR4_HPDS_SHIFT 16 991#define ID_MMFR4_CNP_SHIFT 12 992#define ID_MMFR4_XNX_SHIFT 8 993#define ID_MMFR4_AC2_SHIFT 4 994#define ID_MMFR4_SPECSEI_SHIFT 0 995 996#define ID_MMFR5_ETS_SHIFT 0 997 998#define ID_PFR0_DIT_SHIFT 24 999#define ID_PFR0_CSV2_SHIFT 16 1000#define ID_PFR0_STATE3_SHIFT 12 1001#define ID_PFR0_STATE2_SHIFT 8 1002#define ID_PFR0_STATE1_SHIFT 4 1003#define ID_PFR0_STATE0_SHIFT 0 1004 1005#define ID_DFR0_PERFMON_SHIFT 24 1006#define ID_DFR0_MPROFDBG_SHIFT 20 1007#define ID_DFR0_MMAPTRC_SHIFT 16 1008#define ID_DFR0_COPTRC_SHIFT 12 1009#define ID_DFR0_MMAPDBG_SHIFT 8 1010#define ID_DFR0_COPSDBG_SHIFT 4 1011#define ID_DFR0_COPDBG_SHIFT 0 1012 1013#define ID_PFR2_SSBS_SHIFT 4 1014#define ID_PFR2_CSV3_SHIFT 0 1015 1016#define MVFR0_FPROUND_SHIFT 28 1017#define MVFR0_FPSHVEC_SHIFT 24 1018#define MVFR0_FPSQRT_SHIFT 20 1019#define MVFR0_FPDIVIDE_SHIFT 16 1020#define MVFR0_FPTRAP_SHIFT 12 1021#define MVFR0_FPDP_SHIFT 8 1022#define MVFR0_FPSP_SHIFT 4 1023#define MVFR0_SIMD_SHIFT 0 1024 1025#define MVFR1_SIMDFMAC_SHIFT 28 1026#define MVFR1_FPHP_SHIFT 24 1027#define MVFR1_SIMDHP_SHIFT 20 1028#define MVFR1_SIMDSP_SHIFT 16 1029#define MVFR1_SIMDINT_SHIFT 12 1030#define MVFR1_SIMDLS_SHIFT 8 1031#define MVFR1_FPDNAN_SHIFT 4 1032#define MVFR1_FPFTZ_SHIFT 0 1033 1034#define ID_PFR1_GIC_SHIFT 28 1035#define ID_PFR1_VIRT_FRAC_SHIFT 24 1036#define ID_PFR1_SEC_FRAC_SHIFT 20 1037#define ID_PFR1_GENTIMER_SHIFT 16 1038#define ID_PFR1_VIRTUALIZATION_SHIFT 12 1039#define ID_PFR1_MPROGMOD_SHIFT 8 1040#define ID_PFR1_SECURITY_SHIFT 4 1041#define ID_PFR1_PROGMOD_SHIFT 0 1042 1043#if defined(CONFIG_ARM64_4K_PAGES) 1044#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 1045#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 1046#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 1047#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN4_2_SHIFT 1048#elif defined(CONFIG_ARM64_16K_PAGES) 1049#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 1050#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 1051#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 1052#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN16_2_SHIFT 1053#elif defined(CONFIG_ARM64_64K_PAGES) 1054#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 1055#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 1056#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 1057#define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN64_2_SHIFT 1058#endif 1059 1060#define MVFR2_FPMISC_SHIFT 4 1061#define MVFR2_SIMDMISC_SHIFT 0 1062 1063#define DCZID_DZP_SHIFT 4 1064#define DCZID_BS_SHIFT 0 1065 1066/* 1067 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 1068 * are reserved by the SVE architecture for future expansion of the LEN 1069 * field, with compatible semantics. 1070 */ 1071#define ZCR_ELx_LEN_SHIFT 0 1072#define ZCR_ELx_LEN_SIZE 9 1073#define ZCR_ELx_LEN_MASK 0x1ff 1074 1075#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 1076#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 1077#define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 1078 1079/* TCR EL1 Bit Definitions */ 1080#define SYS_TCR_EL1_TCMA1 (BIT(58)) 1081#define SYS_TCR_EL1_TCMA0 (BIT(57)) 1082 1083/* GCR_EL1 Definitions */ 1084#define SYS_GCR_EL1_RRND (BIT(16)) 1085#define SYS_GCR_EL1_EXCL_MASK 0xffffUL 1086 1087/* RGSR_EL1 Definitions */ 1088#define SYS_RGSR_EL1_TAG_MASK 0xfUL 1089#define SYS_RGSR_EL1_SEED_SHIFT 8 1090#define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1091 1092/* GMID_EL1 field definitions */ 1093#define SYS_GMID_EL1_BS_SHIFT 0 1094#define SYS_GMID_EL1_BS_SIZE 4 1095 1096/* TFSR{,E0}_EL1 bit definitions */ 1097#define SYS_TFSR_EL1_TF0_SHIFT 0 1098#define SYS_TFSR_EL1_TF1_SHIFT 1 1099#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1100#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1101 1102/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1103#define SYS_MPIDR_SAFE_VAL (BIT(31)) 1104 1105#define TRFCR_ELx_TS_SHIFT 5 1106#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 1107#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 1108#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 1109#define TRFCR_EL2_CX BIT(3) 1110#define TRFCR_ELx_ExTRE BIT(1) 1111#define TRFCR_ELx_E0TRE BIT(0) 1112 1113 1114/* GIC Hypervisor interface registers */ 1115/* ICH_MISR_EL2 bit definitions */ 1116#define ICH_MISR_EOI (1 << 0) 1117#define ICH_MISR_U (1 << 1) 1118 1119/* ICH_LR*_EL2 bit definitions */ 1120#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 1121 1122#define ICH_LR_EOI (1ULL << 41) 1123#define ICH_LR_GROUP (1ULL << 60) 1124#define ICH_LR_HW (1ULL << 61) 1125#define ICH_LR_STATE (3ULL << 62) 1126#define ICH_LR_PENDING_BIT (1ULL << 62) 1127#define ICH_LR_ACTIVE_BIT (1ULL << 63) 1128#define ICH_LR_PHYS_ID_SHIFT 32 1129#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 1130#define ICH_LR_PRIORITY_SHIFT 48 1131#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 1132 1133/* ICH_HCR_EL2 bit definitions */ 1134#define ICH_HCR_EN (1 << 0) 1135#define ICH_HCR_UIE (1 << 1) 1136#define ICH_HCR_NPIE (1 << 3) 1137#define ICH_HCR_TC (1 << 10) 1138#define ICH_HCR_TALL0 (1 << 11) 1139#define ICH_HCR_TALL1 (1 << 12) 1140#define ICH_HCR_EOIcount_SHIFT 27 1141#define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 1142 1143/* ICH_VMCR_EL2 bit definitions */ 1144#define ICH_VMCR_ACK_CTL_SHIFT 2 1145#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 1146#define ICH_VMCR_FIQ_EN_SHIFT 3 1147#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 1148#define ICH_VMCR_CBPR_SHIFT 4 1149#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 1150#define ICH_VMCR_EOIM_SHIFT 9 1151#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 1152#define ICH_VMCR_BPR1_SHIFT 18 1153#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 1154#define ICH_VMCR_BPR0_SHIFT 21 1155#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 1156#define ICH_VMCR_PMR_SHIFT 24 1157#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 1158#define ICH_VMCR_ENG0_SHIFT 0 1159#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 1160#define ICH_VMCR_ENG1_SHIFT 1 1161#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 1162 1163/* ICH_VTR_EL2 bit definitions */ 1164#define ICH_VTR_PRI_BITS_SHIFT 29 1165#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 1166#define ICH_VTR_ID_BITS_SHIFT 23 1167#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 1168#define ICH_VTR_SEIS_SHIFT 22 1169#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 1170#define ICH_VTR_A3V_SHIFT 21 1171#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 1172 1173#define ARM64_FEATURE_FIELD_BITS 4 1174 1175/* Create a mask for the feature bits of the specified feature. */ 1176#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) 1177 1178#ifdef __ASSEMBLY__ 1179 1180 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 1181 .equ .L__reg_num_x\num, \num 1182 .endr 1183 .equ .L__reg_num_xzr, 31 1184 1185 .macro mrs_s, rt, sreg 1186 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 1187 .endm 1188 1189 .macro msr_s, sreg, rt 1190 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 1191 .endm 1192 1193#else 1194 1195#include <linux/build_bug.h> 1196#include <linux/types.h> 1197#include <asm/alternative.h> 1198 1199#define __DEFINE_MRS_MSR_S_REGNUM \ 1200" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 1201" .equ .L__reg_num_x\\num, \\num\n" \ 1202" .endr\n" \ 1203" .equ .L__reg_num_xzr, 31\n" 1204 1205#define DEFINE_MRS_S \ 1206 __DEFINE_MRS_MSR_S_REGNUM \ 1207" .macro mrs_s, rt, sreg\n" \ 1208 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 1209" .endm\n" 1210 1211#define DEFINE_MSR_S \ 1212 __DEFINE_MRS_MSR_S_REGNUM \ 1213" .macro msr_s, sreg, rt\n" \ 1214 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 1215" .endm\n" 1216 1217#define UNDEFINE_MRS_S \ 1218" .purgem mrs_s\n" 1219 1220#define UNDEFINE_MSR_S \ 1221" .purgem msr_s\n" 1222 1223#define __mrs_s(v, r) \ 1224 DEFINE_MRS_S \ 1225" mrs_s " v ", " __stringify(r) "\n" \ 1226 UNDEFINE_MRS_S 1227 1228#define __msr_s(r, v) \ 1229 DEFINE_MSR_S \ 1230" msr_s " __stringify(r) ", " v "\n" \ 1231 UNDEFINE_MSR_S 1232 1233/* 1234 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1235 * optimized away or replaced with synthetic values. 1236 */ 1237#define read_sysreg(r) ({ \ 1238 u64 __val; \ 1239 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1240 __val; \ 1241}) 1242 1243/* 1244 * The "Z" constraint normally means a zero immediate, but when combined with 1245 * the "%x0" template means XZR. 1246 */ 1247#define write_sysreg(v, r) do { \ 1248 u64 __val = (u64)(v); \ 1249 asm volatile("msr " __stringify(r) ", %x0" \ 1250 : : "rZ" (__val)); \ 1251} while (0) 1252 1253/* 1254 * For registers without architectural names, or simply unsupported by 1255 * GAS. 1256 */ 1257#define read_sysreg_s(r) ({ \ 1258 u64 __val; \ 1259 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1260 __val; \ 1261}) 1262 1263#define write_sysreg_s(v, r) do { \ 1264 u64 __val = (u64)(v); \ 1265 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1266} while (0) 1267 1268/* 1269 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1270 * set mask are set. Other bits are left as-is. 1271 */ 1272#define sysreg_clear_set(sysreg, clear, set) do { \ 1273 u64 __scs_val = read_sysreg(sysreg); \ 1274 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1275 if (__scs_new != __scs_val) \ 1276 write_sysreg(__scs_new, sysreg); \ 1277} while (0) 1278 1279#define sysreg_clear_set_s(sysreg, clear, set) do { \ 1280 u64 __scs_val = read_sysreg_s(sysreg); \ 1281 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1282 if (__scs_new != __scs_val) \ 1283 write_sysreg_s(__scs_new, sysreg); \ 1284} while (0) 1285 1286#define read_sysreg_par() ({ \ 1287 u64 par; \ 1288 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1289 par = read_sysreg(par_el1); \ 1290 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1291 par; \ 1292}) 1293 1294#endif 1295 1296#endif /* __ASM_SYSREG_H */ 1297