1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * intel_hdmi_audio.c - Intel HDMI audio driver 4 * 5 * Copyright (C) 2016 Intel Corp 6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 7 * Ramesh Babu K V <ramesh.babu@intel.com> 8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 9 * Jerome Anand <jerome.anand@intel.com> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * ALSA driver for Intel HDMI audio 14 */ 15 16#include <linux/types.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/slab.h> 20#include <linux/module.h> 21#include <linux/interrupt.h> 22#include <linux/pm_runtime.h> 23#include <linux/dma-mapping.h> 24#include <linux/delay.h> 25#include <sound/core.h> 26#include <sound/asoundef.h> 27#include <sound/pcm.h> 28#include <sound/pcm_params.h> 29#include <sound/initval.h> 30#include <sound/control.h> 31#include <sound/jack.h> 32#include <drm/drm_edid.h> 33#include <drm/intel_lpe_audio.h> 34#include "intel_hdmi_audio.h" 35 36#define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000 37 38#define for_each_pipe(card_ctx, pipe) \ 39 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 40#define for_each_port(card_ctx, port) \ 41 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 42 43/*standard module options for ALSA. This module supports only one card*/ 44static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 45static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 46static bool single_port; 47 48module_param_named(index, hdmi_card_index, int, 0444); 49MODULE_PARM_DESC(index, 50 "Index value for INTEL Intel HDMI Audio controller."); 51module_param_named(id, hdmi_card_id, charp, 0444); 52MODULE_PARM_DESC(id, 53 "ID string for INTEL Intel HDMI Audio controller."); 54module_param(single_port, bool, 0444); 55MODULE_PARM_DESC(single_port, 56 "Single-port mode (for compatibility)"); 57 58/* 59 * ELD SA bits in the CEA Speaker Allocation data block 60 */ 61static const int eld_speaker_allocation_bits[] = { 62 [0] = FL | FR, 63 [1] = LFE, 64 [2] = FC, 65 [3] = RL | RR, 66 [4] = RC, 67 [5] = FLC | FRC, 68 [6] = RLC | RRC, 69 /* the following are not defined in ELD yet */ 70 [7] = 0, 71}; 72 73/* 74 * This is an ordered list! 75 * 76 * The preceding ones have better chances to be selected by 77 * hdmi_channel_allocation(). 78 */ 79static struct cea_channel_speaker_allocation channel_allocations[] = { 80/* channel: 7 6 5 4 3 2 1 0 */ 81{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 82 /* 2.1 */ 83{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 84 /* Dolby Surround */ 85{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 86 /* surround40 */ 87{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 88 /* surround41 */ 89{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 90 /* surround50 */ 91{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 92 /* surround51 */ 93{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 94 /* 6.1 */ 95{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 96 /* surround71 */ 97{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 98 99{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 100{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 101{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 102{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 103{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 104{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 105{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 106{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 107{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 108{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 109{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 110{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 111{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 112{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 113{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 114{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 115{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 116{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 117{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 118{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 119{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 120{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 121{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 122}; 123 124static const struct channel_map_table map_tables[] = { 125 { SNDRV_CHMAP_FL, 0x00, FL }, 126 { SNDRV_CHMAP_FR, 0x01, FR }, 127 { SNDRV_CHMAP_RL, 0x04, RL }, 128 { SNDRV_CHMAP_RR, 0x05, RR }, 129 { SNDRV_CHMAP_LFE, 0x02, LFE }, 130 { SNDRV_CHMAP_FC, 0x03, FC }, 131 { SNDRV_CHMAP_RLC, 0x06, RLC }, 132 { SNDRV_CHMAP_RRC, 0x07, RRC }, 133 {} /* terminator */ 134}; 135 136/* hardware capability structure */ 137static const struct snd_pcm_hardware had_pcm_hardware = { 138 .info = (SNDRV_PCM_INFO_INTERLEAVED | 139 SNDRV_PCM_INFO_MMAP | 140 SNDRV_PCM_INFO_MMAP_VALID | 141 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 142 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 143 SNDRV_PCM_FMTBIT_S24_LE | 144 SNDRV_PCM_FMTBIT_S32_LE), 145 .rates = SNDRV_PCM_RATE_32000 | 146 SNDRV_PCM_RATE_44100 | 147 SNDRV_PCM_RATE_48000 | 148 SNDRV_PCM_RATE_88200 | 149 SNDRV_PCM_RATE_96000 | 150 SNDRV_PCM_RATE_176400 | 151 SNDRV_PCM_RATE_192000, 152 .rate_min = HAD_MIN_RATE, 153 .rate_max = HAD_MAX_RATE, 154 .channels_min = HAD_MIN_CHANNEL, 155 .channels_max = HAD_MAX_CHANNEL, 156 .buffer_bytes_max = HAD_MAX_BUFFER, 157 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 158 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 159 .periods_min = HAD_MIN_PERIODS, 160 .periods_max = HAD_MAX_PERIODS, 161 .fifo_size = HAD_FIFO_SIZE, 162}; 163 164/* Get the active PCM substream; 165 * Call had_substream_put() for unreferecing. 166 * Don't call this inside had_spinlock, as it takes by itself 167 */ 168static struct snd_pcm_substream * 169had_substream_get(struct snd_intelhad *intelhaddata) 170{ 171 struct snd_pcm_substream *substream; 172 unsigned long flags; 173 174 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 175 substream = intelhaddata->stream_info.substream; 176 if (substream) 177 intelhaddata->stream_info.substream_refcount++; 178 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 179 return substream; 180} 181 182/* Unref the active PCM substream; 183 * Don't call this inside had_spinlock, as it takes by itself 184 */ 185static void had_substream_put(struct snd_intelhad *intelhaddata) 186{ 187 unsigned long flags; 188 189 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 190 intelhaddata->stream_info.substream_refcount--; 191 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 192} 193 194static u32 had_config_offset(int pipe) 195{ 196 switch (pipe) { 197 default: 198 case 0: 199 return AUDIO_HDMI_CONFIG_A; 200 case 1: 201 return AUDIO_HDMI_CONFIG_B; 202 case 2: 203 return AUDIO_HDMI_CONFIG_C; 204 } 205} 206 207/* Register access functions */ 208static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 209 int pipe, u32 reg) 210{ 211 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 212} 213 214static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 215 int pipe, u32 reg, u32 val) 216{ 217 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 218} 219 220static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 221{ 222 if (!ctx->connected) 223 *val = 0; 224 else 225 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 226} 227 228static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 229{ 230 if (ctx->connected) 231 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 232} 233 234/* 235 * enable / disable audio configuration 236 * 237 * The normal read/modify should not directly be used on VLV2 for 238 * updating AUD_CONFIG register. 239 * This is because: 240 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 241 * HDMI IP. As a result a read-modify of AUD_CONFIG register will always 242 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 243 * register. This field should be 1xy binary for configuration with 6 or 244 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 245 * causes the "channels" field to be updated as 0xy binary resulting in 246 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 247 * appropriate value when doing read-modify of AUD_CONFIG register. 248 */ 249static void had_enable_audio(struct snd_intelhad *intelhaddata, 250 bool enable) 251{ 252 /* update the cached value */ 253 intelhaddata->aud_config.regx.aud_en = enable; 254 had_write_register(intelhaddata, AUD_CONFIG, 255 intelhaddata->aud_config.regval); 256} 257 258/* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 259static void had_ack_irqs(struct snd_intelhad *ctx) 260{ 261 u32 status_reg; 262 263 if (!ctx->connected) 264 return; 265 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 266 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 267 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 268 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 269} 270 271/* Reset buffer pointers */ 272static void had_reset_audio(struct snd_intelhad *intelhaddata) 273{ 274 had_write_register(intelhaddata, AUD_HDMI_STATUS, 275 AUD_HDMI_STATUSG_MASK_FUNCRST); 276 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 277} 278 279/* 280 * initialize audio channel status registers 281 * This function is called in the prepare callback 282 */ 283static int had_prog_status_reg(struct snd_pcm_substream *substream, 284 struct snd_intelhad *intelhaddata) 285{ 286 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 287 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 288 289 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 290 IEC958_AES0_NONAUDIO) >> 1; 291 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 292 IEC958_AES3_CON_CLOCK) >> 4; 293 294 switch (substream->runtime->rate) { 295 case AUD_SAMPLE_RATE_32: 296 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 297 break; 298 299 case AUD_SAMPLE_RATE_44_1: 300 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 301 break; 302 case AUD_SAMPLE_RATE_48: 303 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 304 break; 305 case AUD_SAMPLE_RATE_88_2: 306 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 307 break; 308 case AUD_SAMPLE_RATE_96: 309 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 310 break; 311 case AUD_SAMPLE_RATE_176_4: 312 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 313 break; 314 case AUD_SAMPLE_RATE_192: 315 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 316 break; 317 318 default: 319 /* control should never come here */ 320 return -EINVAL; 321 } 322 323 had_write_register(intelhaddata, 324 AUD_CH_STATUS_0, ch_stat0.regval); 325 326 switch (substream->runtime->format) { 327 case SNDRV_PCM_FORMAT_S16_LE: 328 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 329 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 330 break; 331 case SNDRV_PCM_FORMAT_S24_LE: 332 case SNDRV_PCM_FORMAT_S32_LE: 333 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 334 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 335 break; 336 default: 337 return -EINVAL; 338 } 339 340 had_write_register(intelhaddata, 341 AUD_CH_STATUS_1, ch_stat1.regval); 342 return 0; 343} 344 345/* 346 * function to initialize audio 347 * registers and buffer configuration registers 348 * This function is called in the prepare callback 349 */ 350static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 351 struct snd_intelhad *intelhaddata) 352{ 353 union aud_cfg cfg_val = {.regval = 0}; 354 union aud_buf_config buf_cfg = {.regval = 0}; 355 u8 channels; 356 357 had_prog_status_reg(substream, intelhaddata); 358 359 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 360 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 361 buf_cfg.regx.aud_delay = 0; 362 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 363 364 channels = substream->runtime->channels; 365 cfg_val.regx.num_ch = channels - 2; 366 if (channels <= 2) 367 cfg_val.regx.layout = LAYOUT0; 368 else 369 cfg_val.regx.layout = LAYOUT1; 370 371 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 372 cfg_val.regx.packet_mode = 1; 373 374 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 375 cfg_val.regx.left_align = 1; 376 377 cfg_val.regx.val_bit = 1; 378 379 /* fix up the DP bits */ 380 if (intelhaddata->dp_output) { 381 cfg_val.regx.dp_modei = 1; 382 cfg_val.regx.set = 1; 383 } 384 385 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 386 intelhaddata->aud_config = cfg_val; 387 return 0; 388} 389 390/* 391 * Compute derived values in channel_allocations[]. 392 */ 393static void init_channel_allocations(void) 394{ 395 int i, j; 396 struct cea_channel_speaker_allocation *p; 397 398 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 399 p = channel_allocations + i; 400 p->channels = 0; 401 p->spk_mask = 0; 402 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 403 if (p->speakers[j]) { 404 p->channels++; 405 p->spk_mask |= p->speakers[j]; 406 } 407 } 408} 409 410/* 411 * The transformation takes two steps: 412 * 413 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 414 * spk_mask => (channel_allocations[]) => ai->CA 415 * 416 * TODO: it could select the wrong CA from multiple candidates. 417 */ 418static int had_channel_allocation(struct snd_intelhad *intelhaddata, 419 int channels) 420{ 421 int i; 422 int ca = 0; 423 int spk_mask = 0; 424 425 /* 426 * CA defaults to 0 for basic stereo audio 427 */ 428 if (channels <= 2) 429 return 0; 430 431 /* 432 * expand ELD's speaker allocation mask 433 * 434 * ELD tells the speaker mask in a compact(paired) form, 435 * expand ELD's notions to match the ones used by Audio InfoFrame. 436 */ 437 438 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 439 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 440 spk_mask |= eld_speaker_allocation_bits[i]; 441 } 442 443 /* search for the first working match in the CA table */ 444 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 445 if (channels == channel_allocations[i].channels && 446 (spk_mask & channel_allocations[i].spk_mask) == 447 channel_allocations[i].spk_mask) { 448 ca = channel_allocations[i].ca_index; 449 break; 450 } 451 } 452 453 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 454 455 return ca; 456} 457 458/* from speaker bit mask to ALSA API channel position */ 459static int spk_to_chmap(int spk) 460{ 461 const struct channel_map_table *t = map_tables; 462 463 for (; t->map; t++) { 464 if (t->spk_mask == spk) 465 return t->map; 466 } 467 return 0; 468} 469 470static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 471{ 472 int i, c; 473 int spk_mask = 0; 474 struct snd_pcm_chmap_elem *chmap; 475 u8 eld_high, eld_high_mask = 0xF0; 476 u8 high_msb; 477 478 kfree(intelhaddata->chmap->chmap); 479 intelhaddata->chmap->chmap = NULL; 480 481 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 482 if (!chmap) 483 return; 484 485 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 486 intelhaddata->eld[DRM_ELD_SPEAKER]); 487 488 /* WA: Fix the max channel supported to 8 */ 489 490 /* 491 * Sink may support more than 8 channels, if eld_high has more than 492 * one bit set. SOC supports max 8 channels. 493 * Refer eld_speaker_allocation_bits, for sink speaker allocation 494 */ 495 496 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 497 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 498 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 499 /* eld_high & (eld_high-1): if more than 1 bit set */ 500 /* 0x1F: 7 channels */ 501 for (i = 1; i < 4; i++) { 502 high_msb = eld_high & (0x80 >> i); 503 if (high_msb) { 504 intelhaddata->eld[DRM_ELD_SPEAKER] &= 505 high_msb | 0xF; 506 break; 507 } 508 } 509 } 510 511 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 512 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 513 spk_mask |= eld_speaker_allocation_bits[i]; 514 } 515 516 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 517 if (spk_mask == channel_allocations[i].spk_mask) { 518 for (c = 0; c < channel_allocations[i].channels; c++) { 519 chmap->map[c] = spk_to_chmap( 520 channel_allocations[i].speakers[ 521 (MAX_SPEAKERS - 1) - c]); 522 } 523 chmap->channels = channel_allocations[i].channels; 524 intelhaddata->chmap->chmap = chmap; 525 break; 526 } 527 } 528 if (i >= ARRAY_SIZE(channel_allocations)) 529 kfree(chmap); 530} 531 532/* 533 * ALSA API channel-map control callbacks 534 */ 535static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 536 struct snd_ctl_elem_info *uinfo) 537{ 538 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 539 uinfo->count = HAD_MAX_CHANNEL; 540 uinfo->value.integer.min = 0; 541 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 542 return 0; 543} 544 545static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 546 struct snd_ctl_elem_value *ucontrol) 547{ 548 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 549 struct snd_intelhad *intelhaddata = info->private_data; 550 int i; 551 const struct snd_pcm_chmap_elem *chmap; 552 553 memset(ucontrol->value.integer.value, 0, 554 sizeof(long) * HAD_MAX_CHANNEL); 555 mutex_lock(&intelhaddata->mutex); 556 if (!intelhaddata->chmap->chmap) { 557 mutex_unlock(&intelhaddata->mutex); 558 return 0; 559 } 560 561 chmap = intelhaddata->chmap->chmap; 562 for (i = 0; i < chmap->channels; i++) 563 ucontrol->value.integer.value[i] = chmap->map[i]; 564 mutex_unlock(&intelhaddata->mutex); 565 566 return 0; 567} 568 569static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 570 struct snd_pcm *pcm) 571{ 572 int err; 573 574 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 575 NULL, 0, (unsigned long)intelhaddata, 576 &intelhaddata->chmap); 577 if (err < 0) 578 return err; 579 580 intelhaddata->chmap->private_data = intelhaddata; 581 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 582 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 583 intelhaddata->chmap->chmap = NULL; 584 return 0; 585} 586 587/* 588 * Initialize Data Island Packets registers 589 * This function is called in the prepare callback 590 */ 591static void had_prog_dip(struct snd_pcm_substream *substream, 592 struct snd_intelhad *intelhaddata) 593{ 594 int i; 595 union aud_ctrl_st ctrl_state = {.regval = 0}; 596 union aud_info_frame2 frame2 = {.regval = 0}; 597 union aud_info_frame3 frame3 = {.regval = 0}; 598 u8 checksum = 0; 599 u32 info_frame; 600 int channels; 601 int ca; 602 603 channels = substream->runtime->channels; 604 605 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 606 607 ca = had_channel_allocation(intelhaddata, channels); 608 if (intelhaddata->dp_output) { 609 info_frame = DP_INFO_FRAME_WORD1; 610 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 611 } else { 612 info_frame = HDMI_INFO_FRAME_WORD1; 613 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 614 frame3.regx.chnl_alloc = ca; 615 616 /* Calculte the byte wide checksum for all valid DIP words */ 617 for (i = 0; i < BYTES_PER_WORD; i++) 618 checksum += (info_frame >> (i * 8)) & 0xff; 619 for (i = 0; i < BYTES_PER_WORD; i++) 620 checksum += (frame2.regval >> (i * 8)) & 0xff; 621 for (i = 0; i < BYTES_PER_WORD; i++) 622 checksum += (frame3.regval >> (i * 8)) & 0xff; 623 624 frame2.regx.chksum = -(checksum); 625 } 626 627 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 628 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 629 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 630 631 /* program remaining DIP words with zero */ 632 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 633 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 634 635 ctrl_state.regx.dip_freq = 1; 636 ctrl_state.regx.dip_en_sta = 1; 637 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 638} 639 640static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 641{ 642 u32 maud_val; 643 644 /* Select maud according to DP 1.2 spec */ 645 if (link_rate == DP_2_7_GHZ) { 646 switch (aud_samp_freq) { 647 case AUD_SAMPLE_RATE_32: 648 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 649 break; 650 651 case AUD_SAMPLE_RATE_44_1: 652 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 653 break; 654 655 case AUD_SAMPLE_RATE_48: 656 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 657 break; 658 659 case AUD_SAMPLE_RATE_88_2: 660 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 661 break; 662 663 case AUD_SAMPLE_RATE_96: 664 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 665 break; 666 667 case AUD_SAMPLE_RATE_176_4: 668 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 669 break; 670 671 case HAD_MAX_RATE: 672 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 673 break; 674 675 default: 676 maud_val = -EINVAL; 677 break; 678 } 679 } else if (link_rate == DP_1_62_GHZ) { 680 switch (aud_samp_freq) { 681 case AUD_SAMPLE_RATE_32: 682 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 683 break; 684 685 case AUD_SAMPLE_RATE_44_1: 686 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 687 break; 688 689 case AUD_SAMPLE_RATE_48: 690 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 691 break; 692 693 case AUD_SAMPLE_RATE_88_2: 694 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 695 break; 696 697 case AUD_SAMPLE_RATE_96: 698 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 699 break; 700 701 case AUD_SAMPLE_RATE_176_4: 702 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 703 break; 704 705 case HAD_MAX_RATE: 706 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 707 break; 708 709 default: 710 maud_val = -EINVAL; 711 break; 712 } 713 } else 714 maud_val = -EINVAL; 715 716 return maud_val; 717} 718 719/* 720 * Program HDMI audio CTS value 721 * 722 * @aud_samp_freq: sampling frequency of audio data 723 * @tmds: sampling frequency of the display data 724 * @link_rate: DP link rate 725 * @n_param: N value, depends on aud_samp_freq 726 * @intelhaddata: substream private data 727 * 728 * Program CTS register based on the audio and display sampling frequency 729 */ 730static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 731 u32 n_param, struct snd_intelhad *intelhaddata) 732{ 733 u32 cts_val; 734 u64 dividend, divisor; 735 736 if (intelhaddata->dp_output) { 737 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 738 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 739 } else { 740 /* Calculate CTS according to HDMI 1.3a spec*/ 741 dividend = (u64)tmds * n_param*1000; 742 divisor = 128 * aud_samp_freq; 743 cts_val = div64_u64(dividend, divisor); 744 } 745 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 746 tmds, n_param, cts_val); 747 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 748} 749 750static int had_calculate_n_value(u32 aud_samp_freq) 751{ 752 int n_val; 753 754 /* Select N according to HDMI 1.3a spec*/ 755 switch (aud_samp_freq) { 756 case AUD_SAMPLE_RATE_32: 757 n_val = 4096; 758 break; 759 760 case AUD_SAMPLE_RATE_44_1: 761 n_val = 6272; 762 break; 763 764 case AUD_SAMPLE_RATE_48: 765 n_val = 6144; 766 break; 767 768 case AUD_SAMPLE_RATE_88_2: 769 n_val = 12544; 770 break; 771 772 case AUD_SAMPLE_RATE_96: 773 n_val = 12288; 774 break; 775 776 case AUD_SAMPLE_RATE_176_4: 777 n_val = 25088; 778 break; 779 780 case HAD_MAX_RATE: 781 n_val = 24576; 782 break; 783 784 default: 785 n_val = -EINVAL; 786 break; 787 } 788 return n_val; 789} 790 791/* 792 * Program HDMI audio N value 793 * 794 * @aud_samp_freq: sampling frequency of audio data 795 * @n_param: N value, depends on aud_samp_freq 796 * @intelhaddata: substream private data 797 * 798 * This function is called in the prepare callback. 799 * It programs based on the audio and display sampling frequency 800 */ 801static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 802 struct snd_intelhad *intelhaddata) 803{ 804 int n_val; 805 806 if (intelhaddata->dp_output) { 807 /* 808 * According to DP specs, Maud and Naud values hold 809 * a relationship, which is stated as: 810 * Maud/Naud = 512 * fs / f_LS_Clk 811 * where, fs is the sampling frequency of the audio stream 812 * and Naud is 32768 for Async clock. 813 */ 814 815 n_val = DP_NAUD_VAL; 816 } else 817 n_val = had_calculate_n_value(aud_samp_freq); 818 819 if (n_val < 0) 820 return n_val; 821 822 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 823 *n_param = n_val; 824 return 0; 825} 826 827/* 828 * PCM ring buffer handling 829 * 830 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 831 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 832 * moves at each period elapsed. The below illustrates how it works: 833 * 834 * At time=0 835 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 836 * BD | 0 | 1 | 2 | 3 | 837 * 838 * At time=1 (period elapsed) 839 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 840 * BD | 1 | 2 | 3 | 0 | 841 * 842 * At time=2 (second period elapsed) 843 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 844 * BD | 2 | 3 | 0 | 1 | 845 * 846 * The bd_head field points to the index of the BD to be read. It's also the 847 * position to be filled at next. The pcm_head and the pcm_filled fields 848 * point to the indices of the current position and of the next position to 849 * be filled, respectively. For PCM buffer there are both _head and _filled 850 * because they may be difference when nperiods > 4. For example, in the 851 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 852 * 853 * pcm_head (=1) --v v-- pcm_filled (=5) 854 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 855 * BD | 1 | 2 | 3 | 0 | 856 * bd_head (=1) --^ ^-- next to fill (= bd_head) 857 * 858 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 859 * the hardware skips those BDs in the loop. 860 * 861 * An exceptional setup is the case with nperiods=1. Since we have to update 862 * BDs after finishing one BD processing, we'd need at least two BDs, where 863 * both BDs point to the same content, the same address, the same size of the 864 * whole PCM buffer. 865 */ 866 867#define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 868#define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 869 870/* Set up a buffer descriptor at the "filled" position */ 871static void had_prog_bd(struct snd_pcm_substream *substream, 872 struct snd_intelhad *intelhaddata) 873{ 874 int idx = intelhaddata->bd_head; 875 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 876 u32 addr = substream->runtime->dma_addr + ofs; 877 878 addr |= AUD_BUF_VALID; 879 if (!substream->runtime->no_period_wakeup) 880 addr |= AUD_BUF_INTR_EN; 881 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 882 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 883 intelhaddata->period_bytes); 884 885 /* advance the indices to the next */ 886 intelhaddata->bd_head++; 887 intelhaddata->bd_head %= intelhaddata->num_bds; 888 intelhaddata->pcmbuf_filled++; 889 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 890} 891 892/* invalidate a buffer descriptor with the given index */ 893static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 894 int idx) 895{ 896 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 897 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 898} 899 900/* Initial programming of ring buffer */ 901static void had_init_ringbuf(struct snd_pcm_substream *substream, 902 struct snd_intelhad *intelhaddata) 903{ 904 struct snd_pcm_runtime *runtime = substream->runtime; 905 int i, num_periods; 906 907 num_periods = runtime->periods; 908 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 909 /* set the minimum 2 BDs for num_periods=1 */ 910 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 911 intelhaddata->period_bytes = 912 frames_to_bytes(runtime, runtime->period_size); 913 WARN_ON(intelhaddata->period_bytes & 0x3f); 914 915 intelhaddata->bd_head = 0; 916 intelhaddata->pcmbuf_head = 0; 917 intelhaddata->pcmbuf_filled = 0; 918 919 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 920 if (i < intelhaddata->num_bds) 921 had_prog_bd(substream, intelhaddata); 922 else /* invalidate the rest */ 923 had_invalidate_bd(intelhaddata, i); 924 } 925 926 intelhaddata->bd_head = 0; /* reset at head again before starting */ 927} 928 929/* process a bd, advance to the next */ 930static void had_advance_ringbuf(struct snd_pcm_substream *substream, 931 struct snd_intelhad *intelhaddata) 932{ 933 int num_periods = substream->runtime->periods; 934 935 /* reprogram the next buffer */ 936 had_prog_bd(substream, intelhaddata); 937 938 /* proceed to next */ 939 intelhaddata->pcmbuf_head++; 940 intelhaddata->pcmbuf_head %= num_periods; 941} 942 943/* process the current BD(s); 944 * returns the current PCM buffer byte position, or -EPIPE for underrun. 945 */ 946static int had_process_ringbuf(struct snd_pcm_substream *substream, 947 struct snd_intelhad *intelhaddata) 948{ 949 int len, processed; 950 unsigned long flags; 951 952 processed = 0; 953 spin_lock_irqsave(&intelhaddata->had_spinlock, flags); 954 for (;;) { 955 /* get the remaining bytes on the buffer */ 956 had_read_register(intelhaddata, 957 AUD_BUF_LEN(intelhaddata->bd_head), 958 &len); 959 if (len < 0 || len > intelhaddata->period_bytes) { 960 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 961 len); 962 len = -EPIPE; 963 goto out; 964 } 965 966 if (len > 0) /* OK, this is the current buffer */ 967 break; 968 969 /* len=0 => already empty, check the next buffer */ 970 if (++processed >= intelhaddata->num_bds) { 971 len = -EPIPE; /* all empty? - report underrun */ 972 goto out; 973 } 974 had_advance_ringbuf(substream, intelhaddata); 975 } 976 977 len = intelhaddata->period_bytes - len; 978 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 979 out: 980 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); 981 return len; 982} 983 984/* called from irq handler */ 985static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 986{ 987 struct snd_pcm_substream *substream; 988 989 substream = had_substream_get(intelhaddata); 990 if (!substream) 991 return; /* no stream? - bail out */ 992 993 if (!intelhaddata->connected) { 994 snd_pcm_stop_xrun(substream); 995 goto out; /* disconnected? - bail out */ 996 } 997 998 /* process or stop the stream */ 999 if (had_process_ringbuf(substream, intelhaddata) < 0) 1000 snd_pcm_stop_xrun(substream); 1001 else 1002 snd_pcm_period_elapsed(substream); 1003 1004 out: 1005 had_substream_put(intelhaddata); 1006} 1007 1008/* 1009 * The interrupt status 'sticky' bits might not be cleared by 1010 * setting '1' to that bit once... 1011 */ 1012static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1013{ 1014 int i; 1015 u32 val; 1016 1017 for (i = 0; i < 100; i++) { 1018 /* clear bit30, 31 AUD_HDMI_STATUS */ 1019 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1020 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1021 return; 1022 udelay(100); 1023 cond_resched(); 1024 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1025 } 1026 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1027} 1028 1029/* Perform some reset procedure after stopping the stream; 1030 * this is called from prepare or hw_free callbacks once after trigger STOP 1031 * or underrun has been processed in order to settle down the h/w state. 1032 */ 1033static int had_pcm_sync_stop(struct snd_pcm_substream *substream) 1034{ 1035 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream); 1036 1037 if (!intelhaddata->connected) 1038 return 0; 1039 1040 /* Reset buffer pointers */ 1041 had_reset_audio(intelhaddata); 1042 wait_clear_underrun_bit(intelhaddata); 1043 return 0; 1044} 1045 1046/* called from irq handler */ 1047static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1048{ 1049 struct snd_pcm_substream *substream; 1050 1051 /* Report UNDERRUN error to above layers */ 1052 substream = had_substream_get(intelhaddata); 1053 if (substream) { 1054 snd_pcm_stop_xrun(substream); 1055 had_substream_put(intelhaddata); 1056 } 1057} 1058 1059/* 1060 * ALSA PCM open callback 1061 */ 1062static int had_pcm_open(struct snd_pcm_substream *substream) 1063{ 1064 struct snd_intelhad *intelhaddata; 1065 struct snd_pcm_runtime *runtime; 1066 int retval; 1067 1068 intelhaddata = snd_pcm_substream_chip(substream); 1069 runtime = substream->runtime; 1070 1071 retval = pm_runtime_resume_and_get(intelhaddata->dev); 1072 if (retval < 0) 1073 return retval; 1074 1075 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1076 runtime->hw = had_pcm_hardware; 1077 1078 retval = snd_pcm_hw_constraint_integer(runtime, 1079 SNDRV_PCM_HW_PARAM_PERIODS); 1080 if (retval < 0) 1081 goto error; 1082 1083 /* Make sure, that the period size is always aligned 1084 * 64byte boundary 1085 */ 1086 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1087 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1088 if (retval < 0) 1089 goto error; 1090 1091 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1092 if (retval < 0) 1093 goto error; 1094 1095 /* expose PCM substream */ 1096 spin_lock_irq(&intelhaddata->had_spinlock); 1097 intelhaddata->stream_info.substream = substream; 1098 intelhaddata->stream_info.substream_refcount++; 1099 spin_unlock_irq(&intelhaddata->had_spinlock); 1100 1101 return retval; 1102 error: 1103 pm_runtime_mark_last_busy(intelhaddata->dev); 1104 pm_runtime_put_autosuspend(intelhaddata->dev); 1105 return retval; 1106} 1107 1108/* 1109 * ALSA PCM close callback 1110 */ 1111static int had_pcm_close(struct snd_pcm_substream *substream) 1112{ 1113 struct snd_intelhad *intelhaddata; 1114 1115 intelhaddata = snd_pcm_substream_chip(substream); 1116 1117 /* unreference and sync with the pending PCM accesses */ 1118 spin_lock_irq(&intelhaddata->had_spinlock); 1119 intelhaddata->stream_info.substream = NULL; 1120 intelhaddata->stream_info.substream_refcount--; 1121 while (intelhaddata->stream_info.substream_refcount > 0) { 1122 spin_unlock_irq(&intelhaddata->had_spinlock); 1123 cpu_relax(); 1124 spin_lock_irq(&intelhaddata->had_spinlock); 1125 } 1126 spin_unlock_irq(&intelhaddata->had_spinlock); 1127 1128 pm_runtime_mark_last_busy(intelhaddata->dev); 1129 pm_runtime_put_autosuspend(intelhaddata->dev); 1130 return 0; 1131} 1132 1133/* 1134 * ALSA PCM hw_params callback 1135 */ 1136static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1137 struct snd_pcm_hw_params *hw_params) 1138{ 1139 struct snd_intelhad *intelhaddata; 1140 int buf_size; 1141 1142 intelhaddata = snd_pcm_substream_chip(substream); 1143 buf_size = params_buffer_bytes(hw_params); 1144 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1145 __func__, buf_size); 1146 return 0; 1147} 1148 1149/* 1150 * ALSA PCM trigger callback 1151 */ 1152static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1153{ 1154 int retval = 0; 1155 struct snd_intelhad *intelhaddata; 1156 1157 intelhaddata = snd_pcm_substream_chip(substream); 1158 1159 spin_lock(&intelhaddata->had_spinlock); 1160 switch (cmd) { 1161 case SNDRV_PCM_TRIGGER_START: 1162 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1163 case SNDRV_PCM_TRIGGER_RESUME: 1164 /* Enable Audio */ 1165 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1166 had_enable_audio(intelhaddata, true); 1167 break; 1168 1169 case SNDRV_PCM_TRIGGER_STOP: 1170 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1171 /* Disable Audio */ 1172 had_enable_audio(intelhaddata, false); 1173 break; 1174 1175 default: 1176 retval = -EINVAL; 1177 } 1178 spin_unlock(&intelhaddata->had_spinlock); 1179 return retval; 1180} 1181 1182/* 1183 * ALSA PCM prepare callback 1184 */ 1185static int had_pcm_prepare(struct snd_pcm_substream *substream) 1186{ 1187 int retval; 1188 u32 disp_samp_freq, n_param; 1189 u32 link_rate = 0; 1190 struct snd_intelhad *intelhaddata; 1191 struct snd_pcm_runtime *runtime; 1192 1193 intelhaddata = snd_pcm_substream_chip(substream); 1194 runtime = substream->runtime; 1195 1196 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1197 (int)frames_to_bytes(runtime, runtime->period_size)); 1198 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1199 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1200 (int)snd_pcm_lib_buffer_bytes(substream)); 1201 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1202 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1203 1204 /* Get N value in KHz */ 1205 disp_samp_freq = intelhaddata->tmds_clock_speed; 1206 1207 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1208 if (retval) { 1209 dev_err(intelhaddata->dev, 1210 "programming N value failed %#x\n", retval); 1211 goto prep_end; 1212 } 1213 1214 if (intelhaddata->dp_output) 1215 link_rate = intelhaddata->link_rate; 1216 1217 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1218 n_param, intelhaddata); 1219 1220 had_prog_dip(substream, intelhaddata); 1221 1222 retval = had_init_audio_ctrl(substream, intelhaddata); 1223 1224 /* Prog buffer address */ 1225 had_init_ringbuf(substream, intelhaddata); 1226 1227 /* 1228 * Program channel mapping in following order: 1229 * FL, FR, C, LFE, RL, RR 1230 */ 1231 1232 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1233 1234prep_end: 1235 return retval; 1236} 1237 1238/* 1239 * ALSA PCM pointer callback 1240 */ 1241static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1242{ 1243 struct snd_intelhad *intelhaddata; 1244 int len; 1245 1246 intelhaddata = snd_pcm_substream_chip(substream); 1247 1248 if (!intelhaddata->connected) 1249 return SNDRV_PCM_POS_XRUN; 1250 1251 len = had_process_ringbuf(substream, intelhaddata); 1252 if (len < 0) 1253 return SNDRV_PCM_POS_XRUN; 1254 len = bytes_to_frames(substream->runtime, len); 1255 /* wrapping may happen when periods=1 */ 1256 len %= substream->runtime->buffer_size; 1257 return len; 1258} 1259 1260/* 1261 * ALSA PCM ops 1262 */ 1263static const struct snd_pcm_ops had_pcm_ops = { 1264 .open = had_pcm_open, 1265 .close = had_pcm_close, 1266 .hw_params = had_pcm_hw_params, 1267 .prepare = had_pcm_prepare, 1268 .trigger = had_pcm_trigger, 1269 .sync_stop = had_pcm_sync_stop, 1270 .pointer = had_pcm_pointer, 1271}; 1272 1273/* process mode change of the running stream; called in mutex */ 1274static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1275{ 1276 struct snd_pcm_substream *substream; 1277 int retval = 0; 1278 u32 disp_samp_freq, n_param; 1279 u32 link_rate = 0; 1280 1281 substream = had_substream_get(intelhaddata); 1282 if (!substream) 1283 return 0; 1284 1285 /* Disable Audio */ 1286 had_enable_audio(intelhaddata, false); 1287 1288 /* Update CTS value */ 1289 disp_samp_freq = intelhaddata->tmds_clock_speed; 1290 1291 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1292 if (retval) { 1293 dev_err(intelhaddata->dev, 1294 "programming N value failed %#x\n", retval); 1295 goto out; 1296 } 1297 1298 if (intelhaddata->dp_output) 1299 link_rate = intelhaddata->link_rate; 1300 1301 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1302 n_param, intelhaddata); 1303 1304 /* Enable Audio */ 1305 had_enable_audio(intelhaddata, true); 1306 1307out: 1308 had_substream_put(intelhaddata); 1309 return retval; 1310} 1311 1312/* process hot plug, called from wq with mutex locked */ 1313static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1314{ 1315 struct snd_pcm_substream *substream; 1316 1317 spin_lock_irq(&intelhaddata->had_spinlock); 1318 if (intelhaddata->connected) { 1319 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1320 spin_unlock_irq(&intelhaddata->had_spinlock); 1321 return; 1322 } 1323 1324 /* Disable Audio */ 1325 had_enable_audio(intelhaddata, false); 1326 1327 intelhaddata->connected = true; 1328 dev_dbg(intelhaddata->dev, 1329 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1330 __func__, __LINE__); 1331 spin_unlock_irq(&intelhaddata->had_spinlock); 1332 1333 had_build_channel_allocation_map(intelhaddata); 1334 1335 /* Report to above ALSA layer */ 1336 substream = had_substream_get(intelhaddata); 1337 if (substream) { 1338 snd_pcm_stop_xrun(substream); 1339 had_substream_put(intelhaddata); 1340 } 1341 1342 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1343} 1344 1345/* process hot unplug, called from wq with mutex locked */ 1346static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1347{ 1348 struct snd_pcm_substream *substream; 1349 1350 spin_lock_irq(&intelhaddata->had_spinlock); 1351 if (!intelhaddata->connected) { 1352 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1353 spin_unlock_irq(&intelhaddata->had_spinlock); 1354 return; 1355 1356 } 1357 1358 /* Disable Audio */ 1359 had_enable_audio(intelhaddata, false); 1360 1361 intelhaddata->connected = false; 1362 dev_dbg(intelhaddata->dev, 1363 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1364 __func__, __LINE__); 1365 spin_unlock_irq(&intelhaddata->had_spinlock); 1366 1367 kfree(intelhaddata->chmap->chmap); 1368 intelhaddata->chmap->chmap = NULL; 1369 1370 /* Report to above ALSA layer */ 1371 substream = had_substream_get(intelhaddata); 1372 if (substream) { 1373 snd_pcm_stop_xrun(substream); 1374 had_substream_put(intelhaddata); 1375 } 1376 1377 snd_jack_report(intelhaddata->jack, 0); 1378} 1379 1380/* 1381 * ALSA iec958 and ELD controls 1382 */ 1383 1384static int had_iec958_info(struct snd_kcontrol *kcontrol, 1385 struct snd_ctl_elem_info *uinfo) 1386{ 1387 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1388 uinfo->count = 1; 1389 return 0; 1390} 1391 1392static int had_iec958_get(struct snd_kcontrol *kcontrol, 1393 struct snd_ctl_elem_value *ucontrol) 1394{ 1395 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1396 1397 mutex_lock(&intelhaddata->mutex); 1398 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1399 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1400 ucontrol->value.iec958.status[2] = 1401 (intelhaddata->aes_bits >> 16) & 0xff; 1402 ucontrol->value.iec958.status[3] = 1403 (intelhaddata->aes_bits >> 24) & 0xff; 1404 mutex_unlock(&intelhaddata->mutex); 1405 return 0; 1406} 1407 1408static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1409 struct snd_ctl_elem_value *ucontrol) 1410{ 1411 ucontrol->value.iec958.status[0] = 0xff; 1412 ucontrol->value.iec958.status[1] = 0xff; 1413 ucontrol->value.iec958.status[2] = 0xff; 1414 ucontrol->value.iec958.status[3] = 0xff; 1415 return 0; 1416} 1417 1418static int had_iec958_put(struct snd_kcontrol *kcontrol, 1419 struct snd_ctl_elem_value *ucontrol) 1420{ 1421 unsigned int val; 1422 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1423 int changed = 0; 1424 1425 val = (ucontrol->value.iec958.status[0] << 0) | 1426 (ucontrol->value.iec958.status[1] << 8) | 1427 (ucontrol->value.iec958.status[2] << 16) | 1428 (ucontrol->value.iec958.status[3] << 24); 1429 mutex_lock(&intelhaddata->mutex); 1430 if (intelhaddata->aes_bits != val) { 1431 intelhaddata->aes_bits = val; 1432 changed = 1; 1433 } 1434 mutex_unlock(&intelhaddata->mutex); 1435 return changed; 1436} 1437 1438static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1439 struct snd_ctl_elem_info *uinfo) 1440{ 1441 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1442 uinfo->count = HDMI_MAX_ELD_BYTES; 1443 return 0; 1444} 1445 1446static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1447 struct snd_ctl_elem_value *ucontrol) 1448{ 1449 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1450 1451 mutex_lock(&intelhaddata->mutex); 1452 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1453 HDMI_MAX_ELD_BYTES); 1454 mutex_unlock(&intelhaddata->mutex); 1455 return 0; 1456} 1457 1458static const struct snd_kcontrol_new had_controls[] = { 1459 { 1460 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1461 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1462 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1463 .info = had_iec958_info, /* shared */ 1464 .get = had_iec958_mask_get, 1465 }, 1466 { 1467 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1468 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1469 .info = had_iec958_info, 1470 .get = had_iec958_get, 1471 .put = had_iec958_put, 1472 }, 1473 { 1474 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1475 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1476 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1477 .name = "ELD", 1478 .info = had_ctl_eld_info, 1479 .get = had_ctl_eld_get, 1480 }, 1481}; 1482 1483/* 1484 * audio interrupt handler 1485 */ 1486static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1487{ 1488 struct snd_intelhad_card *card_ctx = dev_id; 1489 u32 audio_stat[3] = {}; 1490 int pipe, port; 1491 1492 for_each_pipe(card_ctx, pipe) { 1493 /* use raw register access to ack IRQs even while disconnected */ 1494 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1495 AUD_HDMI_STATUS) & 1496 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1497 1498 if (audio_stat[pipe]) 1499 had_write_register_raw(card_ctx, pipe, 1500 AUD_HDMI_STATUS, audio_stat[pipe]); 1501 } 1502 1503 for_each_port(card_ctx, port) { 1504 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1505 int pipe = ctx->pipe; 1506 1507 if (pipe < 0) 1508 continue; 1509 1510 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1511 had_process_buffer_done(ctx); 1512 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1513 had_process_buffer_underrun(ctx); 1514 } 1515 1516 return IRQ_HANDLED; 1517} 1518 1519/* 1520 * monitor plug/unplug notification from i915; just kick off the work 1521 */ 1522static void notify_audio_lpe(struct platform_device *pdev, int port) 1523{ 1524 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1525 struct snd_intelhad *ctx; 1526 1527 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; 1528 if (single_port) 1529 ctx->port = port; 1530 1531 schedule_work(&ctx->hdmi_audio_wq); 1532} 1533 1534/* the work to handle monitor hot plug/unplug */ 1535static void had_audio_wq(struct work_struct *work) 1536{ 1537 struct snd_intelhad *ctx = 1538 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1539 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1540 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1541 int ret; 1542 1543 ret = pm_runtime_resume_and_get(ctx->dev); 1544 if (ret < 0) 1545 return; 1546 1547 mutex_lock(&ctx->mutex); 1548 if (ppdata->pipe < 0) { 1549 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1550 __func__, ctx->port); 1551 1552 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1553 1554 ctx->dp_output = false; 1555 ctx->tmds_clock_speed = 0; 1556 ctx->link_rate = 0; 1557 1558 /* Shut down the stream */ 1559 had_process_hot_unplug(ctx); 1560 1561 ctx->pipe = -1; 1562 } else { 1563 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1564 __func__, ctx->port, ppdata->ls_clock); 1565 1566 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1567 1568 ctx->dp_output = ppdata->dp_output; 1569 if (ctx->dp_output) { 1570 ctx->tmds_clock_speed = 0; 1571 ctx->link_rate = ppdata->ls_clock; 1572 } else { 1573 ctx->tmds_clock_speed = ppdata->ls_clock; 1574 ctx->link_rate = 0; 1575 } 1576 1577 /* 1578 * Shut down the stream before we change 1579 * the pipe assignment for this pcm device 1580 */ 1581 had_process_hot_plug(ctx); 1582 1583 ctx->pipe = ppdata->pipe; 1584 1585 /* Restart the stream if necessary */ 1586 had_process_mode_change(ctx); 1587 } 1588 1589 mutex_unlock(&ctx->mutex); 1590 pm_runtime_mark_last_busy(ctx->dev); 1591 pm_runtime_put_autosuspend(ctx->dev); 1592} 1593 1594/* 1595 * Jack interface 1596 */ 1597static int had_create_jack(struct snd_intelhad *ctx, 1598 struct snd_pcm *pcm) 1599{ 1600 char hdmi_str[32]; 1601 int err; 1602 1603 snprintf(hdmi_str, sizeof(hdmi_str), 1604 "HDMI/DP,pcm=%d", pcm->device); 1605 1606 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1607 SND_JACK_AVOUT, &ctx->jack, 1608 true, false); 1609 if (err < 0) 1610 return err; 1611 ctx->jack->private_data = ctx; 1612 return 0; 1613} 1614 1615/* 1616 * PM callbacks 1617 */ 1618 1619static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) 1620{ 1621 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1622 1623 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1624 1625 return 0; 1626} 1627 1628static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) 1629{ 1630 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1631 1632 pm_runtime_mark_last_busy(dev); 1633 1634 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1635 1636 return 0; 1637} 1638 1639/* release resources */ 1640static void hdmi_lpe_audio_free(struct snd_card *card) 1641{ 1642 struct snd_intelhad_card *card_ctx = card->private_data; 1643 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1644 int port; 1645 1646 spin_lock_irq(&pdata->lpe_audio_slock); 1647 pdata->notify_audio_lpe = NULL; 1648 spin_unlock_irq(&pdata->lpe_audio_slock); 1649 1650 for_each_port(card_ctx, port) { 1651 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1652 1653 cancel_work_sync(&ctx->hdmi_audio_wq); 1654 } 1655} 1656 1657/* 1658 * hdmi_lpe_audio_probe - start bridge with i915 1659 * 1660 * This function is called when the i915 driver creates the 1661 * hdmi-lpe-audio platform device. 1662 */ 1663static int __hdmi_lpe_audio_probe(struct platform_device *pdev) 1664{ 1665 struct snd_card *card; 1666 struct snd_intelhad_card *card_ctx; 1667 struct snd_intelhad *ctx; 1668 struct snd_pcm *pcm; 1669 struct intel_hdmi_lpe_audio_pdata *pdata; 1670 int irq; 1671 struct resource *res_mmio; 1672 int port, ret; 1673 1674 pdata = pdev->dev.platform_data; 1675 if (!pdata) { 1676 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1677 return -EINVAL; 1678 } 1679 1680 /* get resources */ 1681 irq = platform_get_irq(pdev, 0); 1682 if (irq < 0) 1683 return irq; 1684 1685 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1686 if (!res_mmio) { 1687 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1688 return -ENXIO; 1689 } 1690 1691 /* create a card instance with ALSA framework */ 1692 ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1693 THIS_MODULE, sizeof(*card_ctx), &card); 1694 if (ret) 1695 return ret; 1696 1697 card_ctx = card->private_data; 1698 card_ctx->dev = &pdev->dev; 1699 card_ctx->card = card; 1700 strcpy(card->driver, INTEL_HAD); 1701 strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1702 strcpy(card->longname, "Intel HDMI/DP LPE Audio"); 1703 1704 card_ctx->irq = -1; 1705 1706 card->private_free = hdmi_lpe_audio_free; 1707 1708 platform_set_drvdata(pdev, card_ctx); 1709 1710 card_ctx->num_pipes = pdata->num_pipes; 1711 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1712 1713 for_each_port(card_ctx, port) { 1714 ctx = &card_ctx->pcm_ctx[port]; 1715 ctx->card_ctx = card_ctx; 1716 ctx->dev = card_ctx->dev; 1717 ctx->port = single_port ? -1 : port; 1718 ctx->pipe = -1; 1719 1720 spin_lock_init(&ctx->had_spinlock); 1721 mutex_init(&ctx->mutex); 1722 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1723 } 1724 1725 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1726 __func__, (unsigned int)res_mmio->start, 1727 (unsigned int)res_mmio->end); 1728 1729 card_ctx->mmio_start = 1730 devm_ioremap(&pdev->dev, res_mmio->start, 1731 (size_t)(resource_size(res_mmio))); 1732 if (!card_ctx->mmio_start) { 1733 dev_err(&pdev->dev, "Could not get ioremap\n"); 1734 return -EACCES; 1735 } 1736 1737 /* setup interrupt handler */ 1738 ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler, 1739 0, pdev->name, card_ctx); 1740 if (ret < 0) { 1741 dev_err(&pdev->dev, "request_irq failed\n"); 1742 return ret; 1743 } 1744 1745 card_ctx->irq = irq; 1746 1747 /* only 32bit addressable */ 1748 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1749 if (ret) 1750 return ret; 1751 1752 init_channel_allocations(); 1753 1754 card_ctx->num_pipes = pdata->num_pipes; 1755 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1756 1757 for_each_port(card_ctx, port) { 1758 int i; 1759 1760 ctx = &card_ctx->pcm_ctx[port]; 1761 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1762 MAX_CAP_STREAMS, &pcm); 1763 if (ret) 1764 return ret; 1765 1766 /* setup private data which can be retrieved when required */ 1767 pcm->private_data = ctx; 1768 pcm->info_flags = 0; 1769 strscpy(pcm->name, card->shortname, strlen(card->shortname)); 1770 /* setup the ops for playback */ 1771 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1772 1773 /* allocate dma pages; 1774 * try to allocate 600k buffer as default which is large enough 1775 */ 1776 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC, 1777 card->dev, HAD_DEFAULT_BUFFER, 1778 HAD_MAX_BUFFER); 1779 1780 /* create controls */ 1781 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1782 struct snd_kcontrol *kctl; 1783 1784 kctl = snd_ctl_new1(&had_controls[i], ctx); 1785 if (!kctl) 1786 return -ENOMEM; 1787 1788 kctl->id.device = pcm->device; 1789 1790 ret = snd_ctl_add(card, kctl); 1791 if (ret < 0) 1792 return ret; 1793 } 1794 1795 /* Register channel map controls */ 1796 ret = had_register_chmap_ctls(ctx, pcm); 1797 if (ret < 0) 1798 return ret; 1799 1800 ret = had_create_jack(ctx, pcm); 1801 if (ret < 0) 1802 return ret; 1803 } 1804 1805 ret = snd_card_register(card); 1806 if (ret) 1807 return ret; 1808 1809 spin_lock_irq(&pdata->lpe_audio_slock); 1810 pdata->notify_audio_lpe = notify_audio_lpe; 1811 spin_unlock_irq(&pdata->lpe_audio_slock); 1812 1813 pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS); 1814 pm_runtime_use_autosuspend(&pdev->dev); 1815 pm_runtime_enable(&pdev->dev); 1816 pm_runtime_mark_last_busy(&pdev->dev); 1817 pm_runtime_idle(&pdev->dev); 1818 1819 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1820 for_each_port(card_ctx, port) { 1821 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1822 1823 schedule_work(&ctx->hdmi_audio_wq); 1824 } 1825 1826 return 0; 1827} 1828 1829static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1830{ 1831 return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev)); 1832} 1833 1834static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1835 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1836}; 1837 1838static struct platform_driver hdmi_lpe_audio_driver = { 1839 .driver = { 1840 .name = "hdmi-lpe-audio", 1841 .pm = &hdmi_lpe_audio_pm, 1842 }, 1843 .probe = hdmi_lpe_audio_probe, 1844}; 1845 1846module_platform_driver(hdmi_lpe_audio_driver); 1847MODULE_ALIAS("platform:hdmi_lpe_audio"); 1848 1849MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1850MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1851MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1852MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1853MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1854MODULE_LICENSE("GPL v2"); 1855