162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (C) ST-Ericsson SA 2012
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
662306a36Sopenharmony_ci *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
762306a36Sopenharmony_ci *         for ST-Ericsson.
862306a36Sopenharmony_ci */
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#ifndef UX500_msp_dai_H
1162306a36Sopenharmony_ci#define UX500_msp_dai_H
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#include <linux/types.h>
1462306a36Sopenharmony_ci#include <linux/spinlock.h>
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci#include "ux500_msp_i2s.h"
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ci#define UX500_NBR_OF_DAI	4
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci#define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |	\
2162306a36Sopenharmony_ci			SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci#define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_8_KHZ		31
2662306a36Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_16_KHZ	124
2762306a36Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_44_1_KHZ	63
2862306a36Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_48_KHZ	49
2962306a36Sopenharmony_ci#define FRAME_PER_2_SLOTS				31
3062306a36Sopenharmony_ci#define FRAME_PER_8_SLOTS				138
3162306a36Sopenharmony_ci#define FRAME_PER_16_SLOTS				277
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci#define UX500_MSP_INTERNAL_CLOCK_FREQ  40000000
3462306a36Sopenharmony_ci#define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci#define UX500_MSP_MIN_CHANNELS		1
3762306a36Sopenharmony_ci#define UX500_MSP_MAX_CHANNELS		8
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci#define PLAYBACK_CONFIGURED		1
4062306a36Sopenharmony_ci#define CAPTURE_CONFIGURED		2
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_cienum ux500_msp_clock_id {
4362306a36Sopenharmony_ci	UX500_MSP_MASTER_CLOCK,
4462306a36Sopenharmony_ci};
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_cistruct ux500_msp_i2s_drvdata {
4762306a36Sopenharmony_ci	struct ux500_msp *msp;
4862306a36Sopenharmony_ci	struct regulator *reg_vape;
4962306a36Sopenharmony_ci	unsigned int fmt;
5062306a36Sopenharmony_ci	unsigned int tx_mask;
5162306a36Sopenharmony_ci	unsigned int rx_mask;
5262306a36Sopenharmony_ci	int slots;
5362306a36Sopenharmony_ci	int slot_width;
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci	/* Clocks */
5662306a36Sopenharmony_ci	unsigned int master_clk;
5762306a36Sopenharmony_ci	struct clk *clk;
5862306a36Sopenharmony_ci	struct clk *pclk;
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci	/* Regulators */
6162306a36Sopenharmony_ci	int vape_opp_constraint;
6262306a36Sopenharmony_ci};
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_ciint ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci#endif
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