162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * omap-dmic.h  --  OMAP Digital Microphone Controller
462306a36Sopenharmony_ci */
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#ifndef _OMAP_DMIC_H
762306a36Sopenharmony_ci#define _OMAP_DMIC_H
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci#define OMAP_DMIC_REVISION_REG		0x00
1062306a36Sopenharmony_ci#define OMAP_DMIC_SYSCONFIG_REG		0x10
1162306a36Sopenharmony_ci#define OMAP_DMIC_IRQSTATUS_RAW_REG	0x24
1262306a36Sopenharmony_ci#define OMAP_DMIC_IRQSTATUS_REG		0x28
1362306a36Sopenharmony_ci#define OMAP_DMIC_IRQENABLE_SET_REG	0x2C
1462306a36Sopenharmony_ci#define OMAP_DMIC_IRQENABLE_CLR_REG	0x30
1562306a36Sopenharmony_ci#define OMAP_DMIC_IRQWAKE_EN_REG	0x34
1662306a36Sopenharmony_ci#define OMAP_DMIC_DMAENABLE_SET_REG	0x38
1762306a36Sopenharmony_ci#define OMAP_DMIC_DMAENABLE_CLR_REG	0x3C
1862306a36Sopenharmony_ci#define OMAP_DMIC_DMAWAKEEN_REG		0x40
1962306a36Sopenharmony_ci#define OMAP_DMIC_CTRL_REG		0x44
2062306a36Sopenharmony_ci#define OMAP_DMIC_DATA_REG		0x48
2162306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_CTRL_REG		0x4C
2262306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC1R_DATA_REG	0x50
2362306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC1L_DATA_REG	0x54
2462306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC2R_DATA_REG	0x58
2562306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC2L_DATA_REG	0x5C
2662306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC3R_DATA_REG	0x60
2762306a36Sopenharmony_ci#define OMAP_DMIC_FIFO_DMIC3L_DATA_REG	0x64
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci/* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
3062306a36Sopenharmony_ci#define OMAP_DMIC_IRQ			(1 << 0)
3162306a36Sopenharmony_ci#define OMAP_DMIC_IRQ_FULL		(1 << 1)
3262306a36Sopenharmony_ci#define OMAP_DMIC_IRQ_ALMST_EMPTY	(1 << 2)
3362306a36Sopenharmony_ci#define OMAP_DMIC_IRQ_EMPTY		(1 << 3)
3462306a36Sopenharmony_ci#define OMAP_DMIC_IRQ_MASK		0x07
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci/* DMIC_DMAENABLE bit fields */
3762306a36Sopenharmony_ci#define OMAP_DMIC_DMA_ENABLE		0x1
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci/* DMIC_CTRL bit fields */
4062306a36Sopenharmony_ci#define OMAP_DMIC_UP1_ENABLE		(1 << 0)
4162306a36Sopenharmony_ci#define OMAP_DMIC_UP2_ENABLE		(1 << 1)
4262306a36Sopenharmony_ci#define OMAP_DMIC_UP3_ENABLE		(1 << 2)
4362306a36Sopenharmony_ci#define OMAP_DMIC_UP_ENABLE_MASK	0x7
4462306a36Sopenharmony_ci#define OMAP_DMIC_FORMAT		(1 << 3)
4562306a36Sopenharmony_ci#define OMAP_DMIC_POLAR1		(1 << 4)
4662306a36Sopenharmony_ci#define OMAP_DMIC_POLAR2		(1 << 5)
4762306a36Sopenharmony_ci#define OMAP_DMIC_POLAR3		(1 << 6)
4862306a36Sopenharmony_ci#define OMAP_DMIC_POLAR_MASK		(0x7 << 4)
4962306a36Sopenharmony_ci#define OMAP_DMIC_CLK_DIV(x)		(((x) & 0x7) << 7)
5062306a36Sopenharmony_ci#define OMAP_DMIC_CLK_DIV_MASK		(0x7 << 7)
5162306a36Sopenharmony_ci#define	OMAP_DMIC_RESET			(1 << 10)
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci#define OMAP_DMICOUTFORMAT_LJUST	(0 << 3)
5462306a36Sopenharmony_ci#define OMAP_DMICOUTFORMAT_RJUST	(1 << 3)
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci/* DMIC_FIFO_CTRL bit fields */
5762306a36Sopenharmony_ci#define OMAP_DMIC_THRES_MAX		0xF
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_cienum omap_dmic_clk {
6062306a36Sopenharmony_ci	OMAP_DMIC_SYSCLK_PAD_CLKS,		/* PAD_CLKS */
6162306a36Sopenharmony_ci	OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS,		/* SLIMBUS_CLK */
6262306a36Sopenharmony_ci	OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS,		/* DMIC_SYNC_MUX_CLK */
6362306a36Sopenharmony_ci	OMAP_DMIC_ABE_DMIC_CLK,			/* abe_dmic_clk */
6462306a36Sopenharmony_ci};
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci#endif
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