1// SPDX-License-Identifier: GPL-2.0-only 2// 3// tegra210_sfc.c - Tegra210 SFC driver 4// 5// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6 7#include <linux/clk.h> 8#include <linux/device.h> 9#include <linux/io.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/regmap.h> 16#include <sound/core.h> 17#include <sound/pcm.h> 18#include <sound/pcm_params.h> 19#include <sound/soc.h> 20 21#include "tegra210_sfc.h" 22#include "tegra_cif.h" 23 24#define UNSUPP_CONV ((void *)(-EOPNOTSUPP)) 25#define BYPASS_CONV NULL 26 27static const struct reg_default tegra210_sfc_reg_defaults[] = { 28 { TEGRA210_SFC_RX_INT_MASK, 0x00000001}, 29 { TEGRA210_SFC_RX_CIF_CTRL, 0x00007700}, 30 { TEGRA210_SFC_TX_INT_MASK, 0x00000001}, 31 { TEGRA210_SFC_TX_CIF_CTRL, 0x00007700}, 32 { TEGRA210_SFC_CG, 0x1}, 33 { TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000}, 34}; 35 36static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = { 37 8000, 38 11025, 39 16000, 40 22050, 41 24000, 42 32000, 43 44100, 44 48000, 45 64000, 46 88200, 47 96000, 48 176400, 49 192000, 50}; 51 52/* coeff RAM tables required for SFC */ 53static u32 coef_8to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 54 0x000c6102,//header 55 0x0001d727,//input gain 56 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 57 0x00e55557, 0xffcadd5b, 0x003d80ba, 58 0x00d13397, 0xfff232f8, 0x00683337, 59 0x00000002,//output gain 60 0x0018a102,//header 61 0x000005d6,//input gain 62 0x00c6543e, 0xff342935, 0x0052f116, 63 0x000a1d78, 0xff3330c0, 0x005f88a3, 64 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 65 0x00000003,//output gain 66 0x00235204,//farrow 67 0x000aaaab, 68 0xffaaaaab, 69 0xfffaaaab, 70 0x00555555, 71 0xff600000, 72 0xfff55555, 73 0x00155555, 74 0x00055555, 75 0xffeaaaab, 76 0x00200000, 77 0x00005102,//header 78 0x0000015f,//input gain 79 0x00a7909c, 0xff241c71, 0x005f5e00, 80 0xffca77f4, 0xff20dd50, 0x006855eb, 81 0xff86c552, 0xff18137a, 0x00773648, 82 0x00000001//output gain 83}; 84 85static u32 coef_8to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 86 0x00006102,//header 87 0x0001d727,//input gain 88 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 89 0x00e55557, 0xffcadd5b, 0x003d80ba, 90 0x00d13397, 0xfff232f8, 0x00683337, 91 0x00000002//output gain 92}; 93 94static u32 coef_8to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 95 0x000c6102,//header 96 0x0001d727,//input gain 97 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 98 0x00e55557, 0xffcadd5b, 0x003d80ba, 99 0x00d13397, 0xfff232f8, 0x00683337, 100 0x00000002,//output gain 101 0x0018a102,//header 102 0x000005d6,//input gain 103 0x00c6543e, 0xff342935, 0x0052f116, 104 0x000a1d78, 0xff3330c0, 0x005f88a3, 105 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 106 0x00000003,//output gain 107 0x00230204,//farrow 108 0x000aaaab, 109 0xffaaaaab, 110 0xfffaaaab, 111 0x00555555, 112 0xff600000, 113 0xfff55555, 114 0x00155555, 115 0x00055555, 116 0xffeaaaab, 117 0x00200000, 118 0x00005102,//header 119 0x000005f3,//input gain 120 0x00d816d6, 0xff385383, 0x004fe566, 121 0x003c548d, 0xff38c23d, 0x005d0b1c, 122 0xfff02f7d, 0xff31e983, 0x0072d65d, 123 0x00000001//output gain 124}; 125 126static u32 coef_8to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 127 0x0000a105,//header 128 0x000005e1,//input gain 129 0x00dca92f, 0xff45647a, 0x0046b59c, 130 0x00429d1e, 0xff4fec62, 0x00516d30, 131 0xffdea779, 0xff5e08ba, 0x0060185e, 132 0xffafbab2, 0xff698d5a, 0x006ce3ae, 133 0xff9a82d2, 0xff704674, 0x007633c5, 134 0xff923433, 0xff721128, 0x007cff42, 135 0x00000003//output gain 136}; 137 138static u32 coef_8to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 139 0x000c6102,//header 140 0x0001d727,//input gain 141 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 142 0x00e55557, 0xffcadd5b, 0x003d80ba, 143 0x00d13397, 0xfff232f8, 0x00683337, 144 0x00000002,//output gain 145 0x00006102,//header 146 0x000013d9,//input gain 147 0x00ebd477, 0xff4ce383, 0x0042049d, 148 0x0089c278, 0xff54414d, 0x00531ded, 149 0x004a5e07, 0xff53cf41, 0x006efbdc, 150 0x00000002//output gain 151}; 152 153static u32 coef_8to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 154 0x0156105,//interpolation + IIR filter 155 0x0000d649,//input gain 156 0x00e87afb, 0xff5f69d0, 0x003df3cf, 157 0x007ce488, 0xff99a5c8, 0x0056a6a0, 158 0x00344928, 0xffcba3e5, 0x006be470, 159 0x00137aa7, 0xffe60276, 0x00773410, 160 0x0005fa2a, 0xfff1ac11, 0x007c795b, 161 0x00012d36, 0xfff5eca2, 0x007f10ef, 162 0x00000002,//ouptut gain 163 0x0021a102,//interpolation + IIR filter 164 0x00000e00,//input gain 165 0x00e2e000, 0xff6e1a00, 0x002aaa00, 166 0x00610a00, 0xff5dda00, 0x003ccc00, 167 0x00163a00, 0xff3c0400, 0x00633200, 168 0x00000003,//Output gain 169 0x00000204,//Farrow filter 170 0x000aaaab, 171 0xffaaaaab, 172 0xfffaaaab, 173 0x00555555, 174 0xff600000, 175 0xfff55555, 176 0x00155555, 177 0x00055555, 178 0xffeaaaab, 179 0x00200000 180}; 181 182static u32 coef_8to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 183 0x00156105,//interpolation + IIR Filter 184 0x0000d649,//input gain 185 0x00e87afb, 0xff5f69d0, 0x003df3cf, 186 0x007ce488, 0xff99a5c8, 0x0056a6a0, 187 0x00344928, 0xffcba3e5, 0x006be470, 188 0x00137aa7, 0xffe60276, 0x00773410, 189 0x0005fa2a, 0xfff1ac11, 0x007c795b, 190 0x00012d36, 0xfff5eca2, 0x007f10ef, 191 0x00000002,//ouptut gain 192 0x0000a102,//interpolation + IIR filter 193 0x00000e00,//input gain 194 0x00e2e000, 0xff6e1a00, 0x002aaa00, 195 0x00610a00, 0xff5dda00, 0x003ccc00, 196 0x00163a00, 0xff3c0400, 0x00633200, 197 0x00000003//output gain 198}; 199 200static u32 coef_8to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 201 0x000c6102,//header 202 0x0001d727,//input gain 203 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 204 0x00e55557, 0xffcadd5b, 0x003d80ba, 205 0x00d13397, 0xfff232f8, 0x00683337, 206 0x00000002,//output gain 207 0x00186102,//header 208 0x000013d9,//input gain 209 0x00ebd477, 0xff4ce383, 0x0042049d, 210 0x0089c278, 0xff54414d, 0x00531ded, 211 0x004a5e07, 0xff53cf41, 0x006efbdc, 212 0x00000002,//output gain 213 0x0024a102,//header 214 0x0000007d,//input gain 215 0x007d1f20, 0xff1a540e, 0x00678bf9, 216 0xff916625, 0xff16b0ff, 0x006e433a, 217 0xff5af660, 0xff0eb91f, 0x00797356, 218 0x00000003,//output gain 219 0x00000204,//farrow 220 0x000aaaab, 221 0xffaaaaab, 222 0xfffaaaab, 223 0x00555555, 224 0xff600000, 225 0xfff55555, 226 0x00155555, 227 0x00055555, 228 0xffeaaaab, 229 0x00200000 230}; 231 232static u32 coef_8to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 233 0x000c6102,//header 234 0x0001d727,//input gain 235 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 236 0x00e55557, 0xffcadd5b, 0x003d80ba, 237 0x00d13397, 0xfff232f8, 0x00683337, 238 0x00000002,//output gain 239 0x00186102,//header 240 0x000013d9,//input gain 241 0x00ebd477, 0xff4ce383, 0x0042049d, 242 0x0089c278, 0xff54414d, 0x00531ded, 243 0x004a5e07, 0xff53cf41, 0x006efbdc, 244 0x00000002,//output gain 245 0x0000a102,//header 246 0x0000007d,//input gain 247 0x007d1f20, 0xff1a540e, 0x00678bf9, 248 0xff916625, 0xff16b0ff, 0x006e433a, 249 0xff5af660, 0xff0eb91f, 0x00797356, 250 0x00000003//output gain 251}; 252 253static u32 coef_11to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 254 0x000c6102,//header 255 0x0000015f,//input gain 256 0x00a7909c, 0xff241c71, 0x005f5e00, 257 0xffca77f4, 0xff20dd50, 0x006855eb, 258 0xff86c552, 0xff18137a, 0x00773648, 259 0x00000002,//output gain 260 0x00186102,//header 261 0x000005f3,//input gain 262 0x00d816d6, 0xff385383, 0x004fe566, 263 0x003c548d, 0xff38c23d, 0x005d0b1c, 264 0xfff02f7d, 0xff31e983, 0x0072d65d, 265 0x00000002,//output gain 266 0x00239204,//farrow 267 0x000aaaab, 268 0xffaaaaab, 269 0xfffaaaab, 270 0x00555555, 271 0xff600000, 272 0xfff55555, 273 0x00155555, 274 0x00055555, 275 0xffeaaaab, 276 0x00200000, 277 0x00005102,//header 278 0x0001d727,//input gain 279 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 280 0x00e55557, 0xffcadd5b, 0x003d80ba, 281 0x00d13397, 0xfff232f8, 0x00683337, 282 0x00000001//output gain 283}; 284 285static u32 coef_11to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 286 0x000c6102,//header 287 0x0001d727,//input gain 288 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 289 0x00e55557, 0xffcadd5b, 0x003d80ba, 290 0x00d13397, 0xfff232f8, 0x00683337, 291 0x00000002,//output gain 292 0x00186102,//header 293 0x000013d9,//input gain 294 0x00ebd477, 0xff4ce383, 0x0042049d, 295 0x0089c278, 0xff54414d, 0x00531ded, 296 0x004a5e07, 0xff53cf41, 0x006efbdc, 297 0x00000002,//output gain 298 0x00009204,//farrow 299 0x000aaaab, 300 0xffaaaaab, 301 0xfffaaaab, 302 0x00555555, 303 0xff600000, 304 0xfff55555, 305 0x00155555, 306 0x00055555, 307 0xffeaaaab, 308 0x00200000 309}; 310 311static u32 coef_11to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 312 0x00006102,//header 313 0x0001d727,//input gain 314 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 315 0x00e55557, 0xffcadd5b, 0x003d80ba, 316 0x00d13397, 0xfff232f8, 0x00683337, 317 0x00000002//output gain 318}; 319 320static u32 coef_11to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 321 0x000c6102,//header 322 0x0001d727,//input gain 323 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 324 0x00e55557, 0xffcadd5b, 0x003d80ba, 325 0x00d13397, 0xfff232f8, 0x00683337, 326 0x00000002,//output gain 327 0x00186102,//header 328 0x000013d9,//input gain 329 0x00ebd477, 0xff4ce383, 0x0042049d, 330 0x0089c278, 0xff54414d, 0x00531ded, 331 0x004a5e07, 0xff53cf41, 0x006efbdc, 332 0x00000002,//output gain 333 0x00005204,//farrow 334 0x000aaaab, 335 0xffaaaaab, 336 0xfffaaaab, 337 0x00555555, 338 0xff600000, 339 0xfff55555, 340 0x00155555, 341 0x00055555, 342 0xffeaaaab, 343 0x00200000 344}; 345 346static u32 coef_11to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 347 0x000c6102,//header 348 0x0001d727,//input gain 349 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 350 0x00e55557, 0xffcadd5b, 0x003d80ba, 351 0x00d13397, 0xfff232f8, 0x00683337, 352 0x00000002,//output gain 353 0x00186102,//header 354 0x000013d9,//input gain 355 0x00ebd477, 0xff4ce383, 0x0042049d, 356 0x0089c278, 0xff54414d, 0x00531ded, 357 0x004a5e07, 0xff53cf41, 0x006efbdc, 358 0x00000002,//output gain 359 0x00246102,//header 360 0x0000010a,//input gain 361 0x00c93dc4, 0xff26f5f6, 0x005d1041, 362 0x001002c4, 0xff245b76, 0x00666002, 363 0xffc30a45, 0xff1baecd, 0x00765921, 364 0x00000002,//output gain 365 0x00009204,//farrow 366 0x000aaaab, 367 0xffaaaaab, 368 0xfffaaaab, 369 0x00555555, 370 0xff600000, 371 0xfff55555, 372 0x00155555, 373 0x00055555, 374 0xffeaaaab, 375 0x00200000 376}; 377 378static u32 coef_11to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 379 0x000c6102,//header 380 0x0001d727,//input gain 381 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 382 0x00e55557, 0xffcadd5b, 0x003d80ba, 383 0x00d13397, 0xfff232f8, 0x00683337, 384 0x00000002,//output gain 385 0x00006102,//header 386 0x000013d9,//input gain 387 0x00ebd477, 0xff4ce383, 0x0042049d, 388 0x0089c278, 0xff54414d, 0x00531ded, 389 0x004a5e07, 0xff53cf41, 0x006efbdc, 390 0x00000002//output gain 391}; 392 393static u32 coef_11to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 394 0x000c6102,//header 395 0x0001d727,//input gain 396 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 397 0x00e55557, 0xffcadd5b, 0x003d80ba, 398 0x00d13397, 0xfff232f8, 0x00683337, 399 0x00000002,//output gain 400 0x00186102,//header 401 0x000013d9,//input gain 402 0x00ebd477, 0xff4ce383, 0x0042049d, 403 0x0089c278, 0xff54414d, 0x00531ded, 404 0x004a5e07, 0xff53cf41, 0x006efbdc, 405 0x00000002,//output gain 406 0x00246102,//header 407 0x0000010a,//input gain 408 0x00c93dc4, 0xff26f5f6, 0x005d1041, 409 0x001002c4, 0xff245b76, 0x00666002, 410 0xffc30a45, 0xff1baecd, 0x00765921, 411 0x00000002,//output gain 412 0x00005204,//farrow 413 0x000aaaab, 414 0xffaaaaab, 415 0xfffaaaab, 416 0x00555555, 417 0xff600000, 418 0xfff55555, 419 0x00155555, 420 0x00055555, 421 0xffeaaaab, 422 0x00200000 423}; 424 425static u32 coef_11to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 426 0x000c6102,//header 427 0x0001d727,//input gain 428 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 429 0x00e55557, 0xffcadd5b, 0x003d80ba, 430 0x00d13397, 0xfff232f8, 0x00683337, 431 0x00000002,//output gain 432 0x00186102,//header 433 0x000013d9,//input gain 434 0x00ebd477, 0xff4ce383, 0x0042049d, 435 0x0089c278, 0xff54414d, 0x00531ded, 436 0x004a5e07, 0xff53cf41, 0x006efbdc, 437 0x00000002,//output gain 438 0x00006102,//header 439 0x0000010a,//input gain 440 0x00c93dc4, 0xff26f5f6, 0x005d1041, 441 0x001002c4, 0xff245b76, 0x00666002, 442 0xffc30a45, 0xff1baecd, 0x00765921, 443 0x00000002//output gain 444}; 445 446static u32 coef_11to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 447 0x000c6102,//header 448 0x0001d727,//input gain 449 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 450 0x00e55557, 0xffcadd5b, 0x003d80ba, 451 0x00d13397, 0xfff232f8, 0x00683337, 452 0x00000002,//output gain 453 0x00186102,//header 454 0x000013d9,//input gain 455 0x00ebd477, 0xff4ce383, 0x0042049d, 456 0x0089c278, 0xff54414d, 0x00531ded, 457 0x004a5e07, 0xff53cf41, 0x006efbdc, 458 0x00000002,//output gain 459 0x00246102,//header 460 0x0000010a,//input gain 461 0x00c93dc4, 0xff26f5f6, 0x005d1041, 462 0x001002c4, 0xff245b76, 0x00666002, 463 0xffc30a45, 0xff1baecd, 0x00765921, 464 0x00000002,//output gain 465 0x00000204,//farrow 466 0x000aaaab, 467 0xffaaaaab, 468 0xfffaaaab, 469 0x00555555, 470 0xff600000, 471 0xfff55555, 472 0x00155555, 473 0x00055555, 474 0xffeaaaab, 475 0x00200000 476}; 477 478static u32 coef_16to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 479 0x00005102,//header 480 0x0001d727,//input gain 481 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 482 0x00e55557, 0xffcadd5b, 0x003d80ba, 483 0x00d13397, 0xfff232f8, 0x00683337, 484 0x00000001//output gain 485}; 486 487static u32 coef_16to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 488 0x000fa103,//header 489 0x000001e0,//input gain 490 0x00de44c0, 0xff380b7f, 0x004ffc73, 491 0x00494b44, 0xff3d493a, 0x005908bf, 492 0xffe9a3c8, 0xff425647, 0x006745f7, 493 0xffc42d61, 0xff40a6c7, 0x00776709, 494 0x00000003,//output gain 495 0x001a5204,//farrow 496 0x000aaaab, 497 0xffaaaaab, 498 0xfffaaaab, 499 0x00555555, 500 0xff600000, 501 0xfff55555, 502 0x00155555, 503 0x00055555, 504 0xffeaaaab, 505 0x00200000, 506 0x00005102,//header 507 0x0001d727,//input gain 508 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 509 0x00e55557, 0xffcadd5b, 0x003d80ba, 510 0x00d13397, 0xfff232f8, 0x00683337, 511 0x00000001//output gain 512}; 513 514static u32 coef_16to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 515 0x000c6102,//header 516 0x0001d727,//input gain 517 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 518 0x00e55557, 0xffcadd5b, 0x003d80ba, 519 0x00d13397, 0xfff232f8, 0x00683337, 520 0x00000002,//output gain 521 0x0018a102,//header 522 0x000005d6,//input gain 523 0x00c6543e, 0xff342935, 0x0052f116, 524 0x000a1d78, 0xff3330c0, 0x005f88a3, 525 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 526 0x00000003,//output gain 527 0x00235204,//farrow 528 0x000aaaab, 529 0xffaaaaab, 530 0xfffaaaab, 531 0x00555555, 532 0xff600000, 533 0xfff55555, 534 0x00155555, 535 0x00055555, 536 0xffeaaaab, 537 0x00200000, 538 0x00005102,//header 539 0x0000015f,//input gain 540 0x00a7909c, 0xff241c71, 0x005f5e00, 541 0xffca77f4, 0xff20dd50, 0x006855eb, 542 0xff86c552, 0xff18137a, 0x00773648, 543 0x00000001//output gain 544}; 545 546static u32 coef_16to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 547 0x0015a105,//header 548 0x00000292,//input gain 549 0x00e4320a, 0xff41d2d9, 0x004911ac, 550 0x005dd9e3, 0xff4c7d80, 0x0052103e, 551 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 552 0xffc4b414, 0xff68582c, 0x006b38e5, 553 0xffabb861, 0xff704bec, 0x0074de52, 554 0xffa19f4c, 0xff729059, 0x007c7e90, 555 0x00000003,//output gain 556 0x00005105,//header 557 0x00000292,//input gain 558 0x00e4320a, 0xff41d2d9, 0x004911ac, 559 0x005dd9e3, 0xff4c7d80, 0x0052103e, 560 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 561 0xffc4b414, 0xff68582c, 0x006b38e5, 562 0xffabb861, 0xff704bec, 0x0074de52, 563 0xffa19f4c, 0xff729059, 0x007c7e90, 564 0x00000001//output gain 565}; 566 567static u32 coef_16to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 568 0x00006102,//header 569 0x0001d727,//input gain 570 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 571 0x00e55557, 0xffcadd5b, 0x003d80ba, 572 0x00d13397, 0xfff232f8, 0x00683337, 573 0x00000002//output gain 574}; 575 576static u32 coef_16to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 577 0x00156105,//interpolation + IIR filter 578 0x0000d649,//input gain 579 0x00e87afb, 0xff5f69d0, 0x003df3cf, 580 0x007ce488, 0xff99a5c8, 0x0056a6a0, 581 0x00344928, 0xffcba3e5, 0x006be470, 582 0x00137aa7, 0xffe60276, 0x00773410, 583 0x0005fa2a, 0xfff1ac11, 0x007c795b, 584 0x00012d36, 0xfff5eca2, 0x007f10ef, 585 0x00000002,//output gain 586 0x0021a102,//interpolation + IIR filter 587 0x00000e00,//input gain 588 0x00e2e000, 0xff6e1a00, 0x002aaa00, 589 0x00610a00, 0xff5dda00, 0x003ccc00, 590 0x00163a00, 0xff3c0400, 0x00633200, 591 0x00000003,//output gain 592 0x002c0204,//Farrow Filter 593 0x000aaaab, 594 0xffaaaaab, 595 0xfffaaaab, 596 0x00555555, 597 0xff600000, 598 0xfff55555, 599 0x00155555, 600 0x00055555, 601 0xffeaaaab, 602 0x00200000, 603 0x00005101,//IIR Filter + Decimator 604 0x0000203c,//input gain 605 0x00f52d35, 0xff2e2162, 0x005a21e0, 606 0x00c6f0f0, 0xff2ecd69, 0x006fa78d, 607 0x00000001//output gain 608}; 609 610static u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 611 0x0000a105,//interpolation + IIR Filter 612 0x00000784,//input gain 613 0x00cc516e, 0xff2c9639, 0x005ad5b3, 614 0x0013ad0d, 0xff3d4799, 0x0063ce75, 615 0xffb6f398, 0xff5138d1, 0x006e9e1f, 616 0xff9186e5, 0xff5f96a4, 0x0076a86e, 617 0xff82089c, 0xff676b81, 0x007b9f8a, 618 0xff7c48a5, 0xff6a31e7, 0x007ebb7b, 619 0x00000003//output gain 620}; 621 622static u32 coef_16to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 623 0x000c6102,//header 624 0x0001d727,//input gain 625 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 626 0x00e55557, 0xffcadd5b, 0x003d80ba, 627 0x00d13397, 0xfff232f8, 0x00683337, 628 0x00000002,//output gain 629 0x0018a102,//header 630 0x000005d6,//input gain 631 0x00c6543e, 0xff342935, 0x0052f116, 632 0x000a1d78, 0xff3330c0, 0x005f88a3, 633 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 634 0x00000003,//output gain 635 0x00000204,//farrow 636 0x000aaaab, 637 0xffaaaaab, 638 0xfffaaaab, 639 0x00555555, 640 0xff600000, 641 0xfff55555, 642 0x00155555, 643 0x00055555, 644 0xffeaaaab, 645 0x00200000 646}; 647 648static u32 coef_16to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 649 0x000c6102,//header 650 0x0001d727,//input gain 651 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 652 0x00e55557, 0xffcadd5b, 0x003d80ba, 653 0x00d13397, 0xfff232f8, 0x00683337, 654 0x00000002,//output gain 655 0x0000a102,//header 656 0x000005d6,//input gain 657 0x00c6543e, 0xff342935, 0x0052f116, 658 0x000a1d78, 0xff3330c0, 0x005f88a3, 659 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 660 0x00000003//output gain 661}; 662 663static u32 coef_16to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 664 0x000c6102,//header 665 0x0001d727,//input gain 666 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 667 0x00e55557, 0xffcadd5b, 0x003d80ba, 668 0x00d13397, 0xfff232f8, 0x00683337, 669 0x00000002,//output gain 670 0x00186102,//header 671 0x000013d9,//input gain 672 0x00ebd477, 0xff4ce383, 0x0042049d, 673 0x0089c278, 0xff54414d, 0x00531ded, 674 0x004a5e07, 0xff53cf41, 0x006efbdc, 675 0x00000002,//output gain 676 0x0024a102,//header 677 0x0000007d,//input gain 678 0x007d1f20, 0xff1a540e, 0x00678bf9, 679 0xff916625, 0xff16b0ff, 0x006e433a, 680 0xff5af660, 0xff0eb91f, 0x00797356, 681 0x00000003,//output gain 682 0x00000204,//farrow 683 0x000aaaab, 684 0xffaaaaab, 685 0xfffaaaab, 686 0x00555555, 687 0xff600000, 688 0xfff55555, 689 0x00155555, 690 0x00055555, 691 0xffeaaaab, 692 0x00200000 693}; 694 695static u32 coef_16to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 696 0x000c6102,//header 697 0x0001d727,//input gain 698 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 699 0x00e55557, 0xffcadd5b, 0x003d80ba, 700 0x00d13397, 0xfff232f8, 0x00683337, 701 0x00000002,//output gain 702 0x00186102,//header 703 0x000013d9,//input gain 704 0x00ebd477, 0xff4ce383, 0x0042049d, 705 0x0089c278, 0xff54414d, 0x00531ded, 706 0x004a5e07, 0xff53cf41, 0x006efbdc, 707 0x00000002,//output gain 708 0x0000a102,//header 709 0x0000007d,//input gain 710 0x007d1f20, 0xff1a540e, 0x00678bf9, 711 0xff916625, 0xff16b0ff, 0x006e433a, 712 0xff5af660, 0xff0eb91f, 0x00797356, 713 0x00000003//output gain 714}; 715 716static u32 coef_22to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 717 0x000c6102,//header 718 0x000005f3,//input gain 719 0x00d816d6, 0xff385383, 0x004fe566, 720 0x003c548d, 0xff38c23d, 0x005d0b1c, 721 0xfff02f7d, 0xff31e983, 0x0072d65d, 722 0x00000002,//output gain 723 0x00179204,//farrow 724 0x000aaaab, 725 0xffaaaaab, 726 0xfffaaaab, 727 0x00555555, 728 0xff600000, 729 0xfff55555, 730 0x00155555, 731 0x00055555, 732 0xffeaaaab, 733 0x00200000, 734 0x00005102,//header 735 0x0001d727,//input gain 736 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 737 0x00e55557, 0xffcadd5b, 0x003d80ba, 738 0x00d13397, 0xfff232f8, 0x00683337, 739 0x00000001//output gain 740}; 741 742static u32 coef_22to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 743 0x00005102,//header 744 0x0001d727,//input gain 745 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 746 0x00e55557, 0xffcadd5b, 0x003d80ba, 747 0x00d13397, 0xfff232f8, 0x00683337, 748 0x00000001//output gain 749}; 750 751static u32 coef_22to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 752 0x000c6102,//header 753 0x0000015f,//input gain 754 0x00a7909c, 0xff241c71, 0x005f5e00, 755 0xffca77f4, 0xff20dd50, 0x006855eb, 756 0xff86c552, 0xff18137a, 0x00773648, 757 0x00000002,//output gain 758 0x00186102,//header 759 0x000005f3,//input gain 760 0x00d816d6, 0xff385383, 0x004fe566, 761 0x003c548d, 0xff38c23d, 0x005d0b1c, 762 0xfff02f7d, 0xff31e983, 0x0072d65d, 763 0x00000002,//output gain 764 0x00239204,//farrow 765 0x000aaaab, 766 0xffaaaaab, 767 0xfffaaaab, 768 0x00555555, 769 0xff600000, 770 0xfff55555, 771 0x00155555, 772 0x00055555, 773 0xffeaaaab, 774 0x00200000, 775 0x00005102,//header 776 0x0001d727,//input gain 777 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 778 0x00e55557, 0xffcadd5b, 0x003d80ba, 779 0x00d13397, 0xfff232f8, 0x00683337, 780 0x00000001//output gain 781}; 782 783static u32 coef_22to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 784 0x000c6102,//header 785 0x0001d727,//input gain 786 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 787 0x00e55557, 0xffcadd5b, 0x003d80ba, 788 0x00d13397, 0xfff232f8, 0x00683337, 789 0x00000002,//output gain 790 0x00186102,//header 791 0x000013d9,//input gain 792 0x00ebd477, 0xff4ce383, 0x0042049d, 793 0x0089c278, 0xff54414d, 0x00531ded, 794 0x004a5e07, 0xff53cf41, 0x006efbdc, 795 0x00000002,//output gain 796 0x00235204,//farrow 797 0x000aaaab, 798 0xffaaaaab, 799 0xfffaaaab, 800 0x00555555, 801 0xff600000, 802 0xfff55555, 803 0x00155555, 804 0x00055555, 805 0xffeaaaab, 806 0x00200000, 807 0x00005102,//header 808 0x0001d029,//input gain 809 0x00f2a98b, 0xff92aa71, 0x001fcd16, 810 0x00ae9004, 0xffb85140, 0x0041813a, 811 0x007f8ed1, 0xffd585fc, 0x006a69e6, 812 0x00000001//output gain 813}; 814 815static u32 coef_22to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 816 0x000c6102,//header 817 0x0001d727,//input gain 818 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 819 0x00e55557, 0xffcadd5b, 0x003d80ba, 820 0x00d13397, 0xfff232f8, 0x00683337, 821 0x00000002,//output gain 822 0x00186102,//header 823 0x000013d9,//input gain 824 0x00ebd477, 0xff4ce383, 0x0042049d, 825 0x0089c278, 0xff54414d, 0x00531ded, 826 0x004a5e07, 0xff53cf41, 0x006efbdc, 827 0x00000002,//output gain 828 0x00009204,//farrow 829 0x000aaaab, 830 0xffaaaaab, 831 0xfffaaaab, 832 0x00555555, 833 0xff600000, 834 0xfff55555, 835 0x00155555, 836 0x00055555, 837 0xffeaaaab, 838 0x00200000 839}; 840 841static u32 coef_22to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 842 0x00006102,//header 843 0x0001d727,//input gain 844 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 845 0x00e55557, 0xffcadd5b, 0x003d80ba, 846 0x00d13397, 0xfff232f8, 0x00683337, 847 0x00000002//output gain 848}; 849 850static u32 coef_22to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 851 0x000c6102,//header 852 0x0001d727,//input gain 853 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 854 0x00e55557, 0xffcadd5b, 0x003d80ba, 855 0x00d13397, 0xfff232f8, 0x00683337, 856 0x00000002,//output gain 857 0x00186102,//header 858 0x000013d9,//input gain 859 0x00ebd477, 0xff4ce383, 0x0042049d, 860 0x0089c278, 0xff54414d, 0x00531ded, 861 0x004a5e07, 0xff53cf41, 0x006efbdc, 862 0x00000002,//output gain 863 0x00005204,//farrow 864 0x000aaaab, 865 0xffaaaaab, 866 0xfffaaaab, 867 0x00555555, 868 0xff600000, 869 0xfff55555, 870 0x00155555, 871 0x00055555, 872 0xffeaaaab, 873 0x00200000 874}; 875 876static u32 coef_22to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 877 0x000c6102,//header 878 0x0001d727,//input gain 879 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 880 0x00e55557, 0xffcadd5b, 0x003d80ba, 881 0x00d13397, 0xfff232f8, 0x00683337, 882 0x00000002,//output gain 883 0x00006102,//header 884 0x000013d9,//input gain 885 0x00ebd477, 0xff4ce383, 0x0042049d, 886 0x0089c278, 0xff54414d, 0x00531ded, 887 0x004a5e07, 0xff53cf41, 0x006efbdc, 888 0x00000002//output gain 889}; 890 891static u32 coef_22to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 892 0x000c6102,//header 893 0x0001d727,//input gain 894 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 895 0x00e55557, 0xffcadd5b, 0x003d80ba, 896 0x00d13397, 0xfff232f8, 0x00683337, 897 0x00000002,//output gain 898 0x00186102,//header 899 0x000013d9,//input gain 900 0x00ebd477, 0xff4ce383, 0x0042049d, 901 0x0089c278, 0xff54414d, 0x00531ded, 902 0x004a5e07, 0xff53cf41, 0x006efbdc, 903 0x00000002,//output gain 904 0x00246102,//header 905 0x0000010a,//input gain 906 0x00c93dc4, 0xff26f5f6, 0x005d1041, 907 0x001002c4, 0xff245b76, 0x00666002, 908 0xffc30a45, 0xff1baecd, 0x00765921, 909 0x00000002,//output gain 910 0x00005204,//farrow 911 0x000aaaab, 912 0xffaaaaab, 913 0xfffaaaab, 914 0x00555555, 915 0xff600000, 916 0xfff55555, 917 0x00155555, 918 0x00055555, 919 0xffeaaaab, 920 0x00200000 921}; 922 923static u32 coef_22to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 924 0x000c6102,//header 925 0x0001d727,//input gain 926 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 927 0x00e55557, 0xffcadd5b, 0x003d80ba, 928 0x00d13397, 0xfff232f8, 0x00683337, 929 0x00000002,//output gain 930 0x00186102,//header 931 0x000013d9,//input gain 932 0x00ebd477, 0xff4ce383, 0x0042049d, 933 0x0089c278, 0xff54414d, 0x00531ded, 934 0x004a5e07, 0xff53cf41, 0x006efbdc, 935 0x00000002,//output gain 936 0x00006102,//header 937 0x0000010a,//input gain 938 0x00c93dc4, 0xff26f5f6, 0x005d1041, 939 0x001002c4, 0xff245b76, 0x00666002, 940 0xffc30a45, 0xff1baecd, 0x00765921, 941 0x00000002//output gain 942}; 943 944static u32 coef_22to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 945 0x000c6102,//header 946 0x0001d727,//input gain 947 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 948 0x00e55557, 0xffcadd5b, 0x003d80ba, 949 0x00d13397, 0xfff232f8, 0x00683337, 950 0x00000002,//output gain 951 0x00186102,//header 952 0x000013d9,//input gain 953 0x00ebd477, 0xff4ce383, 0x0042049d, 954 0x0089c278, 0xff54414d, 0x00531ded, 955 0x004a5e07, 0xff53cf41, 0x006efbdc, 956 0x00000002,//output gain 957 0x00246102,//header 958 0x0000010a,//input gain 959 0x00c93dc4, 0xff26f5f6, 0x005d1041, 960 0x001002c4, 0xff245b76, 0x00666002, 961 0xffc30a45, 0xff1baecd, 0x00765921, 962 0x00000002,//output gain 963 0x00000204,//farrow 964 0x000aaaab, 965 0xffaaaaab, 966 0xfffaaaab, 967 0x00555555, 968 0xff600000, 969 0xfff55555, 970 0x00155555, 971 0x00055555, 972 0xffeaaaab, 973 0x00200000 974}; 975 976static u32 coef_24to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 977 0x00009105,//header 978 0x000005e1,//input gain 979 0x00dca92f, 0xff45647a, 0x0046b59c, 980 0x00429d1e, 0xff4fec62, 0x00516d30, 981 0xffdea779, 0xff5e08ba, 0x0060185e, 982 0xffafbab2, 0xff698d5a, 0x006ce3ae, 983 0xff9a82d2, 0xff704674, 0x007633c5, 984 0xff923433, 0xff721128, 0x007cff42, 985 0x00000001//output gain 986}; 987 988static u32 coef_24to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 989 0x000f6103,//header 990 0x000001e0,//input gain 991 0x00de44c0, 0xff380b7f, 0x004ffc73, 992 0x00494b44, 0xff3d493a, 0x005908bf, 993 0xffe9a3c8, 0xff425647, 0x006745f7, 994 0xffc42d61, 0xff40a6c7, 0x00776709, 995 0x00000002,//output gain 996 0x001a5204,//farrow 997 0x000aaaab, 998 0xffaaaaab, 999 0xfffaaaab, 1000 0x00555555, 1001 0xff600000, 1002 0xfff55555, 1003 0x00155555, 1004 0x00055555, 1005 0xffeaaaab, 1006 0x00200000, 1007 0x00005102,//header 1008 0x0001d727,//input gain 1009 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1010 0x00e55557, 0xffcadd5b, 0x003d80ba, 1011 0x00d13397, 0xfff232f8, 0x00683337, 1012 0x00000001//output gain 1013}; 1014 1015static u32 coef_24to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1016 0x00156105,//header 1017 0x00000292,//input gain 1018 0x00e4320a, 0xff41d2d9, 0x004911ac, 1019 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1020 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1021 0xffc4b414, 0xff68582c, 0x006b38e5, 1022 0xffabb861, 0xff704bec, 0x0074de52, 1023 0xffa19f4c, 0xff729059, 0x007c7e90, 1024 0x00000002,//output gain 1025 0x00009105,//header 1026 0x00000292,//input gain 1027 0x00e4320a, 0xff41d2d9, 0x004911ac, 1028 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1029 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1030 0xffc4b414, 0xff68582c, 0x006b38e5, 1031 0xffabb861, 0xff704bec, 0x0074de52, 1032 0xffa19f4c, 0xff729059, 0x007c7e90, 1033 0x00000001//output gain 1034}; 1035 1036static u32 coef_24to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1037 0x000c6102,//header 1038 0x0001d029,//input gain 1039 0x00f2a98b, 0xff92aa71, 0x001fcd16, 1040 0x00ae9004, 0xffb85140, 0x0041813a, 1041 0x007f8ed1, 0xffd585fc, 0x006a69e6, 1042 0x00000002,//output gain 1043 0x001b6103,//header 1044 0x000001e0,//input gain 1045 0x00de44c0, 0xff380b7f, 0x004ffc73, 1046 0x00494b44, 0xff3d493a, 0x005908bf, 1047 0xffe9a3c8, 0xff425647, 0x006745f7, 1048 0xffc42d61, 0xff40a6c7, 0x00776709, 1049 0x00000002,//output gain 1050 0x00265204,//farrow 1051 0x000aaaab, 1052 0xffaaaaab, 1053 0xfffaaaab, 1054 0x00555555, 1055 0xff600000, 1056 0xfff55555, 1057 0x00155555, 1058 0x00055555, 1059 0xffeaaaab, 1060 0x00200000, 1061 0x00005102,//header 1062 0x0001d727,//input gain 1063 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1064 0x00e55557, 0xffcadd5b, 0x003d80ba, 1065 0x00d13397, 0xfff232f8, 0x00683337, 1066 0x00000001//output gain 1067}; 1068 1069static u32 coef_24to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1070 0x000c6102,//header 1071 0x0001d727,//input gain 1072 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1073 0x00e55557, 0xffcadd5b, 0x003d80ba, 1074 0x00d13397, 0xfff232f8, 0x00683337, 1075 0x00000002,//output gain 1076 0x00186102,//header 1077 0x000013d9,//input gain 1078 0x00ebd477, 0xff4ce383, 0x0042049d, 1079 0x0089c278, 0xff54414d, 0x00531ded, 1080 0x004a5e07, 0xff53cf41, 0x006efbdc, 1081 0x00000002,//output gain 1082 0x00009102,//header 1083 0x000013d9,//input gain 1084 0x00ebd477, 0xff4ce383, 0x0042049d, 1085 0x0089c278, 0xff54414d, 0x00531ded, 1086 0x004a5e07, 0xff53cf41, 0x006efbdc, 1087 0x00000001//output gain 1088}; 1089 1090static u32 coef_24to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1091 0x000c6102,//header 1092 0x0001d727,//input gain 1093 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1094 0x00e55557, 0xffcadd5b, 0x003d80ba, 1095 0x00d13397, 0xfff232f8, 0x00683337, 1096 0x00000002,//output gain 1097 0x00186102,//header 1098 0x000013d9,//input gain 1099 0x00ebd477, 0xff4ce383, 0x0042049d, 1100 0x0089c278, 0xff54414d, 0x00531ded, 1101 0x004a5e07, 0xff53cf41, 0x006efbdc, 1102 0x00000002,//output gain 1103 0x00230204,//farrow 1104 0x000aaaab, 1105 0xffaaaaab, 1106 0xfffaaaab, 1107 0x00555555, 1108 0xff600000, 1109 0xfff55555, 1110 0x00155555, 1111 0x00055555, 1112 0xffeaaaab, 1113 0x00200000, 1114 0x00005102,//header 1115 0x00001685,//input gain 1116 0x00f53ae9, 0xff52f196, 0x003e3e08, 1117 0x00b9f857, 0xff5d8985, 0x0050070a, 1118 0x008c3e86, 0xff6053f0, 0x006d98ef, 1119 0x00000001//output gain 1120}; 1121 1122static u32 coef_24to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1123 0x00006102,//header 1124 0x0001d727,//input gain 1125 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1126 0x00e55557, 0xffcadd5b, 0x003d80ba, 1127 0x00d13397, 0xfff232f8, 0x00683337, 1128 0x00000002//output gain 1129}; 1130 1131static u32 coef_24to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1132 0x000c6102,//header 1133 0x0001d727,//input gain 1134 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1135 0x00e55557, 0xffcadd5b, 0x003d80ba, 1136 0x00d13397, 0xfff232f8, 0x00683337, 1137 0x00000002,//output gain 1138 0x00186102,//header 1139 0x000013d9,//input gain 1140 0x00ebd477, 0xff4ce383, 0x0042049d, 1141 0x0089c278, 0xff54414d, 0x00531ded, 1142 0x004a5e07, 0xff53cf41, 0x006efbdc, 1143 0x00000002,//output gain 1144 0x00246102,//header 1145 0x0000010a,//input gain 1146 0x00c93dc4, 0xff26f5f6, 0x005d1041, 1147 0x001002c4, 0xff245b76, 0x00666002, 1148 0xffc30a45, 0xff1baecd, 0x00765921, 1149 0x00000002,//output gain 1150 0x002f0204,//farrow 1151 0x000aaaab, 1152 0xffaaaaab, 1153 0xfffaaaab, 1154 0x00555555, 1155 0xff600000, 1156 0xfff55555, 1157 0x00155555, 1158 0x00055555, 1159 0xffeaaaab, 1160 0x00200000, 1161 0x00005102,//header 1162 0x00000138,//input gain 1163 0x00d5d232, 0xff2a3bf8, 0x005a785c, 1164 0x0034001b, 0xff283109, 0x006462a6, 1165 0xffe6746a, 0xff1fb09c, 0x00758a91, 1166 0x00000001//output gain 1167}; 1168 1169static u32 coef_24to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1170 0x000c6102,//header 1171 0x0001d727,//input gain 1172 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1173 0x00e55557, 0xffcadd5b, 0x003d80ba, 1174 0x00d13397, 0xfff232f8, 0x00683337, 1175 0x00000002,//output gain 1176 0x00006102,//header 1177 0x000013d9,//input gain 1178 0x00ebd477, 0xff4ce383, 0x0042049d, 1179 0x0089c278, 0xff54414d, 0x00531ded, 1180 0x004a5e07, 0xff53cf41, 0x006efbdc, 1181 0x00000002//output gain 1182}; 1183 1184static u32 coef_24to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1185 0x000c6102,//header 1186 0x0001d727,//input gain 1187 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1188 0x00e55557, 0xffcadd5b, 0x003d80ba, 1189 0x00d13397, 0xfff232f8, 0x00683337, 1190 0x00000002,//output gain 1191 0x00186102,//header 1192 0x000013d9,//input gain 1193 0x00ebd477, 0xff4ce383, 0x0042049d, 1194 0x0089c278, 0xff54414d, 0x00531ded, 1195 0x004a5e07, 0xff53cf41, 0x006efbdc, 1196 0x00000002,//output gain 1197 0x00246102,//header 1198 0x0000010a,//input gain 1199 0x00c93dc4, 0xff26f5f6, 0x005d1041, 1200 0x001002c4, 0xff245b76, 0x00666002, 1201 0xffc30a45, 0xff1baecd, 0x00765921, 1202 0x00000002,//output gain 1203 0x00000204,//farrow 1204 0x000aaaab, 1205 0xffaaaaab, 1206 0xfffaaaab, 1207 0x00555555, 1208 0xff600000, 1209 0xfff55555, 1210 0x00155555, 1211 0x00055555, 1212 0xffeaaaab, 1213 0x00200000 1214}; 1215 1216static u32 coef_24to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1217 0x000c6102,//header 1218 0x0001d727,//input gain 1219 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1220 0x00e55557, 0xffcadd5b, 0x003d80ba, 1221 0x00d13397, 0xfff232f8, 0x00683337, 1222 0x00000002,//output gain 1223 0x00186102,//header 1224 0x000013d9,//input gain 1225 0x00ebd477, 0xff4ce383, 0x0042049d, 1226 0x0089c278, 0xff54414d, 0x00531ded, 1227 0x004a5e07, 0xff53cf41, 0x006efbdc, 1228 0x00000002,//output gain 1229 0x00006102,//header 1230 0x0000010a,//input gain 1231 0x00c93dc4, 0xff26f5f6, 0x005d1041, 1232 0x001002c4, 0xff245b76, 0x00666002, 1233 0xffc30a45, 0xff1baecd, 0x00765921, 1234 0x00000002//output gain 1235}; 1236 1237static u32 coef_32to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1238 0x000c5102,//header 1239 0x000013d9,//input gain 1240 0x00ebd477, 0xff4ce383, 0x0042049d, 1241 0x0089c278, 0xff54414d, 0x00531ded, 1242 0x004a5e07, 0xff53cf41, 0x006efbdc, 1243 0x00000001,//output gain 1244 0x00005102,//header 1245 0x0001d727,//input gain 1246 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1247 0x00e55557, 0xffcadd5b, 0x003d80ba, 1248 0x00d13397, 0xfff232f8, 0x00683337, 1249 0x00000001//output gain 1250}; 1251 1252static u32 coef_32to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1253 0x000ca102,//header 1254 0x000000af,//input gain 1255 0x00c65663, 0xff23d2ce, 0x005f97d6, 1256 0x00086ad6, 0xff20ec4f, 0x00683201, 1257 0xffbbbef6, 0xff184447, 0x00770963, 1258 0x00000003,//output gain 1259 0x00175204,//farrow 1260 0x000aaaab, 1261 0xffaaaaab, 1262 0xfffaaaab, 1263 0x00555555, 1264 0xff600000, 1265 0xfff55555, 1266 0x00155555, 1267 0x00055555, 1268 0xffeaaaab, 1269 0x00200000, 1270 0x0000d102,//header 1271 0x000013d9,//input gain 1272 0x00ebd477, 0xff4ce383, 0x0042049d, 1273 0x0089c278, 0xff54414d, 0x00531ded, 1274 0x004a5e07, 0xff53cf41, 0x006efbdc, 1275 0x00000001//output gain 1276}; 1277 1278static u32 coef_32to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1279 0x00005102,//header 1280 0x0001d727,//input gain 1281 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1282 0x00e55557, 0xffcadd5b, 0x003d80ba, 1283 0x00d13397, 0xfff232f8, 0x00683337, 1284 0x00000001//output gain 1285}; 1286 1287static u32 coef_32to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1288 0x000fa103,//header 1289 0x000001e0,//input gain 1290 0x00de44c0, 0xff380b7f, 0x004ffc73, 1291 0x00494b44, 0xff3d493a, 0x005908bf, 1292 0xffe9a3c8, 0xff425647, 0x006745f7, 1293 0xffc42d61, 0xff40a6c7, 0x00776709, 1294 0x00000003,//output gain 1295 0x001a5204,//farrow 1296 0x000aaaab, 1297 0xffaaaaab, 1298 0xfffaaaab, 1299 0x00555555, 1300 0xff600000, 1301 0xfff55555, 1302 0x00155555, 1303 0x00055555, 1304 0xffeaaaab, 1305 0x00200000, 1306 0x00005102,//header 1307 0x0001d727,//input gain 1308 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1309 0x00e55557, 0xffcadd5b, 0x003d80ba, 1310 0x00d13397, 0xfff232f8, 0x00683337, 1311 0x00000001//output gain 1312}; 1313 1314static u32 coef_32to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1315 0x000ca102,//header 1316 0x000013d9,//input gain 1317 0x00ebd477, 0xff4ce383, 0x0042049d, 1318 0x0089c278, 0xff54414d, 0x00531ded, 1319 0x004a5e07, 0xff53cf41, 0x006efbdc, 1320 0x00000003,//output gain 1321 0x0000d102,//header 1322 0x000013d9,//input gain 1323 0x00ebd477, 0xff4ce383, 0x0042049d, 1324 0x0089c278, 0xff54414d, 0x00531ded, 1325 0x004a5e07, 0xff53cf41, 0x006efbdc, 1326 0x00000001//output gain 1327}; 1328 1329static u32 coef_32to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1330 0x000c6102,//header 1331 0x0001d727,//input gain 1332 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1333 0x00e55557, 0xffcadd5b, 0x003d80ba, 1334 0x00d13397, 0xfff232f8, 0x00683337, 1335 0x00000002,//output gain 1336 0x0018a102,//header 1337 0x000005d6,//input gain 1338 0x00c6543e, 0xff342935, 0x0052f116, 1339 0x000a1d78, 0xff3330c0, 0x005f88a3, 1340 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 1341 0x00000003,//output gain 1342 0x00235204,//farrow 1343 0x000aaaab, 1344 0xffaaaaab, 1345 0xfffaaaab, 1346 0x00555555, 1347 0xff600000, 1348 0xfff55555, 1349 0x00155555, 1350 0x00055555, 1351 0xffeaaaab, 1352 0x00200000, 1353 0x00005102,//header 1354 0x0000015f,//input gain 1355 0x00a7909c, 0xff241c71, 0x005f5e00, 1356 0xffca77f4, 0xff20dd50, 0x006855eb, 1357 0xff86c552, 0xff18137a, 0x00773648, 1358 0x00000001//output gain 1359}; 1360 1361static u32 coef_32to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1362 0x0015a105,//header 1363 0x00000292,//input gain 1364 0x00e4320a, 0xff41d2d9, 0x004911ac, 1365 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1366 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1367 0xffc4b414, 0xff68582c, 0x006b38e5, 1368 0xffabb861, 0xff704bec, 0x0074de52, 1369 0xffa19f4c, 0xff729059, 0x007c7e90, 1370 0x00000003,//output gain 1371 0x00005105,//header 1372 0x00000292,//input gain 1373 0x00e4320a, 0xff41d2d9, 0x004911ac, 1374 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1375 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1376 0xffc4b414, 0xff68582c, 0x006b38e5, 1377 0xffabb861, 0xff704bec, 0x0074de52, 1378 0xffa19f4c, 0xff729059, 0x007c7e90, 1379 0x00000001//output gain 1380}; 1381 1382static u32 coef_32to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1383 0x000c6102,//header 1384 0x0001d727,//input gain 1385 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1386 0x00e55557, 0xffcadd5b, 0x003d80ba, 1387 0x00d13397, 0xfff232f8, 0x00683337, 1388 0x00000002,//output gain 1389 0x0018a102,//header 1390 0x000005d6,//input gain 1391 0x00c6543e, 0xff342935, 0x0052f116, 1392 0x000a1d78, 0xff3330c0, 0x005f88a3, 1393 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 1394 0x00000003,//output gain 1395 0x00230204,//farrow 1396 0x000aaaab, 1397 0xffaaaaab, 1398 0xfffaaaab, 1399 0x00555555, 1400 0xff600000, 1401 0xfff55555, 1402 0x00155555, 1403 0x00055555, 1404 0xffeaaaab, 1405 0x00200000, 1406 0x00005102,//header 1407 0x000005f3,//input gain 1408 0x00d816d6, 0xff385383, 0x004fe566, 1409 0x003c548d, 0xff38c23d, 0x005d0b1c, 1410 0xfff02f7d, 0xff31e983, 0x0072d65d, 1411 0x00000001//output gain 1412}; 1413 1414static u32 coef_32to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1415 0x0000a105,//header 1416 0x00000292,//input gain 1417 0x00e4320a, 0xff41d2d9, 0x004911ac, 1418 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1419 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1420 0xffc4b414, 0xff68582c, 0x006b38e5, 1421 0xffabb861, 0xff704bec, 0x0074de52, 1422 0xffa19f4c, 0xff729059, 0x007c7e90, 1423 0x00000003//output gain 1424}; 1425 1426static u32 coef_32to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1427 0x000c6102,//header 1428 0x0001d727,//input gain 1429 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1430 0x00e55557, 0xffcadd5b, 0x003d80ba, 1431 0x00d13397, 0xfff232f8, 0x00683337, 1432 0x00000002,//output gain 1433 0x0018a102,//header 1434 0x000005d6,//input gain 1435 0x00c6543e, 0xff342935, 0x0052f116, 1436 0x000a1d78, 0xff3330c0, 0x005f88a3, 1437 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 1438 0x00000003,//output gain 1439 0x00000204,//farrow 1440 0x000aaaab, 1441 0xffaaaaab, 1442 0xfffaaaab, 1443 0x00555555, 1444 0xff600000, 1445 0xfff55555, 1446 0x00155555, 1447 0x00055555, 1448 0xffeaaaab, 1449 0x00200000 1450}; 1451 1452static u32 coef_32to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1453 0x000c6102,//header 1454 0x0001d727,//input gain 1455 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1456 0x00e55557, 0xffcadd5b, 0x003d80ba, 1457 0x00d13397, 0xfff232f8, 0x00683337, 1458 0x00000002,//output gain 1459 0x0000a102,//header 1460 0x000005d6,//input gain 1461 0x00c6543e, 0xff342935, 0x0052f116, 1462 0x000a1d78, 0xff3330c0, 0x005f88a3, 1463 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 1464 0x00000003//output gain 1465}; 1466 1467static u32 coef_44to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1468 0x00120104,//IIR Filter 1469 0x00000af2,//input gain 1470 0x0057eebe, 0xff1e9863, 0x00652604, 1471 0xff7206ea, 0xff22ad7e, 0x006d47e1, 1472 0xff42a4d7, 0xff26e722, 0x0075fd83, 1473 0xff352f66, 0xff29312b, 0x007b986b, 1474 0xff310a07, 0xff296f51, 0x007eca7c, 1475 0x00000001,//output gain 1476 0x001d9204,//Farrow Filter + decimation 1477 0x000aaaab, 1478 0xffaaaaab, 1479 0xfffaaaab, 1480 0x00555555, 1481 0xff600000, 1482 0xfff55555, 1483 0x00155555, 1484 0x00055555, 1485 0xffeaaaab, 1486 0x00200000, 1487 0x00005105,//IIR Filter + Decimator 1488 0x0000d649,//input gain 1489 0x00e87afb, 0xff5f69d0, 0x003df3cf, 1490 0x007ce488, 0xff99a5c8, 0x0056a6a0, 1491 0x00344928, 0xffcba3e5, 0x006be470, 1492 0x00137aa7, 0xffe60276, 0x00773410, 1493 0x0005fa2a, 0xfff1ac11, 0x007c795b, 1494 0x00012d36, 0xfff5eca2, 0x007f10ef, 1495 0x00000001//output gain 1496}; 1497 1498static u32 coef_44to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1499 0x000c5102,//header 1500 0x000013d9,//input gain 1501 0x00ebd477, 0xff4ce383, 0x0042049d, 1502 0x0089c278, 0xff54414d, 0x00531ded, 1503 0x004a5e07, 0xff53cf41, 0x006efbdc, 1504 0x00000001,//output gain 1505 0x00005102,//header 1506 0x0001d727,//input gain 1507 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1508 0x00e55557, 0xffcadd5b, 0x003d80ba, 1509 0x00d13397, 0xfff232f8, 0x00683337, 1510 0x00000001//output gain 1511}; 1512 1513static u32 coef_44to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1514 0x00126104,//IIR Filter + interpolation 1515 0x00000af2,//input gain 1516 0x0057eebe, 0xff1e9863, 0x00652604, 1517 0xff7206ea, 0xff22ad7e, 0x006d47e1, 1518 0xff42a4d7, 0xff26e722, 0x0075fd83, 1519 0xff352f66, 0xff29312b, 0x007b986b, 1520 0xff310a07, 0xff296f51, 0x007eca7c, 1521 0x00000002,//output gain 1522 0x001d9204,//Farrow Filter + decimation 1523 0x000aaaab, 1524 0xffaaaaab, 1525 0xfffaaaab, 1526 0x00555555, 1527 0xff600000, 1528 0xfff55555, 1529 0x00155555, 1530 0x00055555, 1531 0xffeaaaab, 1532 0x00200000, 1533 0x00005105,//IIR Filter + Decimator 1534 0x0000d649,//input gain 1535 0x00e87afb, 0xff5f69d0, 0x003df3cf, 1536 0x007ce488, 0xff99a5c8, 0x0056a6a0, 1537 0x00344928, 0xffcba3e5, 0x006be470, 1538 0x00137aa7, 0xffe60276, 0x00773410, 1539 0x0005fa2a, 0xfff1ac11, 0x007c795b, 1540 0x00012d36, 0xfff5eca2, 0x007f10ef, 1541 0x00000001//output gain 1542}; 1543 1544static u32 coef_44to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1545 0x00005102,//header 1546 0x0001d727,//input gain 1547 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1548 0x00e55557, 0xffcadd5b, 0x003d80ba, 1549 0x00d13397, 0xfff232f8, 0x00683337, 1550 0x00000001//output gain 1551}; 1552 1553static u32 coef_44to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1554 0x000c6102,//header 1555 0x00001685,//input gain 1556 0x00f53ae9, 0xff52f196, 0x003e3e08, 1557 0x00b9f857, 0xff5d8985, 0x0050070a, 1558 0x008c3e86, 0xff6053f0, 0x006d98ef, 1559 0x00000002,//output gain 1560 0x00175204,//farrow 1561 0x000aaaab, 1562 0xffaaaaab, 1563 0xfffaaaab, 1564 0x00555555, 1565 0xff600000, 1566 0xfff55555, 1567 0x00155555, 1568 0x00055555, 1569 0xffeaaaab, 1570 0x00200000, 1571 0x00005102,//header 1572 0x0001d727,//input gain 1573 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1574 0x00e55557, 0xffcadd5b, 0x003d80ba, 1575 0x00d13397, 0xfff232f8, 0x00683337, 1576 0x00000001//output gain 1577}; 1578 1579static u32 coef_44to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1580 0x000c6102,//header 1581 0x0000015f,//input gain 1582 0x00a7909c, 0xff241c71, 0x005f5e00, 1583 0xffca77f4, 0xff20dd50, 0x006855eb, 1584 0xff86c552, 0xff18137a, 0x00773648, 1585 0x00000002,//output gain 1586 0x00186102,//header 1587 0x000005f3,//input gain 1588 0x00d816d6, 0xff385383, 0x004fe566, 1589 0x003c548d, 0xff38c23d, 0x005d0b1c, 1590 0xfff02f7d, 0xff31e983, 0x0072d65d, 1591 0x00000002,//output gain 1592 0x00239204,//farrow 1593 0x000aaaab, 1594 0xffaaaaab, 1595 0xfffaaaab, 1596 0x00555555, 1597 0xff600000, 1598 0xfff55555, 1599 0x00155555, 1600 0x00055555, 1601 0xffeaaaab, 1602 0x00200000, 1603 0x00005102,//header 1604 0x0001d727,//input gain 1605 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1606 0x00e55557, 0xffcadd5b, 0x003d80ba, 1607 0x00d13397, 0xfff232f8, 0x00683337, 1608 0x00000001//output gain 1609}; 1610 1611static u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1612 0x000c6102,//header 1613 0x0001d727,//input gain 1614 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1615 0x00e55557, 0xffcadd5b, 0x003d80ba, 1616 0x00d13397, 0xfff232f8, 0x00683337, 1617 0x00000002,//output gain 1618 0x00186102,//header 1619 0x000013d9,//input gain 1620 0x00ebd477, 0xff4ce383, 0x0042049d, 1621 0x0089c278, 0xff54414d, 0x00531ded, 1622 0x004a5e07, 0xff53cf41, 0x006efbdc, 1623 0x00000002,//output gain 1624 0x00235204,//farrow 1625 0x000aaaab, 1626 0xffaaaaab, 1627 0xfffaaaab, 1628 0x00555555, 1629 0xff600000, 1630 0xfff55555, 1631 0x00155555, 1632 0x00055555, 1633 0xffeaaaab, 1634 0x00200000, 1635 0x00005102,//header 1636 0x0001d029,//input gain 1637 0x00f2a98b, 0xff92aa71, 0x001fcd16, 1638 0x00ae9004, 0xffb85140, 0x0041813a, 1639 0x007f8ed1, 0xffd585fc, 0x006a69e6, 1640 0x00000001//output gain 1641}; 1642 1643static u32 coef_44to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1644 0x00006102,//header 1645 0x0001d727,//input gain 1646 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1647 0x00e55557, 0xffcadd5b, 0x003d80ba, 1648 0x00d13397, 0xfff232f8, 0x00683337, 1649 0x00000002//output gain 1650}; 1651 1652static u32 coef_44to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1653 0x000c6102,//header 1654 0x0001d727,//input gain 1655 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1656 0x00e55557, 0xffcadd5b, 0x003d80ba, 1657 0x00d13397, 0xfff232f8, 0x00683337, 1658 0x00000002,//output gain 1659 0x00186102,//header 1660 0x000013d9,//input gain 1661 0x00ebd477, 0xff4ce383, 0x0042049d, 1662 0x0089c278, 0xff54414d, 0x00531ded, 1663 0x004a5e07, 0xff53cf41, 0x006efbdc, 1664 0x00000002,//output gain 1665 0x00005204,//farrow 1666 0x000aaaab, 1667 0xffaaaaab, 1668 0xfffaaaab, 1669 0x00555555, 1670 0xff600000, 1671 0xfff55555, 1672 0x00155555, 1673 0x00055555, 1674 0xffeaaaab, 1675 0x00200000 1676}; 1677 1678static u32 coef_44to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1679 0x000c6102,//header 1680 0x0001d727,//input gain 1681 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1682 0x00e55557, 0xffcadd5b, 0x003d80ba, 1683 0x00d13397, 0xfff232f8, 0x00683337, 1684 0x00000002,//output gain 1685 0x00006102,//header 1686 0x000013d9,//input gain 1687 0x00ebd477, 0xff4ce383, 0x0042049d, 1688 0x0089c278, 0xff54414d, 0x00531ded, 1689 0x004a5e07, 0xff53cf41, 0x006efbdc, 1690 0x00000002//output gain 1691}; 1692 1693static u32 coef_44to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1694 0x000c6102,//header 1695 0x0001d727,//input gain 1696 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1697 0x00e55557, 0xffcadd5b, 0x003d80ba, 1698 0x00d13397, 0xfff232f8, 0x00683337, 1699 0x00000002,//output gain 1700 0x00186102,//header 1701 0x000013d9,//input gain 1702 0x00ebd477, 0xff4ce383, 0x0042049d, 1703 0x0089c278, 0xff54414d, 0x00531ded, 1704 0x004a5e07, 0xff53cf41, 0x006efbdc, 1705 0x00000002,//output gain 1706 0x00246102,//header 1707 0x0000010a,//input gain 1708 0x00c93dc4, 0xff26f5f6, 0x005d1041, 1709 0x001002c4, 0xff245b76, 0x00666002, 1710 0xffc30a45, 0xff1baecd, 0x00765921, 1711 0x00000002,//output gain 1712 0x00005204,//farrow 1713 0x000aaaab, 1714 0xffaaaaab, 1715 0xfffaaaab, 1716 0x00555555, 1717 0xff600000, 1718 0xfff55555, 1719 0x00155555, 1720 0x00055555, 1721 0xffeaaaab, 1722 0x00200000 1723}; 1724 1725static u32 coef_48to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1726 0x000c9102,//IIR Filter + Decimator 1727 0x00000e00,//input gain 1728 0x00e2e000, 0xff6e1a00, 0x002aaa00, 1729 0x00610a00, 0xff5dda00, 0x003ccc00, 1730 0x00163a00, 0xff3c0400, 0x00633200, 1731 0x00000001,//output gain 1732 0x00005105,//IIR Filter + Decimator 1733 0x0000d649,//input gain 1734 0x00e87afb, 0xff5f69d0, 0x003df3cf, 1735 0x007ce488, 0xff99a5c8, 0x0056a6a0, 1736 0x00344928, 0xffcba3e5, 0x006be470, 1737 0x00137aa7, 0xffe60276, 0x00773410, 1738 0x0005fa2a, 0xfff1ac11, 0x007c795b, 1739 0x00012d36, 0xfff5eca2, 0x007f10ef, 1740 0x00000001//output gain 1741}; 1742 1743static u32 coef_48to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1744 0x000c6102,//header 1745 0x000000af,//input gain 1746 0x00c65663, 0xff23d2ce, 0x005f97d6, 1747 0x00086ad6, 0xff20ec4f, 0x00683201, 1748 0xffbbbef6, 0xff184447, 0x00770963, 1749 0x00000002,//output gain 1750 0x00175204,//farrow 1751 0x000aaaab, 1752 0xffaaaaab, 1753 0xfffaaaab, 1754 0x00555555, 1755 0xff600000, 1756 0xfff55555, 1757 0x00155555, 1758 0x00055555, 1759 0xffeaaaab, 1760 0x00200000, 1761 0x00235102,//header 1762 0x000013d9,//input gain 1763 0x00ebd477, 0xff4ce383, 0x0042049d, 1764 0x0089c278, 0xff54414d, 0x00531ded, 1765 0x004a5e07, 0xff53cf41, 0x006efbdc, 1766 0x00000001,//output gain 1767 0x00005102,//header 1768 0x0001d727,//input gain 1769 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1770 0x00e55557, 0xffcadd5b, 0x003d80ba, 1771 0x00d13397, 0xfff232f8, 0x00683337, 1772 0x00000001//output gain 1773}; 1774 1775static u32 coef_48to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1776 0x00009105,//IIR Filter + Decimator 1777 0x00000784,//input gain 1778 0x00cc516e, 0xff2c9639, 0x005ad5b3, 1779 0x0013ad0d, 0xff3d4799, 0x0063ce75, 1780 0xffb6f398, 0xff5138d1, 0x006e9e1f, 1781 0xff9186e5, 0xff5f96a4, 0x0076a86e, 1782 0xff82089c, 0xff676b81, 0x007b9f8a, 1783 0xff7c48a5, 0xff6a31e7, 0x007ebb7b, 1784 0x00000001//output gain 1785}; 1786 1787static u32 coef_48to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1788 0x000f6103,//header 1789 0x000001e0,//input gain 1790 0x00de44c0, 0xff380b7f, 0x004ffc73, 1791 0x00494b44, 0xff3d493a, 0x005908bf, 1792 0xffe9a3c8, 0xff425647, 0x006745f7, 1793 0xffc42d61, 0xff40a6c7, 0x00776709, 1794 0x00000002,//output gain 1795 0x001a5204,//farrow 1796 0x000aaaab, 1797 0xffaaaaab, 1798 0xfffaaaab, 1799 0x00555555, 1800 0xff600000, 1801 0xfff55555, 1802 0x00155555, 1803 0x00055555, 1804 0xffeaaaab, 1805 0x00200000, 1806 0x00005102,//header 1807 0x0001d727,//input gain 1808 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1809 0x00e55557, 0xffcadd5b, 0x003d80ba, 1810 0x00d13397, 0xfff232f8, 0x00683337, 1811 0x00000001//output gain 1812}; 1813 1814static u32 coef_48to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1815 0x00005102,//header 1816 0x0001d727,//input gain 1817 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1818 0x00e55557, 0xffcadd5b, 0x003d80ba, 1819 0x00d13397, 0xfff232f8, 0x00683337, 1820 0x00000001//output gain 1821}; 1822 1823static u32 coef_48to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1824 0x00156105,//header 1825 0x00000292,//input gain 1826 0x00e4320a, 0xff41d2d9, 0x004911ac, 1827 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1828 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1829 0xffc4b414, 0xff68582c, 0x006b38e5, 1830 0xffabb861, 0xff704bec, 0x0074de52, 1831 0xffa19f4c, 0xff729059, 0x007c7e90, 1832 0x00000002,//output gain 1833 0x00009105,//header 1834 0x00000292,//input gain 1835 0x00e4320a, 0xff41d2d9, 0x004911ac, 1836 0x005dd9e3, 0xff4c7d80, 0x0052103e, 1837 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 1838 0xffc4b414, 0xff68582c, 0x006b38e5, 1839 0xffabb861, 0xff704bec, 0x0074de52, 1840 0xffa19f4c, 0xff729059, 0x007c7e90, 1841 0x00000001//output gain 1842}; 1843 1844static u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1845 0x000c6102,//header 1846 0x0001d029,//input gain 1847 0x00f2a98b, 0xff92aa71, 0x001fcd16, 1848 0x00ae9004, 0xffb85140, 0x0041813a, 1849 0x007f8ed1, 0xffd585fc, 0x006a69e6, 1850 0x00000002,//output gain 1851 0x001b6103,//header 1852 0x000001e0,//input gain 1853 0x00de44c0, 0xff380b7f, 0x004ffc73, 1854 0x00494b44, 0xff3d493a, 0x005908bf, 1855 0xffe9a3c8, 0xff425647, 0x006745f7, 1856 0xffc42d61, 0xff40a6c7, 0x00776709, 1857 0x00000002,//output gain 1858 0x00265204,//farrow 1859 0x000aaaab, 1860 0xffaaaaab, 1861 0xfffaaaab, 1862 0x00555555, 1863 0xff600000, 1864 0xfff55555, 1865 0x00155555, 1866 0x00055555, 1867 0xffeaaaab, 1868 0x00200000, 1869 0x00005102,//header 1870 0x0001d727,//input gain 1871 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1872 0x00e55557, 0xffcadd5b, 0x003d80ba, 1873 0x00d13397, 0xfff232f8, 0x00683337, 1874 0x00000001//output gain 1875}; 1876 1877static u32 coef_48to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1878 0x000c6102,//header 1879 0x0001d727,//input gain 1880 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1881 0x00e55557, 0xffcadd5b, 0x003d80ba, 1882 0x00d13397, 0xfff232f8, 0x00683337, 1883 0x00000002,//output gain 1884 0x00186102,//header 1885 0x000013d9,//input gain 1886 0x00ebd477, 0xff4ce383, 0x0042049d, 1887 0x0089c278, 0xff54414d, 0x00531ded, 1888 0x004a5e07, 0xff53cf41, 0x006efbdc, 1889 0x00000002,//output gain 1890 0x00230204,//farrow 1891 0x000aaaab, 1892 0xffaaaaab, 1893 0xfffaaaab, 1894 0x00555555, 1895 0xff600000, 1896 0xfff55555, 1897 0x00155555, 1898 0x00055555, 1899 0xffeaaaab, 1900 0x00200000, 1901 0x00005102,//header 1902 0x00001685,//input gain 1903 0x00f53ae9, 0xff52f196, 0x003e3e08, 1904 0x00b9f857, 0xff5d8985, 0x0050070a, 1905 0x008c3e86, 0xff6053f0, 0x006d98ef, 1906 0x00000001//output gain 1907}; 1908 1909static u32 coef_48to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1910 0x00006102,//header 1911 0x0001d727,//input gain 1912 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1913 0x00e55557, 0xffcadd5b, 0x003d80ba, 1914 0x00d13397, 0xfff232f8, 0x00683337, 1915 0x00000002//output gain 1916}; 1917 1918static u32 coef_48to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1919 0x000c6102,//header 1920 0x0001d727,//input gain 1921 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1922 0x00e55557, 0xffcadd5b, 0x003d80ba, 1923 0x00d13397, 0xfff232f8, 0x00683337, 1924 0x00000002,//output gain 1925 0x00186102,//header 1926 0x000013d9,//input gain 1927 0x00ebd477, 0xff4ce383, 0x0042049d, 1928 0x0089c278, 0xff54414d, 0x00531ded, 1929 0x004a5e07, 0xff53cf41, 0x006efbdc, 1930 0x00000002,//output gain 1931 0x00246102,//header 1932 0x0000010a,//input gain 1933 0x00c93dc4, 0xff26f5f6, 0x005d1041, 1934 0x001002c4, 0xff245b76, 0x00666002, 1935 0xffc30a45, 0xff1baecd, 0x00765921, 1936 0x00000002,//output gain 1937 0x002f0204,//farrow 1938 0x000aaaab, 1939 0xffaaaaab, 1940 0xfffaaaab, 1941 0x00555555, 1942 0xff600000, 1943 0xfff55555, 1944 0x00155555, 1945 0x00055555, 1946 0xffeaaaab, 1947 0x00200000, 1948 0x00005102,//header 1949 0x00000138,//input gain 1950 0x00d5d232, 0xff2a3bf8, 0x005a785c, 1951 0x0034001b, 0xff283109, 0x006462a6, 1952 0xffe6746a, 0xff1fb09c, 0x00758a91, 1953 0x00000001//output gain 1954}; 1955 1956static u32 coef_48to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1957 0x000c6102,//header 1958 0x0001d727,//input gain 1959 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1960 0x00e55557, 0xffcadd5b, 0x003d80ba, 1961 0x00d13397, 0xfff232f8, 0x00683337, 1962 0x00000002,//output gain 1963 0x00006102,//header 1964 0x000013d9,//input gain 1965 0x00ebd477, 0xff4ce383, 0x0042049d, 1966 0x0089c278, 0xff54414d, 0x00531ded, 1967 0x004a5e07, 0xff53cf41, 0x006efbdc, 1968 0x00000002//output gain 1969}; 1970 1971static u32 coef_88to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 1972 0x000c0102,//header 1973 0x00000057,//input gain 1974 0x00a8e717, 0xff1c748d, 0x0065b976, 1975 0xffcbccab, 0xff190aff, 0x006cc1cf, 1976 0xff871ce1, 0xff10d878, 0x0078cfc5, 1977 0x00000001,//output gain 1978 0x00179204,//farrow 1979 0x000aaaab, 1980 0xffaaaaab, 1981 0xfffaaaab, 1982 0x00555555, 1983 0xff600000, 1984 0xfff55555, 1985 0x00155555, 1986 0x00055555, 1987 0xffeaaaab, 1988 0x00200000, 1989 0x00235102,//header 1990 0x000013d9,//input gain 1991 0x00ebd477, 0xff4ce383, 0x0042049d, 1992 0x0089c278, 0xff54414d, 0x00531ded, 1993 0x004a5e07, 0xff53cf41, 0x006efbdc, 1994 0x00000001,//output gain 1995 0x00005102,//header 1996 0x0001d727,//input gain 1997 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 1998 0x00e55557, 0xffcadd5b, 0x003d80ba, 1999 0x00d13397, 0xfff232f8, 0x00683337, 2000 0x00000001//output gain 2001}; 2002 2003static u32 coef_88to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2004 0x000c5102,//header 2005 0x0000010a,//input gain 2006 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2007 0x001002c4, 0xff245b76, 0x00666002, 2008 0xffc30a45, 0xff1baecd, 0x00765921, 2009 0x00000001,//output gain 2010 0x00185102,//header 2011 0x000013d9,//input gain 2012 0x00ebd477, 0xff4ce383, 0x0042049d, 2013 0x0089c278, 0xff54414d, 0x00531ded, 2014 0x004a5e07, 0xff53cf41, 0x006efbdc, 2015 0x00000001,//output gain 2016 0x00005102,//header 2017 0x0001d727,//input gain 2018 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2019 0x00e55557, 0xffcadd5b, 0x003d80ba, 2020 0x00d13397, 0xfff232f8, 0x00683337, 2021 0x00000001//output gain 2022}; 2023 2024static u32 coef_88to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2025 0x000c0102,//header 2026 0x000005f3,//input gain 2027 0x00d816d6, 0xff385383, 0x004fe566, 2028 0x003c548d, 0xff38c23d, 0x005d0b1c, 2029 0xfff02f7d, 0xff31e983, 0x0072d65d, 2030 0x00000001,//output gain 2031 0x00179204,//farrow 2032 0x000aaaab, 2033 0xffaaaaab, 2034 0xfffaaaab, 2035 0x00555555, 2036 0xff600000, 2037 0xfff55555, 2038 0x00155555, 2039 0x00055555, 2040 0xffeaaaab, 2041 0x00200000, 2042 0x00005102,//header 2043 0x0001d727,//input gain 2044 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2045 0x00e55557, 0xffcadd5b, 0x003d80ba, 2046 0x00d13397, 0xfff232f8, 0x00683337, 2047 0x00000001//output gain 2048}; 2049 2050static u32 coef_88to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2051 0x000c5102,//header 2052 0x000013d9,//input gain 2053 0x00ebd477, 0xff4ce383, 0x0042049d, 2054 0x0089c278, 0xff54414d, 0x00531ded, 2055 0x004a5e07, 0xff53cf41, 0x006efbdc, 2056 0x00000001,//output gain 2057 0x00005102,//header 2058 0x0001d727,//input gain 2059 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2060 0x00e55557, 0xffcadd5b, 0x003d80ba, 2061 0x00d13397, 0xfff232f8, 0x00683337, 2062 0x00000001//output gain 2063}; 2064 2065static u32 coef_88to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2066 0x000c0102,//header 2067 0x00001685,//input gain 2068 0x00f53ae9, 0xff52f196, 0x003e3e08, 2069 0x00b9f857, 0xff5d8985, 0x0050070a, 2070 0x008c3e86, 0xff6053f0, 0x006d98ef, 2071 0x00000001,//output gain 2072 0x00175204,//farrow 2073 0x000aaaab, 2074 0xffaaaaab, 2075 0xfffaaaab, 2076 0x00555555, 2077 0xff600000, 2078 0xfff55555, 2079 0x00155555, 2080 0x00055555, 2081 0xffeaaaab, 2082 0x00200000, 2083 0x00005102,//header 2084 0x0001d727,//input gain 2085 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2086 0x00e55557, 0xffcadd5b, 0x003d80ba, 2087 0x00d13397, 0xfff232f8, 0x00683337, 2088 0x00000001//output gain 2089}; 2090 2091static u32 coef_88to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2092 0x000c6102,//header 2093 0x000005f3,//input gain 2094 0x00d816d6, 0xff385383, 0x004fe566, 2095 0x003c548d, 0xff38c23d, 0x005d0b1c, 2096 0xfff02f7d, 0xff31e983, 0x0072d65d, 2097 0x00000002,//output gain 2098 0x00179204,//farrow 2099 0x000aaaab, 2100 0xffaaaaab, 2101 0xfffaaaab, 2102 0x00555555, 2103 0xff600000, 2104 0xfff55555, 2105 0x00155555, 2106 0x00055555, 2107 0xffeaaaab, 2108 0x00200000, 2109 0x00005102,//header 2110 0x0001d727,//input gain 2111 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2112 0x00e55557, 0xffcadd5b, 0x003d80ba, 2113 0x00d13397, 0xfff232f8, 0x00683337, 2114 0x00000001//output gain 2115}; 2116 2117static u32 coef_88to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2118 0x00005102,//header 2119 0x0001d727,//input gain 2120 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2121 0x00e55557, 0xffcadd5b, 0x003d80ba, 2122 0x00d13397, 0xfff232f8, 0x00683337, 2123 0x00000001//output gain 2124}; 2125 2126static u32 coef_88to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2127 0x000c6102,//header 2128 0x00001685,//input gain 2129 0x00f53ae9, 0xff52f196, 0x003e3e08, 2130 0x00b9f857, 0xff5d8985, 0x0050070a, 2131 0x008c3e86, 0xff6053f0, 0x006d98ef, 2132 0x00000002,//output gain 2133 0x00175204,//farrow 2134 0x000aaaab, 2135 0xffaaaaab, 2136 0xfffaaaab, 2137 0x00555555, 2138 0xff600000, 2139 0xfff55555, 2140 0x00155555, 2141 0x00055555, 2142 0xffeaaaab, 2143 0x00200000, 2144 0x00005102,//header 2145 0x0001d727,//input gain 2146 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2147 0x00e55557, 0xffcadd5b, 0x003d80ba, 2148 0x00d13397, 0xfff232f8, 0x00683337, 2149 0x00000001//output gain 2150}; 2151 2152static u32 coef_88to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2153 0x000c6102,//header 2154 0x000013d9,//input gain 2155 0x00ebd477, 0xff4ce383, 0x0042049d, 2156 0x0089c278, 0xff54414d, 0x00531ded, 2157 0x004a5e07, 0xff53cf41, 0x006efbdc, 2158 0x00000002,//output gain 2159 0x00005204,//farrow 2160 0x000aaaab, 2161 0xffaaaaab, 2162 0xfffaaaab, 2163 0x00555555, 2164 0xff600000, 2165 0xfff55555, 2166 0x00155555, 2167 0x00055555, 2168 0xffeaaaab, 2169 0x00200000 2170}; 2171 2172static u32 coef_88to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2173 0x00006102,//header 2174 0x000013d9,//input gain 2175 0x00ebd477, 0xff4ce383, 0x0042049d, 2176 0x0089c278, 0xff54414d, 0x00531ded, 2177 0x004a5e07, 0xff53cf41, 0x006efbdc, 2178 0x00000002//output gain 2179}; 2180 2181static u32 coef_88to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2182 0x000c6102,//header 2183 0x000013d9,//input gain 2184 0x00ebd477, 0xff4ce383, 0x0042049d, 2185 0x0089c278, 0xff54414d, 0x00531ded, 2186 0x004a5e07, 0xff53cf41, 0x006efbdc, 2187 0x00000002,//output gain 2188 0x00186102,//header 2189 0x0000010a,//input gain 2190 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2191 0x001002c4, 0xff245b76, 0x00666002, 2192 0xffc30a45, 0xff1baecd, 0x00765921, 2193 0x00000002,//output gain 2194 0x00005204,//farrow 2195 0x000aaaab, 2196 0xffaaaaab, 2197 0xfffaaaab, 2198 0x00555555, 2199 0xff600000, 2200 0xfff55555, 2201 0x00155555, 2202 0x00055555, 2203 0xffeaaaab, 2204 0x00200000 2205}; 2206 2207static u32 coef_96to8[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2208 0x000c9102,//header 2209 0x0000007d,//input gain 2210 0x007d1f20, 0xff1a540e, 0x00678bf9, 2211 0xff916625, 0xff16b0ff, 0x006e433a, 2212 0xff5af660, 0xff0eb91f, 0x00797356, 2213 0x00000001,//output gain 2214 0x00185102,//header 2215 0x000013d9,//input gain 2216 0x00ebd477, 0xff4ce383, 0x0042049d, 2217 0x0089c278, 0xff54414d, 0x00531ded, 2218 0x004a5e07, 0xff53cf41, 0x006efbdc, 2219 0x00000001,//output gain 2220 0x00005102,//header 2221 0x0001d727,//input gain 2222 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2223 0x00e55557, 0xffcadd5b, 0x003d80ba, 2224 0x00d13397, 0xfff232f8, 0x00683337, 2225 0x00000001//output gain 2226}; 2227 2228static u32 coef_96to11[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2229 0x000c0102,//header 2230 0x000000af,//input gain 2231 0x00c65663, 0xff23d2ce, 0x005f97d6, 2232 0x00086ad6, 0xff20ec4f, 0x00683201, 2233 0xffbbbef6, 0xff184447, 0x00770963, 2234 0x00000001,//output gain 2235 0x00175204,//farrow 2236 0x000aaaab, 2237 0xffaaaaab, 2238 0xfffaaaab, 2239 0x00555555, 2240 0xff600000, 2241 0xfff55555, 2242 0x00155555, 2243 0x00055555, 2244 0xffeaaaab, 2245 0x00200000, 2246 0x00235102,//header 2247 0x000013d9,//input gain 2248 0x00ebd477, 0xff4ce383, 0x0042049d, 2249 0x0089c278, 0xff54414d, 0x00531ded, 2250 0x004a5e07, 0xff53cf41, 0x006efbdc, 2251 0x00000001,//output gain 2252 0x00005102,//header 2253 0x0001d727,//input gain 2254 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2255 0x00e55557, 0xffcadd5b, 0x003d80ba, 2256 0x00d13397, 0xfff232f8, 0x00683337, 2257 0x00000001//output gain 2258}; 2259 2260static u32 coef_96to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2261 0x000c9102,//header 2262 0x000005d6,//input gain 2263 0x00c6543e, 0xff342935, 0x0052f116, 2264 0x000a1d78, 0xff3330c0, 0x005f88a3, 2265 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 2266 0x00000001,//output gain 2267 0x00005102,//header 2268 0x0001d727,//input gain 2269 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2270 0x00e55557, 0xffcadd5b, 0x003d80ba, 2271 0x00d13397, 0xfff232f8, 0x00683337, 2272 0x00000001//output gain 2273}; 2274 2275static u32 coef_96to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2276 0x000c6102,//header 2277 0x000000af,//input gain 2278 0x00c65663, 0xff23d2ce, 0x005f97d6, 2279 0x00086ad6, 0xff20ec4f, 0x00683201, 2280 0xffbbbef6, 0xff184447, 0x00770963, 2281 0x00000002,//output gain 2282 0x00175204,//farrow 2283 0x000aaaab, 2284 0xffaaaaab, 2285 0xfffaaaab, 2286 0x00555555, 2287 0xff600000, 2288 0xfff55555, 2289 0x00155555, 2290 0x00055555, 2291 0xffeaaaab, 2292 0x00200000, 2293 0x00235102,//header 2294 0x000013d9,//input gain 2295 0x00ebd477, 0xff4ce383, 0x0042049d, 2296 0x0089c278, 0xff54414d, 0x00531ded, 2297 0x004a5e07, 0xff53cf41, 0x006efbdc, 2298 0x00000001,//output gain 2299 0x00005102,//header 2300 0x0001d727,//input gain 2301 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2302 0x00e55557, 0xffcadd5b, 0x003d80ba, 2303 0x00d13397, 0xfff232f8, 0x00683337, 2304 0x00000001//output gain 2305}; 2306 2307static u32 coef_96to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2308 0x000c5102,//header 2309 0x000013d9,//input gain 2310 0x00ebd477, 0xff4ce383, 0x0042049d, 2311 0x0089c278, 0xff54414d, 0x00531ded, 2312 0x004a5e07, 0xff53cf41, 0x006efbdc, 2313 0x00000001,//output gain 2314 0x00005102,//header 2315 0x0001d727,//input gain 2316 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2317 0x00e55557, 0xffcadd5b, 0x003d80ba, 2318 0x00d13397, 0xfff232f8, 0x00683337, 2319 0x00000001//output gain 2320}; 2321 2322static u32 coef_96to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2323 0x00009105,//header 2324 0x00000292,//input gain 2325 0x00e4320a, 0xff41d2d9, 0x004911ac, 2326 0x005dd9e3, 0xff4c7d80, 0x0052103e, 2327 0xfff8ebef, 0xff5b6fab, 0x005f0a0d, 2328 0xffc4b414, 0xff68582c, 0x006b38e5, 2329 0xffabb861, 0xff704bec, 0x0074de52, 2330 0xffa19f4c, 0xff729059, 0x007c7e90, 2331 0x00000001//output gain 2332}; 2333 2334static u32 coef_96to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2335 0x000f6103,//header 2336 0x000001e0,//input gain 2337 0x00de44c0, 0xff380b7f, 0x004ffc73, 2338 0x00494b44, 0xff3d493a, 0x005908bf, 2339 0xffe9a3c8, 0xff425647, 0x006745f7, 2340 0xffc42d61, 0xff40a6c7, 0x00776709, 2341 0x00000002,//output gain 2342 0x001a5204,//farrow 2343 0x000aaaab, 2344 0xffaaaaab, 2345 0xfffaaaab, 2346 0x00555555, 2347 0xff600000, 2348 0xfff55555, 2349 0x00155555, 2350 0x00055555, 2351 0xffeaaaab, 2352 0x00200000, 2353 0x00005102,//header 2354 0x0001d727,//input gain 2355 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2356 0x00e55557, 0xffcadd5b, 0x003d80ba, 2357 0x00d13397, 0xfff232f8, 0x00683337, 2358 0x00000001//output gain 2359}; 2360 2361static u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2362 0x00005102,//header 2363 0x0001d727,//input gain 2364 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2365 0x00e55557, 0xffcadd5b, 0x003d80ba, 2366 0x00d13397, 0xfff232f8, 0x00683337, 2367 0x00000001//output gain 2368}; 2369 2370static u32 coef_96to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2371 0x000f6103,//header 2372 0x000001e0,//input gain 2373 0x00de44c0, 0xff380b7f, 0x004ffc73, 2374 0x00494b44, 0xff3d493a, 0x005908bf, 2375 0xffe9a3c8, 0xff425647, 0x006745f7, 2376 0xffc42d61, 0xff40a6c7, 0x00776709, 2377 0x00000002,//output gain 2378 0x001a0204,//farrow 2379 0x000aaaab, 2380 0xffaaaaab, 2381 0xfffaaaab, 2382 0x00555555, 2383 0xff600000, 2384 0xfff55555, 2385 0x00155555, 2386 0x00055555, 2387 0xffeaaaab, 2388 0x00200000, 2389 0x00005102,//header 2390 0x000013d9,//input gain 2391 0x00ebd477, 0xff4ce383, 0x0042049d, 2392 0x0089c278, 0xff54414d, 0x00531ded, 2393 0x004a5e07, 0xff53cf41, 0x006efbdc, 2394 0x00000001//output gain 2395}; 2396 2397static u32 coef_96to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2398 0x000f6103,//header 2399 0x000001e0,//input gain 2400 0x00de44c0, 0xff380b7f, 0x004ffc73, 2401 0x00494b44, 0xff3d493a, 0x005908bf, 2402 0xffe9a3c8, 0xff425647, 0x006745f7, 2403 0xffc42d61, 0xff40a6c7, 0x00776709, 2404 0x00000002,//output gain 2405 0x001b6102,//header 2406 0x000000af,//input gain 2407 0x00c65663, 0xff23d2ce, 0x005f97d6, 2408 0x00086ad6, 0xff20ec4f, 0x00683201, 2409 0xffbbbef6, 0xff184447, 0x00770963, 2410 0x00000002,//output gain 2411 0x00260204,//farrow 2412 0x000aaaab, 2413 0xffaaaaab, 2414 0xfffaaaab, 2415 0x00555555, 2416 0xff600000, 2417 0xfff55555, 2418 0x00155555, 2419 0x00055555, 2420 0xffeaaaab, 2421 0x00200000, 2422 0x00005102,//header 2423 0x0000010a,//input gain 2424 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2425 0x001002c4, 0xff245b76, 0x00666002, 2426 0xffc30a45, 0xff1baecd, 0x00765921, 2427 0x00000001//output gain 2428}; 2429 2430static u32 coef_96to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2431 0x00006103,//header 2432 0x000001e0,//input gain 2433 0x00de44c0, 0xff380b7f, 0x004ffc73, 2434 0x00494b44, 0xff3d493a, 0x005908bf, 2435 0xffe9a3c8, 0xff425647, 0x006745f7, 2436 0xffc42d61, 0xff40a6c7, 0x00776709, 2437 0x00000002//output gain 2438}; 2439 2440static u32 coef_176to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2441 0x000c0102,//header 2442 0x00000057,//input gain 2443 0x00a8e717, 0xff1c748d, 0x0065b976, 2444 0xffcbccab, 0xff190aff, 0x006cc1cf, 2445 0xff871ce1, 0xff10d878, 0x0078cfc5, 2446 0x00000001,//output gain 2447 0x00179204,//farrow 2448 0x000aaaab, 2449 0xffaaaaab, 2450 0xfffaaaab, 2451 0x00555555, 2452 0xff600000, 2453 0xfff55555, 2454 0x00155555, 2455 0x00055555, 2456 0xffeaaaab, 2457 0x00200000, 2458 0x00235102,//header 2459 0x000013d9,//input gain 2460 0x00ebd477, 0xff4ce383, 0x0042049d, 2461 0x0089c278, 0xff54414d, 0x00531ded, 2462 0x004a5e07, 0xff53cf41, 0x006efbdc, 2463 0x00000001,//output gain 2464 0x00005102,//header 2465 0x0001d727,//input gain 2466 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2467 0x00e55557, 0xffcadd5b, 0x003d80ba, 2468 0x00d13397, 0xfff232f8, 0x00683337, 2469 0x00000001//output gain 2470}; 2471 2472static u32 coef_176to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2473 0x000c5102,//header 2474 0x0000010a,//input gain 2475 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2476 0x001002c4, 0xff245b76, 0x00666002, 2477 0xffc30a45, 0xff1baecd, 0x00765921, 2478 0x00000001,//output gain 2479 0x00185102,//header 2480 0x000013d9,//input gain 2481 0x00ebd477, 0xff4ce383, 0x0042049d, 2482 0x0089c278, 0xff54414d, 0x00531ded, 2483 0x004a5e07, 0xff53cf41, 0x006efbdc, 2484 0x00000001,//output gain 2485 0x00005102,//header 2486 0x0001d727,//input gain 2487 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2488 0x00e55557, 0xffcadd5b, 0x003d80ba, 2489 0x00d13397, 0xfff232f8, 0x00683337, 2490 0x00000001//output gain 2491}; 2492 2493static u32 coef_176to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2494 0x000c0102,//header 2495 0x00000138,//input gain 2496 0x00d5d232, 0xff2a3bf8, 0x005a785c, 2497 0x0034001b, 0xff283109, 0x006462a6, 2498 0xffe6746a, 0xff1fb09c, 0x00758a91, 2499 0x00000001,//output gain 2500 0x00175204,//farrow 2501 0x000aaaab, 2502 0xffaaaaab, 2503 0xfffaaaab, 2504 0x00555555, 2505 0xff600000, 2506 0xfff55555, 2507 0x00155555, 2508 0x00055555, 2509 0xffeaaaab, 2510 0x00200000, 2511 0x00235102,//header 2512 0x000013d9,//input gain 2513 0x00ebd477, 0xff4ce383, 0x0042049d, 2514 0x0089c278, 0xff54414d, 0x00531ded, 2515 0x004a5e07, 0xff53cf41, 0x006efbdc, 2516 0x00000001,//output gain 2517 0x00005102,//header 2518 0x0001d727,//input gain 2519 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2520 0x00e55557, 0xffcadd5b, 0x003d80ba, 2521 0x00d13397, 0xfff232f8, 0x00683337, 2522 0x00000001//output gain 2523}; 2524 2525static u32 coef_176to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2526 0x000c0102,//header 2527 0x000005f3,//input gain 2528 0x00d816d6, 0xff385383, 0x004fe566, 2529 0x003c548d, 0xff38c23d, 0x005d0b1c, 2530 0xfff02f7d, 0xff31e983, 0x0072d65d, 2531 0x00000001,//output gain 2532 0x00179204,//farrow 2533 0x000aaaab, 2534 0xffaaaaab, 2535 0xfffaaaab, 2536 0x00555555, 2537 0xff600000, 2538 0xfff55555, 2539 0x00155555, 2540 0x00055555, 2541 0xffeaaaab, 2542 0x00200000, 2543 0x00005102,//header 2544 0x0001d727,//input gain 2545 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2546 0x00e55557, 0xffcadd5b, 0x003d80ba, 2547 0x00d13397, 0xfff232f8, 0x00683337, 2548 0x00000001//output gain 2549}; 2550 2551static u32 coef_176to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2552 0x000c5102,//header 2553 0x000013d9,//input gain 2554 0x00ebd477, 0xff4ce383, 0x0042049d, 2555 0x0089c278, 0xff54414d, 0x00531ded, 2556 0x004a5e07, 0xff53cf41, 0x006efbdc, 2557 0x00000001,//output gain 2558 0x00005102,//header 2559 0x0001d727,//input gain 2560 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2561 0x00e55557, 0xffcadd5b, 0x003d80ba, 2562 0x00d13397, 0xfff232f8, 0x00683337, 2563 0x00000001//output gain 2564}; 2565 2566static u32 coef_176to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2567 0x000c0102,//header 2568 0x00001685,//input gain 2569 0x00f53ae9, 0xff52f196, 0x003e3e08, 2570 0x00b9f857, 0xff5d8985, 0x0050070a, 2571 0x008c3e86, 0xff6053f0, 0x006d98ef, 2572 0x00000001,//output gain 2573 0x00175204,//farrow 2574 0x000aaaab, 2575 0xffaaaaab, 2576 0xfffaaaab, 2577 0x00555555, 2578 0xff600000, 2579 0xfff55555, 2580 0x00155555, 2581 0x00055555, 2582 0xffeaaaab, 2583 0x00200000, 2584 0x00005102,//header 2585 0x0001d727,//input gain 2586 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2587 0x00e55557, 0xffcadd5b, 0x003d80ba, 2588 0x00d13397, 0xfff232f8, 0x00683337, 2589 0x00000001//output gain 2590}; 2591 2592static u32 coef_176to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2593 0x00005102,//header 2594 0x000013d9,//input gain 2595 0x00ebd477, 0xff4ce383, 0x0042049d, 2596 0x0089c278, 0xff54414d, 0x00531ded, 2597 0x004a5e07, 0xff53cf41, 0x006efbdc, 2598 0x00000001//output gain 2599}; 2600 2601static u32 coef_176to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2602 0x000c6102,//header 2603 0x0000010a,//input gain 2604 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2605 0x001002c4, 0xff245b76, 0x00666002, 2606 0xffc30a45, 0xff1baecd, 0x00765921, 2607 0x00000002,//output gain 2608 0x00175204,//farrow 2609 0x000aaaab, 2610 0xffaaaaab, 2611 0xfffaaaab, 2612 0x00555555, 2613 0xff600000, 2614 0xfff55555, 2615 0x00155555, 2616 0x00055555, 2617 0xffeaaaab, 2618 0x00200000, 2619 0x00005103,//header 2620 0x000001e0,//input gain 2621 0x00de44c0, 0xff380b7f, 0x004ffc73, 2622 0x00494b44, 0xff3d493a, 0x005908bf, 2623 0xffe9a3c8, 0xff425647, 0x006745f7, 2624 0xffc42d61, 0xff40a6c7, 0x00776709, 2625 0x00000001//output gain 2626}; 2627 2628static u32 coef_176to192[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2629 0x000c6102,//header 2630 0x0000010a,//input gain 2631 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2632 0x001002c4, 0xff245b76, 0x00666002, 2633 0xffc30a45, 0xff1baecd, 0x00765921, 2634 0x00000002,//output gain 2635 0x00005204,//farrow 2636 0x000aaaab, 2637 0xffaaaaab, 2638 0xfffaaaab, 2639 0x00555555, 2640 0xff600000, 2641 0xfff55555, 2642 0x00155555, 2643 0x00055555, 2644 0xffeaaaab, 2645 0x00200000 2646}; 2647 2648static u32 coef_192to16[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2649 0x000c9102,//header 2650 0x0000007d,//input gain 2651 0x007d1f20, 0xff1a540e, 0x00678bf9, 2652 0xff916625, 0xff16b0ff, 0x006e433a, 2653 0xff5af660, 0xff0eb91f, 0x00797356, 2654 0x00000001,//output gain 2655 0x00185102,//header 2656 0x000013d9,//input gain 2657 0x00ebd477, 0xff4ce383, 0x0042049d, 2658 0x0089c278, 0xff54414d, 0x00531ded, 2659 0x004a5e07, 0xff53cf41, 0x006efbdc, 2660 0x00000001,//output gain 2661 0x00005102,//header 2662 0x0001d727,//input gain 2663 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2664 0x00e55557, 0xffcadd5b, 0x003d80ba, 2665 0x00d13397, 0xfff232f8, 0x00683337, 2666 0x00000001//output gain 2667}; 2668 2669static u32 coef_192to22[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2670 0x000c0102,//header 2671 0x000000af,//input gain 2672 0x00c65663, 0xff23d2ce, 0x005f97d6, 2673 0x00086ad6, 0xff20ec4f, 0x00683201, 2674 0xffbbbef6, 0xff184447, 0x00770963, 2675 0x00000001,//output gain 2676 0x00175204,//farrow 2677 0x000aaaab, 2678 0xffaaaaab, 2679 0xfffaaaab, 2680 0x00555555, 2681 0xff600000, 2682 0xfff55555, 2683 0x00155555, 2684 0x00055555, 2685 0xffeaaaab, 2686 0x00200000, 2687 0x00235102,//header 2688 0x000013d9,//input gain 2689 0x00ebd477, 0xff4ce383, 0x0042049d, 2690 0x0089c278, 0xff54414d, 0x00531ded, 2691 0x004a5e07, 0xff53cf41, 0x006efbdc, 2692 0x00000001,//output gain 2693 0x00005102,//header 2694 0x0001d727,//input gain 2695 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2696 0x00e55557, 0xffcadd5b, 0x003d80ba, 2697 0x00d13397, 0xfff232f8, 0x00683337, 2698 0x00000001//output gain 2699}; 2700 2701static u32 coef_192to24[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2702 0x000c5102,//header 2703 0x0000010a,//input gain 2704 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2705 0x001002c4, 0xff245b76, 0x00666002, 2706 0xffc30a45, 0xff1baecd, 0x00765921, 2707 0x00000001,//output gain 2708 0x00185102,//header 2709 0x000013d9,//input gain 2710 0x00ebd477, 0xff4ce383, 0x0042049d, 2711 0x0089c278, 0xff54414d, 0x00531ded, 2712 0x004a5e07, 0xff53cf41, 0x006efbdc, 2713 0x00000001,//output gain 2714 0x00005102,//header 2715 0x0001d727,//input gain 2716 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2717 0x00e55557, 0xffcadd5b, 0x003d80ba, 2718 0x00d13397, 0xfff232f8, 0x00683337, 2719 0x00000001//output gain 2720}; 2721 2722static u32 coef_192to32[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2723 0x000c9102,//header 2724 0x000005d6,//input gain 2725 0x00c6543e, 0xff342935, 0x0052f116, 2726 0x000a1d78, 0xff3330c0, 0x005f88a3, 2727 0xffbee7c0, 0xff2b5ba5, 0x0073eb26, 2728 0x00000001,//output gain 2729 0x00005102,//header 2730 0x0001d727,//input gain 2731 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2732 0x00e55557, 0xffcadd5b, 0x003d80ba, 2733 0x00d13397, 0xfff232f8, 0x00683337, 2734 0x00000001//output gain 2735}; 2736 2737static u32 coef_192to44[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2738 0x000c6102,//header 2739 0x000000af,//input gain 2740 0x00c65663, 0xff23d2ce, 0x005f97d6, 2741 0x00086ad6, 0xff20ec4f, 0x00683201, 2742 0xffbbbef6, 0xff184447, 0x00770963, 2743 0x00000002,//output gain 2744 0x00175204,//farrow 2745 0x000aaaab, 2746 0xffaaaaab, 2747 0xfffaaaab, 2748 0x00555555, 2749 0xff600000, 2750 0xfff55555, 2751 0x00155555, 2752 0x00055555, 2753 0xffeaaaab, 2754 0x00200000, 2755 0x00235102,//header 2756 0x000013d9,//input gain 2757 0x00ebd477, 0xff4ce383, 0x0042049d, 2758 0x0089c278, 0xff54414d, 0x00531ded, 2759 0x004a5e07, 0xff53cf41, 0x006efbdc, 2760 0x00000001,//output gain 2761 0x00005102,//header 2762 0x0001d727,//input gain 2763 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2764 0x00e55557, 0xffcadd5b, 0x003d80ba, 2765 0x00d13397, 0xfff232f8, 0x00683337, 2766 0x00000001//output gain 2767}; 2768 2769static u32 coef_192to48[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2770 0x000c5102,//header 2771 0x000013d9,//input gain 2772 0x00ebd477, 0xff4ce383, 0x0042049d, 2773 0x0089c278, 0xff54414d, 0x00531ded, 2774 0x004a5e07, 0xff53cf41, 0x006efbdc, 2775 0x00000001,//output gain 2776 0x00005102,//header 2777 0x0001d727,//input gain 2778 0x00fc2fc7, 0xff9bb27b, 0x001c564c, 2779 0x00e55557, 0xffcadd5b, 0x003d80ba, 2780 0x00d13397, 0xfff232f8, 0x00683337, 2781 0x00000001//output gain 2782}; 2783 2784static u32 coef_192to88[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2785 0x000c6102,//header 2786 0x000000af,//input gain 2787 0x00c65663, 0xff23d2ce, 0x005f97d6, 2788 0x00086ad6, 0xff20ec4f, 0x00683201, 2789 0xffbbbef6, 0xff184447, 0x00770963, 2790 0x00000002,//output gain 2791 0x00175204,//farrow 2792 0x000aaaab, 2793 0xffaaaaab, 2794 0xfffaaaab, 2795 0x00555555, 2796 0xff600000, 2797 0xfff55555, 2798 0x00155555, 2799 0x00055555, 2800 0xffeaaaab, 2801 0x00200000, 2802 0x00005102,//header 2803 0x000013d9,//input gain 2804 0x00ebd477, 0xff4ce383, 0x0042049d, 2805 0x0089c278, 0xff54414d, 0x00531ded, 2806 0x004a5e07, 0xff53cf41, 0x006efbdc, 2807 0x00000001//output gain 2808}; 2809 2810static u32 coef_192to96[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2811 0x00005103,//header 2812 0x000001e0,//input gain 2813 0x00de44c0, 0xff380b7f, 0x004ffc73, 2814 0x00494b44, 0xff3d493a, 0x005908bf, 2815 0xffe9a3c8, 0xff425647, 0x006745f7, 2816 0xffc42d61, 0xff40a6c7, 0x00776709, 2817 0x00000001//output gain 2818}; 2819 2820static u32 coef_192to176[TEGRA210_SFC_COEF_RAM_DEPTH] = { 2821 0x000c6102,//header 2822 0x000000af,//input gain 2823 0x00c65663, 0xff23d2ce, 0x005f97d6, 2824 0x00086ad6, 0xff20ec4f, 0x00683201, 2825 0xffbbbef6, 0xff184447, 0x00770963, 2826 0x00000002,//output gain 2827 0x00170204,//farrow 2828 0x000aaaab, 2829 0xffaaaaab, 2830 0xfffaaaab, 2831 0x00555555, 2832 0xff600000, 2833 0xfff55555, 2834 0x00155555, 2835 0x00055555, 2836 0xffeaaaab, 2837 0x00200000, 2838 0x00005102,//header 2839 0x0000010a,//input gain 2840 0x00c93dc4, 0xff26f5f6, 0x005d1041, 2841 0x001002c4, 0xff245b76, 0x00666002, 2842 0xffc30a45, 0xff1baecd, 0x00765921, 2843 0x00000001//output gain 2844}; 2845 2846/* 2847 * Coefficient table for various sample rate conversions. The sample 2848 * rates available are as per tegra210_sfc_rates[]. 2849 */ 2850static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 2851 /* Convertions from 8 kHz */ 2852 { 2853 BYPASS_CONV, 2854 coef_8to11, 2855 coef_8to16, 2856 coef_8to22, 2857 coef_8to24, 2858 coef_8to32, 2859 coef_8to44, 2860 coef_8to48, 2861 UNSUPP_CONV, 2862 coef_8to88, 2863 coef_8to96, 2864 UNSUPP_CONV, 2865 UNSUPP_CONV, 2866 }, 2867 /* Convertions from 11.025 kHz */ 2868 { 2869 coef_11to8, 2870 BYPASS_CONV, 2871 coef_11to16, 2872 coef_11to22, 2873 coef_11to24, 2874 coef_11to32, 2875 coef_11to44, 2876 coef_11to48, 2877 UNSUPP_CONV, 2878 coef_11to88, 2879 coef_11to96, 2880 UNSUPP_CONV, 2881 UNSUPP_CONV, 2882 }, 2883 /* Convertions from 16 kHz */ 2884 { 2885 coef_16to8, 2886 coef_16to11, 2887 BYPASS_CONV, 2888 coef_16to22, 2889 coef_16to24, 2890 coef_16to32, 2891 coef_16to44, 2892 coef_16to48, 2893 UNSUPP_CONV, 2894 coef_16to88, 2895 coef_16to96, 2896 coef_16to176, 2897 coef_16to192, 2898 }, 2899 /* Convertions from 22.05 kHz */ 2900 { 2901 coef_22to8, 2902 coef_22to11, 2903 coef_22to16, 2904 BYPASS_CONV, 2905 coef_22to24, 2906 coef_22to32, 2907 coef_22to44, 2908 coef_22to48, 2909 UNSUPP_CONV, 2910 coef_22to88, 2911 coef_22to96, 2912 coef_22to176, 2913 coef_22to192, 2914 }, 2915 /* Convertions from 24 kHz */ 2916 { 2917 coef_24to8, 2918 coef_24to11, 2919 coef_24to16, 2920 coef_24to22, 2921 BYPASS_CONV, 2922 coef_24to32, 2923 coef_24to44, 2924 coef_24to48, 2925 UNSUPP_CONV, 2926 coef_24to88, 2927 coef_24to96, 2928 coef_24to176, 2929 coef_24to192, 2930 }, 2931 /* Convertions from 32 kHz */ 2932 { 2933 coef_32to8, 2934 coef_32to11, 2935 coef_32to16, 2936 coef_32to22, 2937 coef_32to24, 2938 BYPASS_CONV, 2939 coef_32to44, 2940 coef_32to48, 2941 UNSUPP_CONV, 2942 coef_32to88, 2943 coef_32to96, 2944 coef_32to176, 2945 coef_32to192, 2946 }, 2947 /* Convertions from 44.1 kHz */ 2948 { 2949 coef_44to8, 2950 coef_44to11, 2951 coef_44to16, 2952 coef_44to22, 2953 coef_44to24, 2954 coef_44to32, 2955 BYPASS_CONV, 2956 coef_44to48, 2957 UNSUPP_CONV, 2958 coef_44to88, 2959 coef_44to96, 2960 coef_44to176, 2961 coef_44to192, 2962 }, 2963 /* Convertions from 48 kHz */ 2964 { 2965 coef_48to8, 2966 coef_48to11, 2967 coef_48to16, 2968 coef_48to22, 2969 coef_48to24, 2970 coef_48to32, 2971 coef_48to44, 2972 BYPASS_CONV, 2973 UNSUPP_CONV, 2974 coef_48to88, 2975 coef_48to96, 2976 coef_48to176, 2977 coef_48to192, 2978 }, 2979 /* Convertions from 64 kHz */ 2980 { 2981 UNSUPP_CONV, 2982 UNSUPP_CONV, 2983 UNSUPP_CONV, 2984 UNSUPP_CONV, 2985 UNSUPP_CONV, 2986 UNSUPP_CONV, 2987 UNSUPP_CONV, 2988 UNSUPP_CONV, 2989 UNSUPP_CONV, 2990 UNSUPP_CONV, 2991 UNSUPP_CONV, 2992 UNSUPP_CONV, 2993 UNSUPP_CONV, 2994 }, 2995 /* Convertions from 88.2 kHz */ 2996 { 2997 coef_88to8, 2998 coef_88to11, 2999 coef_88to16, 3000 coef_88to22, 3001 coef_88to24, 3002 coef_88to32, 3003 coef_88to44, 3004 coef_88to48, 3005 UNSUPP_CONV, 3006 BYPASS_CONV, 3007 coef_88to96, 3008 coef_88to176, 3009 coef_88to192, 3010 }, 3011 /* Convertions from 96 kHz */ 3012 { coef_96to8, 3013 coef_96to11, 3014 coef_96to16, 3015 coef_96to22, 3016 coef_96to24, 3017 coef_96to32, 3018 coef_96to44, 3019 coef_96to48, 3020 UNSUPP_CONV, 3021 coef_96to88, 3022 BYPASS_CONV, 3023 coef_96to176, 3024 coef_96to192, 3025 }, 3026 /* Convertions from 176.4 kHz */ 3027 { 3028 UNSUPP_CONV, 3029 UNSUPP_CONV, 3030 coef_176to16, 3031 coef_176to22, 3032 coef_176to24, 3033 coef_176to32, 3034 coef_176to44, 3035 coef_176to48, 3036 UNSUPP_CONV, 3037 coef_176to88, 3038 coef_176to96, 3039 BYPASS_CONV, 3040 coef_176to192, 3041 }, 3042 /* Convertions from 192 kHz */ 3043 { 3044 UNSUPP_CONV, 3045 UNSUPP_CONV, 3046 coef_192to16, 3047 coef_192to22, 3048 coef_192to24, 3049 coef_192to32, 3050 coef_192to44, 3051 coef_192to48, 3052 UNSUPP_CONV, 3053 coef_192to88, 3054 coef_192to96, 3055 coef_192to176, 3056 BYPASS_CONV, 3057 }, 3058}; 3059 3060static int __maybe_unused tegra210_sfc_runtime_suspend(struct device *dev) 3061{ 3062 struct tegra210_sfc *sfc = dev_get_drvdata(dev); 3063 3064 regcache_cache_only(sfc->regmap, true); 3065 regcache_mark_dirty(sfc->regmap); 3066 3067 return 0; 3068} 3069 3070static int __maybe_unused tegra210_sfc_runtime_resume(struct device *dev) 3071{ 3072 struct tegra210_sfc *sfc = dev_get_drvdata(dev); 3073 3074 regcache_cache_only(sfc->regmap, false); 3075 regcache_sync(sfc->regmap); 3076 3077 return 0; 3078} 3079 3080static inline void tegra210_sfc_write_ram(struct regmap *regmap, 3081 s32 *data) 3082{ 3083 int i; 3084 3085 regmap_write(regmap, TEGRA210_SFC_CFG_RAM_CTRL, 3086 TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN | 3087 TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN | 3088 TEGRA210_SFC_RAM_CTRL_RW_WRITE); 3089 3090 for (i = 0; i < TEGRA210_SFC_COEF_RAM_DEPTH; i++) 3091 regmap_write(regmap, TEGRA210_SFC_CFG_RAM_DATA, data[i]); 3092} 3093 3094static int tegra210_sfc_write_coeff_ram(struct snd_soc_component *cmpnt) 3095{ 3096 struct tegra210_sfc *sfc = dev_get_drvdata(cmpnt->dev); 3097 s32 *coeff_ram; 3098 3099 /* Bypass */ 3100 if (sfc->srate_in == sfc->srate_out) 3101 return 0; 3102 3103 coeff_ram = coef_addr_table[sfc->srate_in][sfc->srate_out]; 3104 if (IS_ERR_OR_NULL(coeff_ram)) { 3105 dev_err(cmpnt->dev, 3106 "Conversion from %d to %d Hz is not supported\n", 3107 sfc->srate_in, sfc->srate_out); 3108 3109 return PTR_ERR_OR_ZERO(coeff_ram); 3110 } 3111 3112 tegra210_sfc_write_ram(sfc->regmap, coeff_ram); 3113 3114 regmap_update_bits(sfc->regmap, 3115 TEGRA210_SFC_COEF_RAM, 3116 TEGRA210_SFC_COEF_RAM_EN, 3117 TEGRA210_SFC_COEF_RAM_EN); 3118 3119 return 0; 3120} 3121 3122static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc, 3123 struct snd_pcm_hw_params *params, 3124 unsigned int reg) 3125{ 3126 unsigned int channels, audio_bits, path; 3127 struct tegra_cif_conf cif_conf; 3128 3129 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf)); 3130 3131 channels = params_channels(params); 3132 3133 switch (params_format(params)) { 3134 case SNDRV_PCM_FORMAT_S16_LE: 3135 audio_bits = TEGRA_ACIF_BITS_16; 3136 break; 3137 case SNDRV_PCM_FORMAT_S32_LE: 3138 audio_bits = TEGRA_ACIF_BITS_32; 3139 break; 3140 default: 3141 return -EOPNOTSUPP; 3142 } 3143 3144 cif_conf.audio_ch = channels; 3145 cif_conf.client_ch = channels; 3146 cif_conf.audio_bits = audio_bits; 3147 cif_conf.client_bits = TEGRA_ACIF_BITS_32; 3148 3149 if (reg == TEGRA210_SFC_RX_CIF_CTRL) 3150 path = SFC_RX_PATH; 3151 else 3152 path = SFC_TX_PATH; 3153 3154 cif_conf.stereo_conv = sfc->stereo_to_mono[path]; 3155 cif_conf.mono_conv = sfc->mono_to_stereo[path]; 3156 3157 tegra_set_cif(sfc->regmap, reg, &cif_conf); 3158 3159 return 0; 3160} 3161 3162static int tegra210_sfc_soft_reset(struct tegra210_sfc *sfc) 3163{ 3164 u32 val; 3165 3166 /* 3167 * Soft Reset: Below performs module soft reset which clears 3168 * all FSM logic, flushes flow control of FIFO and resets the 3169 * state register. It also brings module back to disabled 3170 * state (without flushing the data in the pipe). 3171 */ 3172 regmap_update_bits(sfc->regmap, TEGRA210_SFC_SOFT_RESET, 3173 TEGRA210_SFC_SOFT_RESET_EN, 1); 3174 3175 return regmap_read_poll_timeout(sfc->regmap, 3176 TEGRA210_SFC_SOFT_RESET, 3177 val, 3178 !(val & TEGRA210_SFC_SOFT_RESET_EN), 3179 10, 10000); 3180} 3181 3182static int tegra210_sfc_rate_to_idx(struct device *dev, int rate, 3183 int *rate_idx) 3184{ 3185 int i; 3186 3187 for (i = 0; i < ARRAY_SIZE(tegra210_sfc_rates); i++) { 3188 if (rate == tegra210_sfc_rates[i]) { 3189 *rate_idx = i; 3190 3191 return 0; 3192 } 3193 } 3194 3195 dev_err(dev, "Sample rate %d Hz is not supported\n", rate); 3196 3197 return -EOPNOTSUPP; 3198} 3199 3200static int tegra210_sfc_startup(struct snd_pcm_substream *substream, 3201 struct snd_soc_dai *dai) 3202{ 3203 struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai); 3204 int err; 3205 3206 regmap_update_bits(sfc->regmap, TEGRA210_SFC_COEF_RAM, 3207 TEGRA210_SFC_COEF_RAM_EN, 0); 3208 3209 err = tegra210_sfc_soft_reset(sfc); 3210 if (err < 0) { 3211 dev_err(dai->dev, "Failed to reset SFC in %s, err = %d\n", 3212 __func__, err); 3213 3214 return err; 3215 } 3216 3217 return 0; 3218} 3219 3220static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream, 3221 struct snd_pcm_hw_params *params, 3222 struct snd_soc_dai *dai) 3223{ 3224 struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai); 3225 struct device *dev = dai->dev; 3226 int err; 3227 3228 err = tegra210_sfc_rate_to_idx(dev, params_rate(params), 3229 &sfc->srate_in); 3230 if (err < 0) 3231 return err; 3232 3233 err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_RX_CIF_CTRL); 3234 if (err < 0) { 3235 dev_err(dev, "Can't set SFC RX CIF: %d\n", err); 3236 return err; 3237 } 3238 3239 regmap_write(sfc->regmap, TEGRA210_SFC_RX_FREQ, sfc->srate_in); 3240 3241 return err; 3242} 3243 3244static int tegra210_sfc_out_hw_params(struct snd_pcm_substream *substream, 3245 struct snd_pcm_hw_params *params, 3246 struct snd_soc_dai *dai) 3247{ 3248 struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai); 3249 struct device *dev = dai->dev; 3250 int err; 3251 3252 err = tegra210_sfc_rate_to_idx(dev, params_rate(params), 3253 &sfc->srate_out); 3254 if (err < 0) 3255 return err; 3256 3257 err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_TX_CIF_CTRL); 3258 if (err < 0) { 3259 dev_err(dev, "Can't set SFC TX CIF: %d\n", err); 3260 return err; 3261 } 3262 3263 regmap_write(sfc->regmap, TEGRA210_SFC_TX_FREQ, sfc->srate_out); 3264 3265 return 0; 3266} 3267 3268static int tegra210_sfc_init(struct snd_soc_dapm_widget *w, 3269 struct snd_kcontrol *kcontrol, int event) 3270{ 3271 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 3272 3273 return tegra210_sfc_write_coeff_ram(cmpnt); 3274} 3275 3276static int tegra210_sfc_iget_stereo_to_mono(struct snd_kcontrol *kcontrol, 3277 struct snd_ctl_elem_value *ucontrol) 3278{ 3279 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3280 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3281 3282 ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_RX_PATH]; 3283 3284 return 0; 3285} 3286 3287static int tegra210_sfc_iput_stereo_to_mono(struct snd_kcontrol *kcontrol, 3288 struct snd_ctl_elem_value *ucontrol) 3289{ 3290 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3291 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3292 unsigned int value = ucontrol->value.enumerated.item[0]; 3293 3294 if (value == sfc->stereo_to_mono[SFC_RX_PATH]) 3295 return 0; 3296 3297 sfc->stereo_to_mono[SFC_RX_PATH] = value; 3298 3299 return 1; 3300} 3301 3302static int tegra210_sfc_iget_mono_to_stereo(struct snd_kcontrol *kcontrol, 3303 struct snd_ctl_elem_value *ucontrol) 3304{ 3305 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3306 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3307 3308 ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_RX_PATH]; 3309 3310 return 0; 3311} 3312 3313static int tegra210_sfc_iput_mono_to_stereo(struct snd_kcontrol *kcontrol, 3314 struct snd_ctl_elem_value *ucontrol) 3315{ 3316 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3317 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3318 unsigned int value = ucontrol->value.enumerated.item[0]; 3319 3320 if (value == sfc->mono_to_stereo[SFC_RX_PATH]) 3321 return 0; 3322 3323 sfc->mono_to_stereo[SFC_RX_PATH] = value; 3324 3325 return 1; 3326} 3327 3328static int tegra210_sfc_oget_stereo_to_mono(struct snd_kcontrol *kcontrol, 3329 struct snd_ctl_elem_value *ucontrol) 3330{ 3331 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3332 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3333 3334 ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_TX_PATH]; 3335 3336 return 0; 3337} 3338 3339static int tegra210_sfc_oput_stereo_to_mono(struct snd_kcontrol *kcontrol, 3340 struct snd_ctl_elem_value *ucontrol) 3341{ 3342 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3343 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3344 unsigned int value = ucontrol->value.enumerated.item[0]; 3345 3346 if (value == sfc->stereo_to_mono[SFC_TX_PATH]) 3347 return 0; 3348 3349 sfc->stereo_to_mono[SFC_TX_PATH] = value; 3350 3351 return 1; 3352} 3353 3354static int tegra210_sfc_oget_mono_to_stereo(struct snd_kcontrol *kcontrol, 3355 struct snd_ctl_elem_value *ucontrol) 3356{ 3357 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3358 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3359 3360 ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_TX_PATH]; 3361 3362 return 0; 3363} 3364 3365static int tegra210_sfc_oput_mono_to_stereo(struct snd_kcontrol *kcontrol, 3366 struct snd_ctl_elem_value *ucontrol) 3367{ 3368 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 3369 struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt); 3370 unsigned int value = ucontrol->value.enumerated.item[0]; 3371 3372 if (value == sfc->mono_to_stereo[SFC_TX_PATH]) 3373 return 0; 3374 3375 sfc->mono_to_stereo[SFC_TX_PATH] = value; 3376 3377 return 1; 3378} 3379 3380static const struct snd_soc_dai_ops tegra210_sfc_in_dai_ops = { 3381 .hw_params = tegra210_sfc_in_hw_params, 3382 .startup = tegra210_sfc_startup, 3383}; 3384 3385static const struct snd_soc_dai_ops tegra210_sfc_out_dai_ops = { 3386 .hw_params = tegra210_sfc_out_hw_params, 3387}; 3388 3389static struct snd_soc_dai_driver tegra210_sfc_dais[] = { 3390 { 3391 .name = "SFC-RX-CIF", 3392 .playback = { 3393 .stream_name = "RX-CIF-Playback", 3394 .channels_min = 1, 3395 .channels_max = 2, 3396 .rates = SNDRV_PCM_RATE_8000_192000, 3397 .formats = SNDRV_PCM_FMTBIT_S8 | 3398 SNDRV_PCM_FMTBIT_S16_LE | 3399 SNDRV_PCM_FMTBIT_S32_LE, 3400 }, 3401 .capture = { 3402 .stream_name = "RX-CIF-Capture", 3403 .channels_min = 1, 3404 .channels_max = 2, 3405 .rates = SNDRV_PCM_RATE_8000_192000, 3406 .formats = SNDRV_PCM_FMTBIT_S8 | 3407 SNDRV_PCM_FMTBIT_S16_LE | 3408 SNDRV_PCM_FMTBIT_S32_LE, 3409 }, 3410 .ops = &tegra210_sfc_in_dai_ops, 3411 }, 3412 { 3413 .name = "SFC-TX-CIF", 3414 .playback = { 3415 .stream_name = "TX-CIF-Playback", 3416 .channels_min = 1, 3417 .channels_max = 2, 3418 .rates = SNDRV_PCM_RATE_8000_192000, 3419 .formats = SNDRV_PCM_FMTBIT_S8 | 3420 SNDRV_PCM_FMTBIT_S16_LE | 3421 SNDRV_PCM_FMTBIT_S32_LE, 3422 }, 3423 .capture = { 3424 .stream_name = "TX-CIF-Capture", 3425 .channels_min = 1, 3426 .channels_max = 2, 3427 .rates = SNDRV_PCM_RATE_8000_192000, 3428 .formats = SNDRV_PCM_FMTBIT_S8 | 3429 SNDRV_PCM_FMTBIT_S16_LE | 3430 SNDRV_PCM_FMTBIT_S32_LE, 3431 }, 3432 .ops = &tegra210_sfc_out_dai_ops, 3433 }, 3434}; 3435 3436static const struct snd_soc_dapm_widget tegra210_sfc_widgets[] = { 3437 SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0), 3438 SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_SFC_ENABLE, 3439 TEGRA210_SFC_EN_SHIFT, 0, 3440 tegra210_sfc_init, SND_SOC_DAPM_PRE_PMU), 3441}; 3442 3443#define RESAMPLE_ROUTE(sname) \ 3444 { "RX XBAR-" sname, NULL, "XBAR-TX" }, \ 3445 { "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \ 3446 { "RX", NULL, "RX-CIF-" sname }, \ 3447 { "TX-CIF-" sname, NULL, "TX" }, \ 3448 { "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \ 3449 { "XBAR-RX", NULL, "TX XBAR-" sname } 3450 3451static const struct snd_soc_dapm_route tegra210_sfc_routes[] = { 3452 { "TX", NULL, "RX" }, 3453 RESAMPLE_ROUTE("Playback"), 3454 RESAMPLE_ROUTE("Capture"), 3455}; 3456 3457static const char * const tegra210_sfc_stereo_conv_text[] = { 3458 "CH0", "CH1", "AVG", 3459}; 3460 3461static const char * const tegra210_sfc_mono_conv_text[] = { 3462 "Zero", "Copy", 3463}; 3464 3465static const struct soc_enum tegra210_sfc_stereo_conv_enum = 3466 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 3467 ARRAY_SIZE(tegra210_sfc_stereo_conv_text), 3468 tegra210_sfc_stereo_conv_text); 3469 3470static const struct soc_enum tegra210_sfc_mono_conv_enum = 3471 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 3472 ARRAY_SIZE(tegra210_sfc_mono_conv_text), 3473 tegra210_sfc_mono_conv_text); 3474 3475static const struct snd_kcontrol_new tegra210_sfc_controls[] = { 3476 SOC_ENUM_EXT("Input Stereo To Mono", tegra210_sfc_stereo_conv_enum, 3477 tegra210_sfc_iget_stereo_to_mono, 3478 tegra210_sfc_iput_stereo_to_mono), 3479 SOC_ENUM_EXT("Input Mono To Stereo", tegra210_sfc_mono_conv_enum, 3480 tegra210_sfc_iget_mono_to_stereo, 3481 tegra210_sfc_iput_mono_to_stereo), 3482 SOC_ENUM_EXT("Output Stereo To Mono", tegra210_sfc_stereo_conv_enum, 3483 tegra210_sfc_oget_stereo_to_mono, 3484 tegra210_sfc_oput_stereo_to_mono), 3485 SOC_ENUM_EXT("Output Mono To Stereo", tegra210_sfc_mono_conv_enum, 3486 tegra210_sfc_oget_mono_to_stereo, 3487 tegra210_sfc_oput_mono_to_stereo), 3488}; 3489 3490static const struct snd_soc_component_driver tegra210_sfc_cmpnt = { 3491 .dapm_widgets = tegra210_sfc_widgets, 3492 .num_dapm_widgets = ARRAY_SIZE(tegra210_sfc_widgets), 3493 .dapm_routes = tegra210_sfc_routes, 3494 .num_dapm_routes = ARRAY_SIZE(tegra210_sfc_routes), 3495 .controls = tegra210_sfc_controls, 3496 .num_controls = ARRAY_SIZE(tegra210_sfc_controls), 3497}; 3498 3499static bool tegra210_sfc_wr_reg(struct device *dev, unsigned int reg) 3500{ 3501 switch (reg) { 3502 case TEGRA210_SFC_RX_INT_MASK ... TEGRA210_SFC_RX_FREQ: 3503 case TEGRA210_SFC_TX_INT_MASK ... TEGRA210_SFC_TX_FREQ: 3504 case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_CG: 3505 case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA: 3506 return true; 3507 default: 3508 return false; 3509 } 3510} 3511 3512static bool tegra210_sfc_rd_reg(struct device *dev, unsigned int reg) 3513{ 3514 switch (reg) { 3515 case TEGRA210_SFC_RX_STATUS ... TEGRA210_SFC_RX_FREQ: 3516 case TEGRA210_SFC_TX_STATUS ... TEGRA210_SFC_TX_FREQ: 3517 case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_INT_STATUS: 3518 case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA: 3519 return true; 3520 default: 3521 return false; 3522 } 3523} 3524 3525static bool tegra210_sfc_volatile_reg(struct device *dev, unsigned int reg) 3526{ 3527 switch (reg) { 3528 case TEGRA210_SFC_RX_STATUS: 3529 case TEGRA210_SFC_RX_INT_STATUS: 3530 case TEGRA210_SFC_RX_INT_SET: 3531 3532 case TEGRA210_SFC_TX_STATUS: 3533 case TEGRA210_SFC_TX_INT_STATUS: 3534 case TEGRA210_SFC_TX_INT_SET: 3535 3536 case TEGRA210_SFC_SOFT_RESET: 3537 case TEGRA210_SFC_STATUS: 3538 case TEGRA210_SFC_INT_STATUS: 3539 case TEGRA210_SFC_CFG_RAM_CTRL: 3540 case TEGRA210_SFC_CFG_RAM_DATA: 3541 return true; 3542 default: 3543 return false; 3544 } 3545} 3546 3547static bool tegra210_sfc_precious_reg(struct device *dev, unsigned int reg) 3548{ 3549 switch (reg) { 3550 case TEGRA210_SFC_CFG_RAM_DATA: 3551 return true; 3552 default: 3553 return false; 3554 } 3555} 3556 3557static const struct regmap_config tegra210_sfc_regmap_config = { 3558 .reg_bits = 32, 3559 .reg_stride = 4, 3560 .val_bits = 32, 3561 .max_register = TEGRA210_SFC_CFG_RAM_DATA, 3562 .writeable_reg = tegra210_sfc_wr_reg, 3563 .readable_reg = tegra210_sfc_rd_reg, 3564 .volatile_reg = tegra210_sfc_volatile_reg, 3565 .precious_reg = tegra210_sfc_precious_reg, 3566 .reg_defaults = tegra210_sfc_reg_defaults, 3567 .num_reg_defaults = ARRAY_SIZE(tegra210_sfc_reg_defaults), 3568 .cache_type = REGCACHE_FLAT, 3569}; 3570 3571static const struct of_device_id tegra210_sfc_of_match[] = { 3572 { .compatible = "nvidia,tegra210-sfc" }, 3573 {}, 3574}; 3575MODULE_DEVICE_TABLE(of, tegra210_sfc_of_match); 3576 3577static int tegra210_sfc_platform_probe(struct platform_device *pdev) 3578{ 3579 struct device *dev = &pdev->dev; 3580 struct tegra210_sfc *sfc; 3581 void __iomem *regs; 3582 int err; 3583 3584 sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL); 3585 if (!sfc) 3586 return -ENOMEM; 3587 3588 dev_set_drvdata(dev, sfc); 3589 3590 regs = devm_platform_ioremap_resource(pdev, 0); 3591 if (IS_ERR(regs)) 3592 return PTR_ERR(regs); 3593 3594 sfc->regmap = devm_regmap_init_mmio(dev, regs, 3595 &tegra210_sfc_regmap_config); 3596 if (IS_ERR(sfc->regmap)) { 3597 dev_err(dev, "regmap init failed\n"); 3598 return PTR_ERR(sfc->regmap); 3599 } 3600 3601 regcache_cache_only(sfc->regmap, true); 3602 3603 err = devm_snd_soc_register_component(dev, &tegra210_sfc_cmpnt, 3604 tegra210_sfc_dais, 3605 ARRAY_SIZE(tegra210_sfc_dais)); 3606 if (err) { 3607 dev_err(dev, "can't register SFC component, err: %d\n", err); 3608 return err; 3609 } 3610 3611 pm_runtime_enable(&pdev->dev); 3612 3613 return 0; 3614} 3615 3616static void tegra210_sfc_platform_remove(struct platform_device *pdev) 3617{ 3618 pm_runtime_disable(&pdev->dev); 3619} 3620 3621static const struct dev_pm_ops tegra210_sfc_pm_ops = { 3622 SET_RUNTIME_PM_OPS(tegra210_sfc_runtime_suspend, 3623 tegra210_sfc_runtime_resume, NULL) 3624 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 3625 pm_runtime_force_resume) 3626}; 3627 3628static struct platform_driver tegra210_sfc_driver = { 3629 .driver = { 3630 .name = "tegra210-sfc", 3631 .of_match_table = tegra210_sfc_of_match, 3632 .pm = &tegra210_sfc_pm_ops, 3633 }, 3634 .probe = tegra210_sfc_platform_probe, 3635 .remove_new = tegra210_sfc_platform_remove, 3636}; 3637module_platform_driver(tegra210_sfc_driver) 3638 3639MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>"); 3640MODULE_DESCRIPTION("Tegra210 SFC ASoC driver"); 3641MODULE_LICENSE("GPL v2"); 3642