1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
4 *
5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
6 *
7 * Partly based on code copyright/by:
8 *
9 * Copyright (c) 2011,2012 Toradex Inc.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/reset.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/dmaengine_pcm.h>
30
31#include "tegra20_ac97.h"
32
33#define DRV_NAME "tegra20-ac97"
34
35static struct tegra20_ac97 *workdata;
36
37static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
38{
39	u32 readback;
40	unsigned long timeout;
41
42	/* reset line is not driven by DAC pad group, have to toggle GPIO */
43	gpio_set_value(workdata->reset_gpio, 0);
44	udelay(2);
45
46	gpio_set_value(workdata->reset_gpio, 1);
47	udelay(2);
48
49	timeout = jiffies + msecs_to_jiffies(100);
50
51	do {
52		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
53		if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
54			break;
55		usleep_range(1000, 2000);
56	} while (!time_after(jiffies, timeout));
57}
58
59static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
60{
61	u32 readback;
62	unsigned long timeout;
63
64	/*
65	 * although sync line is driven by the DAC pad group warm reset using
66	 * the controller cmd is not working, have to toggle sync line
67	 * manually.
68	 */
69	gpio_request(workdata->sync_gpio, "codec-sync");
70
71	gpio_direction_output(workdata->sync_gpio, 1);
72
73	udelay(2);
74	gpio_set_value(workdata->sync_gpio, 0);
75	udelay(2);
76	gpio_free(workdata->sync_gpio);
77
78	timeout = jiffies + msecs_to_jiffies(100);
79
80	do {
81		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
82		if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
83			break;
84		usleep_range(1000, 2000);
85	} while (!time_after(jiffies, timeout));
86}
87
88static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
89					      unsigned short reg)
90{
91	u32 readback;
92	unsigned long timeout;
93
94	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
95		     (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
96		      TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
97		     TEGRA20_AC97_CMD_BUSY);
98
99	timeout = jiffies + msecs_to_jiffies(100);
100
101	do {
102		regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
103		if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
104			break;
105		usleep_range(1000, 2000);
106	} while (!time_after(jiffies, timeout));
107
108	return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
109		TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
110}
111
112static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
113				     unsigned short reg, unsigned short val)
114{
115	u32 readback;
116	unsigned long timeout;
117
118	regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
119		     ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
120		      TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
121		     ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
122		      TEGRA20_AC97_CMD_CMD_DATA_MASK) |
123		     TEGRA20_AC97_CMD_BUSY);
124
125	timeout = jiffies + msecs_to_jiffies(100);
126
127	do {
128		regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
129		if (!(readback & TEGRA20_AC97_CMD_BUSY))
130			break;
131		usleep_range(1000, 2000);
132	} while (!time_after(jiffies, timeout));
133}
134
135static struct snd_ac97_bus_ops tegra20_ac97_ops = {
136	.read		= tegra20_ac97_codec_read,
137	.write		= tegra20_ac97_codec_write,
138	.reset		= tegra20_ac97_codec_reset,
139	.warm_reset	= tegra20_ac97_codec_warm_reset,
140};
141
142static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
143{
144	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
145			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
146			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
147
148	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
149			   TEGRA20_AC97_CTRL_PCM_DAC_EN |
150			   TEGRA20_AC97_CTRL_STM_EN,
151			   TEGRA20_AC97_CTRL_PCM_DAC_EN |
152			   TEGRA20_AC97_CTRL_STM_EN);
153}
154
155static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
156{
157	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
158			   TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
159
160	regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
161			   TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
162}
163
164static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
165{
166	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
167			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
168			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
169}
170
171static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
172{
173	regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
174			   TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
175}
176
177static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
178				struct snd_soc_dai *dai)
179{
180	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
181
182	switch (cmd) {
183	case SNDRV_PCM_TRIGGER_START:
184	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
185	case SNDRV_PCM_TRIGGER_RESUME:
186		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
187			tegra20_ac97_start_playback(ac97);
188		else
189			tegra20_ac97_start_capture(ac97);
190		break;
191	case SNDRV_PCM_TRIGGER_STOP:
192	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
193	case SNDRV_PCM_TRIGGER_SUSPEND:
194		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
195			tegra20_ac97_stop_playback(ac97);
196		else
197			tegra20_ac97_stop_capture(ac97);
198		break;
199	default:
200		return -EINVAL;
201	}
202
203	return 0;
204}
205
206static int tegra20_ac97_probe(struct snd_soc_dai *dai)
207{
208	struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
209
210	snd_soc_dai_init_dma_data(dai,	&ac97->playback_dma_data,
211					&ac97->capture_dma_data);
212
213	return 0;
214}
215
216static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
217	.probe		= tegra20_ac97_probe,
218	.trigger	= tegra20_ac97_trigger,
219};
220
221static struct snd_soc_dai_driver tegra20_ac97_dai = {
222	.name = "tegra-ac97-pcm",
223	.playback = {
224		.stream_name = "PCM Playback",
225		.channels_min = 2,
226		.channels_max = 2,
227		.rates = SNDRV_PCM_RATE_8000_48000,
228		.formats = SNDRV_PCM_FMTBIT_S16_LE,
229	},
230	.capture = {
231		.stream_name = "PCM Capture",
232		.channels_min = 2,
233		.channels_max = 2,
234		.rates = SNDRV_PCM_RATE_8000_48000,
235		.formats = SNDRV_PCM_FMTBIT_S16_LE,
236	},
237	.ops = &tegra20_ac97_dai_ops,
238};
239
240static const struct snd_soc_component_driver tegra20_ac97_component = {
241	.name			= DRV_NAME,
242	.legacy_dai_naming	= 1,
243};
244
245static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
246{
247	switch (reg) {
248	case TEGRA20_AC97_CTRL:
249	case TEGRA20_AC97_CMD:
250	case TEGRA20_AC97_STATUS1:
251	case TEGRA20_AC97_FIFO1_SCR:
252	case TEGRA20_AC97_FIFO_TX1:
253	case TEGRA20_AC97_FIFO_RX1:
254		return true;
255	default:
256		break;
257	}
258
259	return false;
260}
261
262static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
263{
264	switch (reg) {
265	case TEGRA20_AC97_STATUS1:
266	case TEGRA20_AC97_FIFO1_SCR:
267	case TEGRA20_AC97_FIFO_TX1:
268	case TEGRA20_AC97_FIFO_RX1:
269		return true;
270	default:
271		break;
272	}
273
274	return false;
275}
276
277static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
278{
279	switch (reg) {
280	case TEGRA20_AC97_FIFO_TX1:
281	case TEGRA20_AC97_FIFO_RX1:
282		return true;
283	default:
284		break;
285	}
286
287	return false;
288}
289
290static const struct regmap_config tegra20_ac97_regmap_config = {
291	.reg_bits = 32,
292	.reg_stride = 4,
293	.val_bits = 32,
294	.max_register = TEGRA20_AC97_FIFO_RX1,
295	.writeable_reg = tegra20_ac97_wr_rd_reg,
296	.readable_reg = tegra20_ac97_wr_rd_reg,
297	.volatile_reg = tegra20_ac97_volatile_reg,
298	.precious_reg = tegra20_ac97_precious_reg,
299	.cache_type = REGCACHE_FLAT,
300};
301
302static int tegra20_ac97_platform_probe(struct platform_device *pdev)
303{
304	struct tegra20_ac97 *ac97;
305	struct resource *mem;
306	void __iomem *regs;
307	int ret = 0;
308
309	ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
310			    GFP_KERNEL);
311	if (!ac97) {
312		ret = -ENOMEM;
313		goto err;
314	}
315	dev_set_drvdata(&pdev->dev, ac97);
316
317	ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
318	if (IS_ERR(ac97->reset)) {
319		dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
320		ret = PTR_ERR(ac97->reset);
321		goto err;
322	}
323
324	ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
325	if (IS_ERR(ac97->clk_ac97)) {
326		dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
327		ret = PTR_ERR(ac97->clk_ac97);
328		goto err;
329	}
330
331	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
332	if (IS_ERR(regs)) {
333		ret = PTR_ERR(regs);
334		goto err_clk_put;
335	}
336
337	ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
338					    &tegra20_ac97_regmap_config);
339	if (IS_ERR(ac97->regmap)) {
340		dev_err(&pdev->dev, "regmap init failed\n");
341		ret = PTR_ERR(ac97->regmap);
342		goto err_clk_put;
343	}
344
345	ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
346					     "nvidia,codec-reset-gpio", 0);
347	if (gpio_is_valid(ac97->reset_gpio)) {
348		ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
349					    GPIOF_OUT_INIT_HIGH, "codec-reset");
350		if (ret) {
351			dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
352			goto err_clk_put;
353		}
354	} else {
355		dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
356		ret = -EINVAL;
357		goto err_clk_put;
358	}
359
360	ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
361					    "nvidia,codec-sync-gpio", 0);
362	if (!gpio_is_valid(ac97->sync_gpio)) {
363		dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
364		ret = -EINVAL;
365		goto err_clk_put;
366	}
367
368	ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
369	ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
370	ac97->capture_dma_data.maxburst = 4;
371
372	ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
373	ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
374	ac97->playback_dma_data.maxburst = 4;
375
376	ret = reset_control_assert(ac97->reset);
377	if (ret) {
378		dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret);
379		goto err_clk_put;
380	}
381
382	ret = clk_prepare_enable(ac97->clk_ac97);
383	if (ret) {
384		dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
385		goto err_clk_put;
386	}
387
388	usleep_range(10, 100);
389
390	ret = reset_control_deassert(ac97->reset);
391	if (ret) {
392		dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret);
393		goto err_clk_disable_unprepare;
394	}
395
396	ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
397	if (ret) {
398		dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
399		goto err_clk_disable_unprepare;
400	}
401
402	ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
403					 &tegra20_ac97_dai, 1);
404	if (ret) {
405		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
406		ret = -ENOMEM;
407		goto err_clk_disable_unprepare;
408	}
409
410	ret = tegra_pcm_platform_register(&pdev->dev);
411	if (ret) {
412		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
413		goto err_unregister_component;
414	}
415
416	/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
417	workdata = ac97;
418
419	return 0;
420
421err_unregister_component:
422	snd_soc_unregister_component(&pdev->dev);
423err_clk_disable_unprepare:
424	clk_disable_unprepare(ac97->clk_ac97);
425err_clk_put:
426err:
427	snd_soc_set_ac97_ops(NULL);
428	return ret;
429}
430
431static void tegra20_ac97_platform_remove(struct platform_device *pdev)
432{
433	struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
434
435	tegra_pcm_platform_unregister(&pdev->dev);
436	snd_soc_unregister_component(&pdev->dev);
437
438	clk_disable_unprepare(ac97->clk_ac97);
439
440	snd_soc_set_ac97_ops(NULL);
441}
442
443static const struct of_device_id tegra20_ac97_of_match[] = {
444	{ .compatible = "nvidia,tegra20-ac97", },
445	{},
446};
447
448static struct platform_driver tegra20_ac97_driver = {
449	.driver = {
450		.name = DRV_NAME,
451		.of_match_table = tegra20_ac97_of_match,
452	},
453	.probe = tegra20_ac97_platform_probe,
454	.remove_new = tegra20_ac97_platform_remove,
455};
456module_platform_driver(tegra20_ac97_driver);
457
458MODULE_AUTHOR("Lucas Stach");
459MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
460MODULE_LICENSE("GPL v2");
461MODULE_ALIAS("platform:" DRV_NAME);
462MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
463