162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * SPEAr SPDIF OUT controller header file
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (ST) 2011 Vipin Kumar (vipin.kumar@st.com)
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#ifndef SPDIF_OUT_REGS_H
962306a36Sopenharmony_ci#define SPDIF_OUT_REGS_H
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#define SPDIF_OUT_SOFT_RST	0x00
1262306a36Sopenharmony_ci	#define SPDIF_OUT_RESET		(1 << 0)
1362306a36Sopenharmony_ci#define SPDIF_OUT_FIFO_DATA	0x04
1462306a36Sopenharmony_ci#define SPDIF_OUT_INT_STA	0x08
1562306a36Sopenharmony_ci#define SPDIF_OUT_INT_STA_CLR	0x0C
1662306a36Sopenharmony_ci	#define SPDIF_INT_UNDERFLOW	(1 << 0)
1762306a36Sopenharmony_ci	#define SPDIF_INT_EODATA	(1 << 1)
1862306a36Sopenharmony_ci	#define SPDIF_INT_EOBLOCK	(1 << 2)
1962306a36Sopenharmony_ci	#define SPDIF_INT_EOLATENCY	(1 << 3)
2062306a36Sopenharmony_ci	#define SPDIF_INT_EOPD_DATA	(1 << 4)
2162306a36Sopenharmony_ci	#define SPDIF_INT_MEMFULLREAD	(1 << 5)
2262306a36Sopenharmony_ci	#define SPDIF_INT_EOPD_PAUSE	(1 << 6)
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci#define SPDIF_OUT_INT_EN	0x10
2562306a36Sopenharmony_ci#define SPDIF_OUT_INT_EN_SET	0x14
2662306a36Sopenharmony_ci#define SPDIF_OUT_INT_EN_CLR	0x18
2762306a36Sopenharmony_ci#define SPDIF_OUT_CTRL		0x1C
2862306a36Sopenharmony_ci	#define SPDIF_OPMODE_MASK	(7 << 0)
2962306a36Sopenharmony_ci	#define SPDIF_OPMODE_OFF	(0 << 0)
3062306a36Sopenharmony_ci	#define SPDIF_OPMODE_MUTE_PCM	(1 << 0)
3162306a36Sopenharmony_ci	#define SPDIF_OPMODE_MUTE_PAUSE	(2 << 0)
3262306a36Sopenharmony_ci	#define SPDIF_OPMODE_AUD_DATA	(3 << 0)
3362306a36Sopenharmony_ci	#define SPDIF_OPMODE_ENCODE	(4 << 0)
3462306a36Sopenharmony_ci	#define SPDIF_STATE_NORMAL	(1 << 3)
3562306a36Sopenharmony_ci	#define SPDIF_DIVIDER_MASK	(0xff << 5)
3662306a36Sopenharmony_ci	#define SPDIF_DIVIDER_SHIFT	(5)
3762306a36Sopenharmony_ci	#define SPDIF_SAMPLEREAD_MASK	(0x1ffff << 15)
3862306a36Sopenharmony_ci	#define SPDIF_SAMPLEREAD_SHIFT	(15)
3962306a36Sopenharmony_ci#define SPDIF_OUT_STA		0x20
4062306a36Sopenharmony_ci#define SPDIF_OUT_PA_PB		0x24
4162306a36Sopenharmony_ci#define SPDIF_OUT_PC_PD		0x28
4262306a36Sopenharmony_ci#define SPDIF_OUT_CL1		0x2C
4362306a36Sopenharmony_ci#define SPDIF_OUT_CR1		0x30
4462306a36Sopenharmony_ci#define SPDIF_OUT_CL2_CR2_UV	0x34
4562306a36Sopenharmony_ci#define SPDIF_OUT_PAUSE_LAT	0x38
4662306a36Sopenharmony_ci#define SPDIF_OUT_FRMLEN_BRST	0x3C
4762306a36Sopenharmony_ci#define SPDIF_OUT_CFG		0x40
4862306a36Sopenharmony_ci	#define SPDIF_OUT_MEMFMT_16_0	(0 << 5)
4962306a36Sopenharmony_ci	#define SPDIF_OUT_MEMFMT_16_16	(1 << 5)
5062306a36Sopenharmony_ci	#define SPDIF_OUT_VALID_DMA	(0 << 3)
5162306a36Sopenharmony_ci	#define SPDIF_OUT_VALID_HW	(1 << 3)
5262306a36Sopenharmony_ci	#define SPDIF_OUT_USER_DMA	(0 << 2)
5362306a36Sopenharmony_ci	#define SPDIF_OUT_USER_HW	(1 << 2)
5462306a36Sopenharmony_ci	#define SPDIF_OUT_CHNLSTA_DMA	(0 << 1)
5562306a36Sopenharmony_ci	#define SPDIF_OUT_CHNLSTA_HW	(1 << 1)
5662306a36Sopenharmony_ci	#define SPDIF_OUT_PARITY_HW	(0 << 0)
5762306a36Sopenharmony_ci	#define SPDIF_OUT_PARITY_DMA	(1 << 0)
5862306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_2	(2 << 8)
5962306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_6	(6 << 8)
6062306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_8	(8 << 8)
6162306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_10	(10 << 8)
6262306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_12	(12 << 8)
6362306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_16	(16 << 8)
6462306a36Sopenharmony_ci	#define SPDIF_OUT_FDMA_TRIG_18	(18 << 8)
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci#endif /* SPDIF_OUT_REGS_H */
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