162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci/* 462306a36Sopenharmony_ci * Copyright (c) 2021 MediaTek Corporation. All rights reserved. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * Header file for the mt8195 DSP clock definition 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#ifndef __MT8195_CLK_H 1062306a36Sopenharmony_ci#define __MT8195_CLK_H 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cistruct snd_sof_dev; 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/*DSP clock*/ 1562306a36Sopenharmony_cienum adsp_clk_id { 1662306a36Sopenharmony_ci CLK_TOP_ADSP, 1762306a36Sopenharmony_ci CLK_TOP_CLK26M, 1862306a36Sopenharmony_ci CLK_TOP_AUDIO_LOCAL_BUS, 1962306a36Sopenharmony_ci CLK_TOP_MAINPLL_D7_D2, 2062306a36Sopenharmony_ci CLK_SCP_ADSP_AUDIODSP, 2162306a36Sopenharmony_ci CLK_TOP_AUDIO_H, 2262306a36Sopenharmony_ci ADSP_CLK_MAX 2362306a36Sopenharmony_ci}; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciint mt8195_adsp_init_clock(struct snd_sof_dev *sdev); 2662306a36Sopenharmony_ciint adsp_clock_on(struct snd_sof_dev *sdev); 2762306a36Sopenharmony_ciint adsp_clock_off(struct snd_sof_dev *sdev); 2862306a36Sopenharmony_ci#endif 29