162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 262306a36Sopenharmony_ci// 362306a36Sopenharmony_ci// Copyright (c) 2022 Mediatek Corporation. All rights reserved. 462306a36Sopenharmony_ci// 562306a36Sopenharmony_ci// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 662306a36Sopenharmony_ci// Tinghan Shen <tinghan.shen@mediatek.com> 762306a36Sopenharmony_ci// 862306a36Sopenharmony_ci// Hardware interface for mt8186 DSP code loader 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include <sound/sof.h> 1162306a36Sopenharmony_ci#include "mt8186.h" 1262306a36Sopenharmony_ci#include "../../ops.h" 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_civoid mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr) 1562306a36Sopenharmony_ci{ 1662306a36Sopenharmony_ci /* set RUNSTALL to stop core */ 1762306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG, 1862306a36Sopenharmony_ci RUNSTALL, RUNSTALL); 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci /* enable mbox 0 & 1 IRQ */ 2162306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_MBOX_IRQ_EN, 2262306a36Sopenharmony_ci DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN, 2362306a36Sopenharmony_ci DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN); 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci /* set core boot address */ 2662306a36Sopenharmony_ci snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr); 2762306a36Sopenharmony_ci snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0); 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci /* assert core reset */ 3062306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN, 3162306a36Sopenharmony_ci SW_RSTN_C0 | SW_DBG_RSTN_C0, 3262306a36Sopenharmony_ci SW_RSTN_C0 | SW_DBG_RSTN_C0); 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci /* hardware requirement */ 3562306a36Sopenharmony_ci udelay(1); 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci /* release core reset */ 3862306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN, 3962306a36Sopenharmony_ci SW_RSTN_C0 | SW_DBG_RSTN_C0, 4062306a36Sopenharmony_ci 0); 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci /* clear RUNSTALL (bit31) to start core */ 4362306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG, 4462306a36Sopenharmony_ci RUNSTALL, 0); 4562306a36Sopenharmony_ci} 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_civoid mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev) 4862306a36Sopenharmony_ci{ 4962306a36Sopenharmony_ci /* set RUNSTALL to stop core */ 5062306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG, 5162306a36Sopenharmony_ci RUNSTALL, RUNSTALL); 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ci /* assert core reset */ 5462306a36Sopenharmony_ci snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN, 5562306a36Sopenharmony_ci SW_RSTN_C0 | SW_DBG_RSTN_C0, 5662306a36Sopenharmony_ci SW_RSTN_C0 | SW_DBG_RSTN_C0); 5762306a36Sopenharmony_ci} 5862306a36Sopenharmony_ci 59