1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2020-2022 Intel Corporation. All rights reserved. 7 */ 8 9/* HDA Registers */ 10#define MTL_PPLCLLPL_BASE 0x948 11#define MTL_PPLCLLPU_STRIDE 0x10 12#define MTL_PPLCLLPL(x) (MTL_PPLCLLPL_BASE + (x) * MTL_PPLCLLPU_STRIDE) 13#define MTL_PPLCLLPU(x) (MTL_PPLCLLPL_BASE + 0x4 + (x) * MTL_PPLCLLPU_STRIDE) 14 15/* DSP Registers */ 16#define MTL_HFDSSCS 0x1000 17#define MTL_HFDSSCS_SPA_MASK BIT(16) 18#define MTL_HFDSSCS_CPA_MASK BIT(24) 19#define MTL_HFSNDWIE 0x114C 20#define MTL_HFPWRCTL 0x1D18 21#define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8) 22#define MTL_HFPWRCTL_WPDSPHPXPG BIT(0) 23#define MTL_HFPWRSTS 0x1D1C 24#define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0) 25#define MTL_HFINTIPPTR 0x1108 26#define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0) 27#define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6) 28#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) 29 30#define MTL_HDA_VS_D0I3C 0x1D4A 31 32#define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 33#define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04 34#define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0) 35#define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8) 36#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24) 37#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24 38 39/* IPC Registers */ 40#define MTL_DSP_REG_HFIPCXTDR 0x73200 41#define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31) 42#define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0) 43#define MTL_DSP_REG_HFIPCXTDA 0x73204 44#define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31) 45#define MTL_DSP_REG_HFIPCXIDR 0x73210 46#define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31) 47#define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0) 48#define MTL_DSP_REG_HFIPCXIDA 0x73214 49#define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31) 50#define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0) 51#define MTL_DSP_REG_HFIPCXCTL 0x73228 52#define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0) 53#define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1) 54#define MTL_DSP_REG_HFIPCXTDDY 0x73300 55#define MTL_DSP_REG_HFIPCXIDDY 0x73380 56#define MTL_DSP_REG_HfHIPCIE 0x1140 57#define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0) 58#define MTL_DSP_REG_HfSNDWIE 0x114C 59#define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0) 60 61#define MTL_DSP_IRQSTS 0x20 62#define MTL_DSP_IRQSTS_IPC BIT(0) 63#define MTL_DSP_IRQSTS_SDW BIT(6) 64 65#define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */ 66 67/* Memory windows */ 68#define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x)) 69 70#define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000) 71#define MTL_DSP_MBOX_UPLINK_SIZE 0x1000 72#define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1) 73#define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000 74 75/* FW registers */ 76#define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ 77#define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ 78 79#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */ 80#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */ 81#define MTL_DSP_REG_HfIMRIS1 0x162088 82#define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) 83 84bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 85int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 86 87void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev); 88void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev); 89 90int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable); 91 92int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev); 93int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev); 94void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 95 96int mtl_power_down_dsp(struct snd_sof_dev *sdev); 97int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 98 99irqreturn_t mtl_ipc_irq_thread(int irq, void *context); 100 101int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 102int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 103 104void mtl_ipc_dump(struct snd_sof_dev *sdev); 105 106u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev, 107 struct snd_soc_component *component, 108 struct snd_pcm_substream *substream); 109