1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// This file is provided under a dual BSD/GPLv2 license. When using or 4// redistributing this file, you may do so under either license. 5// 6// Copyright(c) 2018 Intel Corporation. All rights reserved. 7// 8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10// Rander Wang <rander.wang@intel.com> 11// Keyon Jie <yang.jie@linux.intel.com> 12// 13 14/* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18#include <sound/hdaudio_ext.h> 19#include <sound/hda_register.h> 20 21#include <linux/acpi.h> 22#include <linux/module.h> 23#include <linux/soundwire/sdw.h> 24#include <linux/soundwire/sdw_intel.h> 25#include <sound/intel-dsp-config.h> 26#include <sound/intel-nhlt.h> 27#include <sound/sof.h> 28#include <sound/sof/xtensa.h> 29#include <sound/hda-mlink.h> 30#include "../sof-audio.h" 31#include "../sof-pci-dev.h" 32#include "../ops.h" 33#include "hda.h" 34 35#define CREATE_TRACE_POINTS 36#include <trace/events/sof_intel.h> 37 38#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 39#include <sound/soc-acpi-intel-match.h> 40#endif 41 42/* platform specific devices */ 43#include "shim.h" 44 45#define EXCEPT_MAX_HDR_SIZE 0x400 46#define HDA_EXT_ROM_STATUS_SIZE 8 47 48static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 49{ 50 const struct sof_intel_dsp_desc *chip; 51 u32 interface_mask[2] = { 0 }; 52 53 chip = get_chip_info(sdev->pdata); 54 switch (chip->hw_ip_version) { 55 case SOF_INTEL_TANGIER: 56 case SOF_INTEL_BAYTRAIL: 57 case SOF_INTEL_BROADWELL: 58 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); 59 break; 60 case SOF_INTEL_CAVS_1_5: 61 case SOF_INTEL_CAVS_1_5_PLUS: 62 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 63 BIT(SOF_DAI_INTEL_HDA); 64 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 65 break; 66 case SOF_INTEL_CAVS_1_8: 67 case SOF_INTEL_CAVS_2_0: 68 case SOF_INTEL_CAVS_2_5: 69 case SOF_INTEL_ACE_1_0: 70 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 71 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 72 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 73 break; 74 case SOF_INTEL_ACE_2_0: 75 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 76 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 77 interface_mask[1] = interface_mask[0]; /* all interfaces accessible without DSP */ 78 break; 79 default: 80 break; 81 } 82 83 return interface_mask[sdev->dspless_mode_selected]; 84} 85 86#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 87 88/* 89 * The default for SoundWire clock stop quirks is to power gate the IP 90 * and do a Bus Reset, this will need to be modified when the DSP 91 * needs to remain in D0i3 so that the Master does not lose context 92 * and enumeration is not required on clock restart 93 */ 94static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 95module_param(sdw_clock_stop_quirks, int, 0444); 96MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 97 98static int sdw_params_stream(struct device *dev, 99 struct sdw_intel_stream_params_data *params_data) 100{ 101 struct snd_soc_dai *d = params_data->dai; 102 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 103 struct snd_sof_dai_config_data data = { 0 }; 104 105 data.dai_index = (params_data->link_id << 8) | d->id; 106 data.dai_data = params_data->alh_stream_id; 107 108 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 109} 110 111struct sdw_intel_ops sdw_callback = { 112 .params_stream = sdw_params_stream, 113}; 114 115static int sdw_ace2x_params_stream(struct device *dev, 116 struct sdw_intel_stream_params_data *params_data) 117{ 118 return sdw_hda_dai_hw_params(params_data->substream, 119 params_data->hw_params, 120 params_data->dai, 121 params_data->link_id); 122} 123 124static int sdw_ace2x_free_stream(struct device *dev, 125 struct sdw_intel_stream_free_data *free_data) 126{ 127 return sdw_hda_dai_hw_free(free_data->substream, 128 free_data->dai, 129 free_data->link_id); 130} 131 132static int sdw_ace2x_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 133{ 134 return sdw_hda_dai_trigger(substream, cmd, dai); 135} 136 137static struct sdw_intel_ops sdw_ace2x_callback = { 138 .params_stream = sdw_ace2x_params_stream, 139 .free_stream = sdw_ace2x_free_stream, 140 .trigger = sdw_ace2x_trigger, 141}; 142 143void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 144{ 145 struct sof_intel_hda_dev *hdev; 146 147 hdev = sdev->pdata->hw_pdata; 148 149 if (!hdev->sdw) 150 return; 151 152 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 153 HDA_DSP_REG_ADSPIC2_SNDW, 154 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 155} 156 157void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 158{ 159 u32 interface_mask = hda_get_interface_mask(sdev); 160 const struct sof_intel_dsp_desc *chip; 161 162 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 163 return; 164 165 chip = get_chip_info(sdev->pdata); 166 if (chip && chip->enable_sdw_irq) 167 chip->enable_sdw_irq(sdev, enable); 168} 169 170static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 171{ 172 u32 interface_mask = hda_get_interface_mask(sdev); 173 struct sof_intel_hda_dev *hdev; 174 acpi_handle handle; 175 int ret; 176 177 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 178 return -EINVAL; 179 180 handle = ACPI_HANDLE(sdev->dev); 181 182 /* save ACPI info for the probe step */ 183 hdev = sdev->pdata->hw_pdata; 184 185 ret = sdw_intel_acpi_scan(handle, &hdev->info); 186 if (ret < 0) 187 return -EINVAL; 188 189 return 0; 190} 191 192static int hda_sdw_probe(struct snd_sof_dev *sdev) 193{ 194 const struct sof_intel_dsp_desc *chip; 195 struct sof_intel_hda_dev *hdev; 196 struct sdw_intel_res res; 197 void *sdw; 198 199 hdev = sdev->pdata->hw_pdata; 200 201 memset(&res, 0, sizeof(res)); 202 203 chip = get_chip_info(sdev->pdata); 204 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 205 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 206 res.hw_ops = &sdw_intel_cnl_hw_ops; 207 res.shim_base = hdev->desc->sdw_shim_base; 208 res.alh_base = hdev->desc->sdw_alh_base; 209 res.ext = false; 210 res.ops = &sdw_callback; 211 } else { 212 /* 213 * retrieve eml_lock needed to protect shared registers 214 * in the HDaudio multi-link areas 215 */ 216 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 217 AZX_REG_ML_LEPTR_ID_SDW); 218 if (!res.eml_lock) 219 return -ENODEV; 220 221 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 222 /* 223 * the SHIM and SoundWire register offsets are link-specific 224 * and will be determined when adding auxiliary devices 225 */ 226 res.hw_ops = &sdw_intel_lnl_hw_ops; 227 res.ext = true; 228 res.ops = &sdw_ace2x_callback; 229 230 } 231 res.irq = sdev->ipc_irq; 232 res.handle = hdev->info.handle; 233 res.parent = sdev->dev; 234 235 res.dev = sdev->dev; 236 res.clock_stop_quirks = sdw_clock_stop_quirks; 237 res.hbus = sof_to_bus(sdev); 238 239 /* 240 * ops and arg fields are not populated for now, 241 * they will be needed when the DAI callbacks are 242 * provided 243 */ 244 245 /* we could filter links here if needed, e.g for quirks */ 246 res.count = hdev->info.count; 247 res.link_mask = hdev->info.link_mask; 248 249 sdw = sdw_intel_probe(&res); 250 if (!sdw) { 251 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 252 return -EINVAL; 253 } 254 255 /* save context */ 256 hdev->sdw = sdw; 257 258 return 0; 259} 260 261int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 262{ 263 struct sof_intel_hda_dev *hdev; 264 struct sdw_intel_ctx *ctx; 265 u32 caps; 266 267 hdev = sdev->pdata->hw_pdata; 268 ctx = hdev->sdw; 269 270 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 271 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 272 273 /* Check HW supported vs property value */ 274 if (caps < ctx->count) { 275 dev_err(sdev->dev, 276 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 277 __func__, ctx->count, caps); 278 return -EINVAL; 279 } 280 281 return 0; 282} 283 284int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 285{ 286 struct sof_intel_hda_dev *hdev; 287 struct sdw_intel_ctx *ctx; 288 struct hdac_bus *bus; 289 u32 slcount; 290 291 bus = sof_to_bus(sdev); 292 293 hdev = sdev->pdata->hw_pdata; 294 ctx = hdev->sdw; 295 296 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 297 298 /* Check HW supported vs property value */ 299 if (slcount < ctx->count) { 300 dev_err(sdev->dev, 301 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 302 __func__, ctx->count, slcount); 303 return -EINVAL; 304 } 305 306 return 0; 307} 308 309static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 310{ 311 const struct sof_intel_dsp_desc *chip; 312 313 chip = get_chip_info(sdev->pdata); 314 if (chip && chip->read_sdw_lcount) 315 return chip->read_sdw_lcount(sdev); 316 317 return 0; 318} 319 320int hda_sdw_startup(struct snd_sof_dev *sdev) 321{ 322 struct sof_intel_hda_dev *hdev; 323 struct snd_sof_pdata *pdata = sdev->pdata; 324 int ret; 325 326 hdev = sdev->pdata->hw_pdata; 327 328 if (!hdev->sdw) 329 return 0; 330 331 if (pdata->machine && !pdata->machine->mach_params.link_mask) 332 return 0; 333 334 ret = hda_sdw_check_lcount(sdev); 335 if (ret < 0) 336 return ret; 337 338 return sdw_intel_startup(hdev->sdw); 339} 340 341static int hda_sdw_exit(struct snd_sof_dev *sdev) 342{ 343 struct sof_intel_hda_dev *hdev; 344 345 hdev = sdev->pdata->hw_pdata; 346 347 hda_sdw_int_enable(sdev, false); 348 349 if (hdev->sdw) 350 sdw_intel_exit(hdev->sdw); 351 hdev->sdw = NULL; 352 353 return 0; 354} 355 356bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 357{ 358 struct sof_intel_hda_dev *hdev; 359 bool ret = false; 360 u32 irq_status; 361 362 hdev = sdev->pdata->hw_pdata; 363 364 if (!hdev->sdw) 365 return ret; 366 367 /* store status */ 368 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 369 370 /* invalid message ? */ 371 if (irq_status == 0xffffffff) 372 goto out; 373 374 /* SDW message ? */ 375 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 376 ret = true; 377 378out: 379 return ret; 380} 381 382static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 383{ 384 u32 interface_mask = hda_get_interface_mask(sdev); 385 const struct sof_intel_dsp_desc *chip; 386 387 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 388 return false; 389 390 chip = get_chip_info(sdev->pdata); 391 if (chip && chip->check_sdw_irq) 392 return chip->check_sdw_irq(sdev); 393 394 return false; 395} 396 397static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 398{ 399 return sdw_intel_thread(irq, context); 400} 401 402bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 403{ 404 struct sof_intel_hda_dev *hdev; 405 406 hdev = sdev->pdata->hw_pdata; 407 if (hdev->sdw && 408 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 409 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 410 return true; 411 412 return false; 413} 414 415static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 416{ 417 u32 interface_mask = hda_get_interface_mask(sdev); 418 const struct sof_intel_dsp_desc *chip; 419 420 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 421 return false; 422 423 chip = get_chip_info(sdev->pdata); 424 if (chip && chip->check_sdw_wakeen_irq) 425 return chip->check_sdw_wakeen_irq(sdev); 426 427 return false; 428} 429 430void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 431{ 432 u32 interface_mask = hda_get_interface_mask(sdev); 433 struct sof_intel_hda_dev *hdev; 434 435 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 436 return; 437 438 hdev = sdev->pdata->hw_pdata; 439 if (!hdev->sdw) 440 return; 441 442 sdw_intel_process_wakeen_event(hdev->sdw); 443} 444 445#else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 446static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 447{ 448 return 0; 449} 450 451static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 452{ 453 return 0; 454} 455 456static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 457{ 458 return 0; 459} 460 461static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 462{ 463 return false; 464} 465 466static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 467{ 468 return IRQ_HANDLED; 469} 470 471static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 472{ 473 return false; 474} 475 476#endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 477 478/* 479 * Debug 480 */ 481 482struct hda_dsp_msg_code { 483 u32 code; 484 const char *text; 485}; 486 487#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 488static bool hda_use_msi = true; 489module_param_named(use_msi, hda_use_msi, bool, 0444); 490MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 491#else 492#define hda_use_msi (1) 493#endif 494 495int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 496module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 497MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 498 499static char *hda_model; 500module_param(hda_model, charp, 0444); 501MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 502 503static int dmic_num_override = -1; 504module_param_named(dmic_num, dmic_num_override, int, 0444); 505MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 506 507static int mclk_id_override = -1; 508module_param_named(mclk_id, mclk_id_override, int, 0444); 509MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 510 511static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 512 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 513 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 514 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 515 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 516 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 517 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 518 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 519 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 520 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 521 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 522 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 523 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 524 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 525 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 526 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 527 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 528}; 529 530#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 531static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 532 FSR_ROM_STATE_ENTRY(INIT), 533 FSR_ROM_STATE_ENTRY(INIT_DONE), 534 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 535 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 536 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 537 FSR_ROM_STATE_ENTRY(FW_ENTERED), 538 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 539 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 540 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 541 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 542 /* CSE states */ 543 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 544 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 545 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 546 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 547 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 548 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 549 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 550 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 551 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 552}; 553 554#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 555static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 556 FSR_BRINGUP_STATE_ENTRY(INIT), 557 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 558 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 559 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 560 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 561 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 562}; 563 564#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 565static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 566 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 567 FSR_WAIT_STATE_ENTRY(IPC_DONE), 568 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 569 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 570 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 571 FSR_WAIT_STATE_ENTRY(CSE_CSR), 572}; 573 574#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 575static const char * const fsr_module_names[] = { 576 FSR_MODULE_NAME_ENTRY(ROM), 577 FSR_MODULE_NAME_ENTRY(ROM_BYP), 578 FSR_MODULE_NAME_ENTRY(BASE_FW), 579 FSR_MODULE_NAME_ENTRY(LP_BOOT), 580 FSR_MODULE_NAME_ENTRY(BRNGUP), 581 FSR_MODULE_NAME_ENTRY(ROM_EXT), 582}; 583 584static const char * 585hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 586 size_t array_size) 587{ 588 int i; 589 590 for (i = 0; i < array_size; i++) { 591 if (code == msg_code[i].code) 592 return msg_code[i].text; 593 } 594 595 return NULL; 596} 597 598static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 599{ 600 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 601 const char *state_text, *error_text, *module_text; 602 u32 fsr, state, wait_state, module, error_code; 603 604 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 605 state = FSR_TO_STATE_CODE(fsr); 606 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 607 module = FSR_TO_MODULE_CODE(fsr); 608 609 if (module > FSR_MOD_ROM_EXT) 610 module_text = "unknown"; 611 else 612 module_text = fsr_module_names[module]; 613 614 if (module == FSR_MOD_BRNGUP) 615 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 616 ARRAY_SIZE(fsr_bringup_state_names)); 617 else 618 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 619 ARRAY_SIZE(fsr_rom_state_names)); 620 621 /* not for us, must be generic sof message */ 622 if (!state_text) { 623 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 624 return; 625 } 626 627 if (wait_state) { 628 const char *wait_state_text; 629 630 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 631 ARRAY_SIZE(fsr_wait_state_names)); 632 if (!wait_state_text) 633 wait_state_text = "unknown"; 634 635 dev_printk(level, sdev->dev, 636 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 637 fsr, module_text, state_text, wait_state_text, 638 fsr & FSR_HALTED ? "not running" : "running"); 639 } else { 640 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 641 fsr, module_text, state_text, 642 fsr & FSR_HALTED ? "not running" : "running"); 643 } 644 645 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 646 if (!error_code) 647 return; 648 649 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 650 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 651 if (!error_text) 652 error_text = "unknown"; 653 654 if (state == FSR_STATE_FW_ENTERED) 655 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 656 error_text); 657 else 658 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 659 error_text); 660} 661 662static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 663 struct sof_ipc_dsp_oops_xtensa *xoops, 664 struct sof_ipc_panic_info *panic_info, 665 u32 *stack, size_t stack_words) 666{ 667 u32 offset = sdev->dsp_oops_offset; 668 669 /* first read registers */ 670 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 671 672 /* note: variable AR register array is not read */ 673 674 /* then get panic info */ 675 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 676 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 677 xoops->arch_hdr.totalsize); 678 return; 679 } 680 offset += xoops->arch_hdr.totalsize; 681 sof_block_read(sdev, sdev->mmio_bar, offset, 682 panic_info, sizeof(*panic_info)); 683 684 /* then get the stack */ 685 offset += sizeof(*panic_info); 686 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 687 stack_words * sizeof(u32)); 688} 689 690/* dump the first 8 dwords representing the extended ROM status */ 691static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 692 u32 flags) 693{ 694 const struct sof_intel_dsp_desc *chip; 695 char msg[128]; 696 int len = 0; 697 u32 value; 698 int i; 699 700 chip = get_chip_info(sdev->pdata); 701 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 702 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 703 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 704 } 705 706 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 707 708} 709 710void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 711{ 712 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 713 struct sof_ipc_dsp_oops_xtensa xoops; 714 struct sof_ipc_panic_info panic_info; 715 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 716 717 /* print ROM/FW status */ 718 hda_dsp_get_state(sdev, level); 719 720 /* The firmware register dump only available with IPC3 */ 721 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 722 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 723 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 724 725 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 726 HDA_DSP_STACK_DUMP_SIZE); 727 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 728 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 729 } else { 730 hda_dsp_dump_ext_rom_status(sdev, level, flags); 731 } 732} 733 734static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 735{ 736 const struct sof_intel_dsp_desc *chip; 737 738 chip = get_chip_info(sdev->pdata); 739 if (chip && chip->check_ipc_irq) 740 return chip->check_ipc_irq(sdev); 741 742 return false; 743} 744 745void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 746{ 747 u32 adspis; 748 u32 intsts; 749 u32 intctl; 750 u32 ppsts; 751 u8 rirbsts; 752 753 /* read key IRQ stats and config registers */ 754 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 755 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 756 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 757 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 758 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 759 760 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 761 intsts, intctl, rirbsts); 762 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 763} 764 765void hda_ipc_dump(struct snd_sof_dev *sdev) 766{ 767 u32 hipcie; 768 u32 hipct; 769 u32 hipcctl; 770 771 hda_ipc_irq_dump(sdev); 772 773 /* read IPC status */ 774 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 775 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 776 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 777 778 /* dump the IPC regs */ 779 /* TODO: parse the raw msg */ 780 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 781 hipcie, hipct, hipcctl); 782} 783 784void hda_ipc4_dump(struct snd_sof_dev *sdev) 785{ 786 u32 hipci, hipcie, hipct, hipcte, hipcctl; 787 788 hda_ipc_irq_dump(sdev); 789 790 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 791 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 792 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 793 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 794 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 795 796 /* dump the IPC regs */ 797 /* TODO: parse the raw msg */ 798 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 799 hipci, hipcie, hipct, hipcte, hipcctl); 800} 801 802bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 803{ 804 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 805 const struct sof_intel_dsp_desc *chip = hda->desc; 806 u32 val; 807 808 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 809 810 return !!(val & chip->ipc_req_mask); 811} 812 813static int hda_init(struct snd_sof_dev *sdev) 814{ 815 struct hda_bus *hbus; 816 struct hdac_bus *bus; 817 struct pci_dev *pci = to_pci_dev(sdev->dev); 818 int ret; 819 820 hbus = sof_to_hbus(sdev); 821 bus = sof_to_bus(sdev); 822 823 /* HDA bus init */ 824 sof_hda_bus_init(sdev, &pci->dev); 825 826 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 827 bus->use_posbuf = 0; 828 else 829 bus->use_posbuf = 1; 830 bus->bdl_pos_adj = 0; 831 bus->sync_write = 1; 832 833 mutex_init(&hbus->prepare_mutex); 834 hbus->pci = pci; 835 hbus->mixer_assigned = -1; 836 hbus->modelname = hda_model; 837 838 /* initialise hdac bus */ 839 bus->addr = pci_resource_start(pci, 0); 840 bus->remap_addr = pci_ioremap_bar(pci, 0); 841 if (!bus->remap_addr) { 842 dev_err(bus->dev, "error: ioremap error\n"); 843 return -ENXIO; 844 } 845 846 /* HDA base */ 847 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 848 849 /* init i915 and HDMI codecs */ 850 ret = hda_codec_i915_init(sdev); 851 if (ret < 0) 852 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 853 854 /* get controller capabilities */ 855 ret = hda_dsp_ctrl_get_caps(sdev); 856 if (ret < 0) 857 dev_err(sdev->dev, "error: get caps error\n"); 858 859 return ret; 860} 861 862static int check_dmic_num(struct snd_sof_dev *sdev) 863{ 864 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 865 struct nhlt_acpi_table *nhlt; 866 int dmic_num = 0; 867 868 nhlt = hdev->nhlt; 869 if (nhlt) 870 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 871 872 /* allow for module parameter override */ 873 if (dmic_num_override != -1) { 874 dev_dbg(sdev->dev, 875 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 876 dmic_num, dmic_num_override); 877 dmic_num = dmic_num_override; 878 } 879 880 if (dmic_num < 0 || dmic_num > 4) { 881 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 882 dmic_num = 0; 883 } 884 885 return dmic_num; 886} 887 888static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 889{ 890 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 891 struct nhlt_acpi_table *nhlt; 892 int ssp_mask = 0; 893 894 nhlt = hdev->nhlt; 895 if (!nhlt) 896 return ssp_mask; 897 898 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 899 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 900 if (ssp_mask) 901 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 902 } 903 904 return ssp_mask; 905} 906 907static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 908{ 909 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 910 struct nhlt_acpi_table *nhlt; 911 912 nhlt = hdev->nhlt; 913 if (!nhlt) 914 return 0; 915 916 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 917} 918 919#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 920 921static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 922 const char *sof_tplg_filename, 923 const char *idisp_str, 924 const char *dmic_str) 925{ 926 const char *tplg_filename = NULL; 927 char *filename, *tmp; 928 const char *split_ext; 929 930 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 931 if (!filename) 932 return NULL; 933 934 /* this assumes a .tplg extension */ 935 tmp = filename; 936 split_ext = strsep(&tmp, "."); 937 if (split_ext) 938 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 939 "%s%s%s.tplg", 940 split_ext, idisp_str, dmic_str); 941 kfree(filename); 942 943 return tplg_filename; 944} 945 946static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 947 const char **tplg_filename, 948 const char *idisp_str, 949 int *dmic_found, 950 bool tplg_fixup) 951{ 952 const char *dmic_str; 953 int dmic_num; 954 955 /* first check for DMICs (using NHLT or module parameter) */ 956 dmic_num = check_dmic_num(sdev); 957 958 switch (dmic_num) { 959 case 1: 960 dmic_str = "-1ch"; 961 break; 962 case 2: 963 dmic_str = "-2ch"; 964 break; 965 case 3: 966 dmic_str = "-3ch"; 967 break; 968 case 4: 969 dmic_str = "-4ch"; 970 break; 971 default: 972 dmic_num = 0; 973 dmic_str = ""; 974 break; 975 } 976 977 if (tplg_fixup) { 978 const char *default_tplg_filename = *tplg_filename; 979 const char *fixed_tplg_filename; 980 981 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 982 idisp_str, dmic_str); 983 if (!fixed_tplg_filename) 984 return -ENOMEM; 985 *tplg_filename = fixed_tplg_filename; 986 } 987 988 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 989 *dmic_found = dmic_num; 990 991 return 0; 992} 993#endif 994 995static int hda_init_caps(struct snd_sof_dev *sdev) 996{ 997 u32 interface_mask = hda_get_interface_mask(sdev); 998 struct hdac_bus *bus = sof_to_bus(sdev); 999 struct snd_sof_pdata *pdata = sdev->pdata; 1000 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 1001 u32 link_mask; 1002 int ret = 0; 1003 1004 /* check if dsp is there */ 1005 if (bus->ppcap) 1006 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 1007 1008 /* Init HDA controller after i915 init */ 1009 ret = hda_dsp_ctrl_init_chip(sdev); 1010 if (ret < 0) { 1011 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 1012 ret); 1013 return ret; 1014 } 1015 1016 hda_bus_ml_init(bus); 1017 1018 /* Skip SoundWire if it is not supported */ 1019 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1020 goto skip_soundwire; 1021 1022 /* scan SoundWire capabilities exposed by DSDT */ 1023 ret = hda_sdw_acpi_scan(sdev); 1024 if (ret < 0) { 1025 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 1026 goto skip_soundwire; 1027 } 1028 1029 link_mask = hdev->info.link_mask; 1030 if (!link_mask) { 1031 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 1032 goto skip_soundwire; 1033 } 1034 1035 /* 1036 * probe/allocate SoundWire resources. 1037 * The hardware configuration takes place in hda_sdw_startup 1038 * after power rails are enabled. 1039 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 1040 * devices, so we allocate the resources in all cases. 1041 */ 1042 ret = hda_sdw_probe(sdev); 1043 if (ret < 0) { 1044 dev_err(sdev->dev, "error: SoundWire probe error\n"); 1045 return ret; 1046 } 1047 1048skip_soundwire: 1049 1050 /* create codec instances */ 1051 hda_codec_probe_bus(sdev); 1052 1053 if (!HDA_IDISP_CODEC(bus->codec_mask)) 1054 hda_codec_i915_display_power(sdev, false); 1055 1056 hda_bus_ml_put_all(bus); 1057 1058 return 0; 1059} 1060 1061static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 1062{ 1063 struct snd_sof_dev *sdev = context; 1064 1065 /* 1066 * Get global interrupt status. It includes all hardware interrupt 1067 * sources in the Intel HD Audio controller. 1068 */ 1069 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1070 SOF_HDA_INTSTS_GIS) { 1071 1072 /* disable GIE interrupt */ 1073 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1074 SOF_HDA_INTCTL, 1075 SOF_HDA_INT_GLOBAL_EN, 1076 0); 1077 1078 return IRQ_WAKE_THREAD; 1079 } 1080 1081 return IRQ_NONE; 1082} 1083 1084static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1085{ 1086 struct snd_sof_dev *sdev = context; 1087 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1088 1089 /* deal with streams and controller first */ 1090 if (hda_dsp_check_stream_irq(sdev)) { 1091 trace_sof_intel_hda_irq(sdev, "stream"); 1092 hda_dsp_stream_threaded_handler(irq, sdev); 1093 } 1094 1095 if (hda_check_ipc_irq(sdev)) { 1096 trace_sof_intel_hda_irq(sdev, "ipc"); 1097 sof_ops(sdev)->irq_thread(irq, sdev); 1098 } 1099 1100 if (hda_dsp_check_sdw_irq(sdev)) { 1101 trace_sof_intel_hda_irq(sdev, "sdw"); 1102 hda_dsp_sdw_thread(irq, hdev->sdw); 1103 } 1104 1105 if (hda_sdw_check_wakeen_irq(sdev)) { 1106 trace_sof_intel_hda_irq(sdev, "wakeen"); 1107 hda_sdw_process_wakeen(sdev); 1108 } 1109 1110 hda_codec_check_for_state_change(sdev); 1111 1112 /* enable GIE interrupt */ 1113 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1114 SOF_HDA_INTCTL, 1115 SOF_HDA_INT_GLOBAL_EN, 1116 SOF_HDA_INT_GLOBAL_EN); 1117 1118 return IRQ_HANDLED; 1119} 1120 1121int hda_dsp_probe(struct snd_sof_dev *sdev) 1122{ 1123 struct pci_dev *pci = to_pci_dev(sdev->dev); 1124 struct sof_intel_hda_dev *hdev; 1125 struct hdac_bus *bus; 1126 const struct sof_intel_dsp_desc *chip; 1127 int ret = 0; 1128 1129 if (!sdev->dspless_mode_selected) { 1130 /* 1131 * detect DSP by checking class/subclass/prog-id information 1132 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1133 * class=04 subclass 01 prog-if 00: DSP is present 1134 * (and may be required e.g. for DMIC or SSP support) 1135 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1136 */ 1137 if (pci->class == 0x040300) { 1138 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1139 return -ENODEV; 1140 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1141 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1142 pci->class); 1143 return -ENODEV; 1144 } 1145 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1146 pci->class); 1147 } 1148 1149 chip = get_chip_info(sdev->pdata); 1150 if (!chip) { 1151 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1152 pci->device); 1153 ret = -EIO; 1154 goto err; 1155 } 1156 1157 sdev->num_cores = chip->cores_num; 1158 1159 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1160 if (!hdev) 1161 return -ENOMEM; 1162 sdev->pdata->hw_pdata = hdev; 1163 hdev->desc = chip; 1164 1165 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1166 PLATFORM_DEVID_NONE, 1167 NULL, 0); 1168 if (IS_ERR(hdev->dmic_dev)) { 1169 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1170 return PTR_ERR(hdev->dmic_dev); 1171 } 1172 1173 /* 1174 * use position update IPC if either it is forced 1175 * or we don't have other choice 1176 */ 1177#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1178 hdev->no_ipc_position = 0; 1179#else 1180 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1181#endif 1182 1183 if (sdev->dspless_mode_selected) 1184 hdev->no_ipc_position = 1; 1185 1186 /* set up HDA base */ 1187 bus = sof_to_bus(sdev); 1188 ret = hda_init(sdev); 1189 if (ret < 0) 1190 goto hdac_bus_unmap; 1191 1192 if (sdev->dspless_mode_selected) 1193 goto skip_dsp_setup; 1194 1195 /* DSP base */ 1196 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1197 if (!sdev->bar[HDA_DSP_BAR]) { 1198 dev_err(sdev->dev, "error: ioremap error\n"); 1199 ret = -ENXIO; 1200 goto hdac_bus_unmap; 1201 } 1202 1203 sdev->mmio_bar = HDA_DSP_BAR; 1204 sdev->mailbox_bar = HDA_DSP_BAR; 1205skip_dsp_setup: 1206 1207 /* allow 64bit DMA address if supported by H/W */ 1208 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1209 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1210 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1211 } 1212 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1213 1214 /* init streams */ 1215 ret = hda_dsp_stream_init(sdev); 1216 if (ret < 0) { 1217 dev_err(sdev->dev, "error: failed to init streams\n"); 1218 /* 1219 * not all errors are due to memory issues, but trying 1220 * to free everything does not harm 1221 */ 1222 goto free_streams; 1223 } 1224 1225 /* 1226 * register our IRQ 1227 * let's try to enable msi firstly 1228 * if it fails, use legacy interrupt mode 1229 * TODO: support msi multiple vectors 1230 */ 1231 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1232 dev_info(sdev->dev, "use msi interrupt mode\n"); 1233 sdev->ipc_irq = pci_irq_vector(pci, 0); 1234 /* initialised to "false" by kzalloc() */ 1235 sdev->msi_enabled = true; 1236 } 1237 1238 if (!sdev->msi_enabled) { 1239 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1240 /* 1241 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1242 * irq number of pci->irq 1243 */ 1244 sdev->ipc_irq = pci->irq; 1245 } 1246 1247 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1248 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1249 hda_dsp_interrupt_thread, 1250 IRQF_SHARED, "AudioDSP", sdev); 1251 if (ret < 0) { 1252 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1253 sdev->ipc_irq); 1254 goto free_irq_vector; 1255 } 1256 1257 pci_set_master(pci); 1258 synchronize_irq(pci->irq); 1259 1260 /* 1261 * clear TCSEL to clear playback on some HD Audio 1262 * codecs. PCI TCSEL is defined in the Intel manuals. 1263 */ 1264 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1265 1266 /* init HDA capabilities */ 1267 ret = hda_init_caps(sdev); 1268 if (ret < 0) 1269 goto free_ipc_irq; 1270 1271 if (!sdev->dspless_mode_selected) { 1272 /* enable ppcap interrupt */ 1273 hda_dsp_ctrl_ppcap_enable(sdev, true); 1274 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1275 1276 /* set default mailbox offset for FW ready message */ 1277 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1278 1279 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1280 } 1281 1282 init_waitqueue_head(&hdev->waitq); 1283 1284 hdev->nhlt = intel_nhlt_init(sdev->dev); 1285 1286 return 0; 1287 1288free_ipc_irq: 1289 free_irq(sdev->ipc_irq, sdev); 1290free_irq_vector: 1291 if (sdev->msi_enabled) 1292 pci_free_irq_vectors(pci); 1293free_streams: 1294 hda_dsp_stream_free(sdev); 1295/* dsp_unmap: not currently used */ 1296 if (!sdev->dspless_mode_selected) 1297 iounmap(sdev->bar[HDA_DSP_BAR]); 1298hdac_bus_unmap: 1299 platform_device_unregister(hdev->dmic_dev); 1300 iounmap(bus->remap_addr); 1301 hda_codec_i915_exit(sdev); 1302err: 1303 return ret; 1304} 1305 1306int hda_dsp_remove(struct snd_sof_dev *sdev) 1307{ 1308 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1309 const struct sof_intel_dsp_desc *chip = hda->desc; 1310 struct hdac_bus *bus = sof_to_bus(sdev); 1311 struct pci_dev *pci = to_pci_dev(sdev->dev); 1312 struct nhlt_acpi_table *nhlt = hda->nhlt; 1313 1314 if (nhlt) 1315 intel_nhlt_free(nhlt); 1316 1317 if (!sdev->dspless_mode_selected) 1318 /* cancel any attempt for DSP D0I3 */ 1319 cancel_delayed_work_sync(&hda->d0i3_work); 1320 1321 hda_codec_device_remove(sdev); 1322 1323 hda_sdw_exit(sdev); 1324 1325 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1326 platform_device_unregister(hda->dmic_dev); 1327 1328 if (!sdev->dspless_mode_selected) { 1329 /* disable DSP IRQ */ 1330 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1331 SOF_HDA_PPCTL_PIE, 0); 1332 } 1333 1334 /* disable CIE and GIE interrupts */ 1335 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1336 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1337 1338 if (sdev->dspless_mode_selected) 1339 goto skip_disable_dsp; 1340 1341 /* no need to check for error as the DSP will be disabled anyway */ 1342 if (chip && chip->power_down_dsp) 1343 chip->power_down_dsp(sdev); 1344 1345 /* disable DSP */ 1346 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1347 SOF_HDA_PPCTL_GPROCEN, 0); 1348 1349skip_disable_dsp: 1350 free_irq(sdev->ipc_irq, sdev); 1351 if (sdev->msi_enabled) 1352 pci_free_irq_vectors(pci); 1353 1354 hda_dsp_stream_free(sdev); 1355 1356 hda_bus_ml_free(sof_to_bus(sdev)); 1357 1358 if (!sdev->dspless_mode_selected) 1359 iounmap(sdev->bar[HDA_DSP_BAR]); 1360 1361 iounmap(bus->remap_addr); 1362 1363 sof_hda_bus_exit(sdev); 1364 1365 hda_codec_i915_exit(sdev); 1366 1367 return 0; 1368} 1369 1370int hda_power_down_dsp(struct snd_sof_dev *sdev) 1371{ 1372 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1373 const struct sof_intel_dsp_desc *chip = hda->desc; 1374 1375 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1376} 1377 1378#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1379static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1380 struct snd_soc_acpi_mach **mach) 1381{ 1382 struct hdac_bus *bus = sof_to_bus(sdev); 1383 struct snd_soc_acpi_mach_params *mach_params; 1384 struct snd_soc_acpi_mach *hda_mach; 1385 struct snd_sof_pdata *pdata = sdev->pdata; 1386 const char *tplg_filename; 1387 const char *idisp_str; 1388 int dmic_num = 0; 1389 int codec_num = 0; 1390 int ret; 1391 int i; 1392 1393 /* codec detection */ 1394 if (!bus->codec_mask) { 1395 dev_info(bus->dev, "no hda codecs found!\n"); 1396 } else { 1397 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1398 bus->codec_mask); 1399 1400 for (i = 0; i < HDA_MAX_CODECS; i++) { 1401 if (bus->codec_mask & (1 << i)) 1402 codec_num++; 1403 } 1404 1405 /* 1406 * If no machine driver is found, then: 1407 * 1408 * generic hda machine driver can handle: 1409 * - one HDMI codec, and/or 1410 * - one external HDAudio codec 1411 */ 1412 if (!*mach && codec_num <= 2) { 1413 bool tplg_fixup; 1414 1415 hda_mach = snd_soc_acpi_intel_hda_machines; 1416 1417 dev_info(bus->dev, "using HDA machine driver %s now\n", 1418 hda_mach->drv_name); 1419 1420 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1421 idisp_str = "-idisp"; 1422 else 1423 idisp_str = ""; 1424 1425 /* topology: use the info from hda_machines */ 1426 if (pdata->tplg_filename) { 1427 tplg_fixup = false; 1428 tplg_filename = pdata->tplg_filename; 1429 } else { 1430 tplg_fixup = true; 1431 tplg_filename = hda_mach->sof_tplg_filename; 1432 } 1433 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1434 tplg_fixup); 1435 if (ret < 0) 1436 return; 1437 1438 hda_mach->mach_params.dmic_num = dmic_num; 1439 pdata->tplg_filename = tplg_filename; 1440 1441 if (codec_num == 2 || 1442 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1443 /* 1444 * Prevent SoundWire links from starting when an external 1445 * HDaudio codec is used 1446 */ 1447 hda_mach->mach_params.link_mask = 0; 1448 } else { 1449 /* 1450 * Allow SoundWire links to start when no external HDaudio codec 1451 * was detected. This will not create a SoundWire card but 1452 * will help detect if any SoundWire codec reports as ATTACHED. 1453 */ 1454 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1455 1456 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1457 } 1458 1459 *mach = hda_mach; 1460 } 1461 } 1462 1463 /* used by hda machine driver to create dai links */ 1464 if (*mach) { 1465 mach_params = &(*mach)->mach_params; 1466 mach_params->codec_mask = bus->codec_mask; 1467 mach_params->common_hdmi_codec_drv = true; 1468 } 1469} 1470#else 1471static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1472 struct snd_soc_acpi_mach **mach) 1473{ 1474} 1475#endif 1476 1477#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1478 1479static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1480{ 1481 struct snd_sof_pdata *pdata = sdev->pdata; 1482 const struct snd_soc_acpi_link_adr *link; 1483 struct snd_soc_acpi_mach *mach; 1484 struct sof_intel_hda_dev *hdev; 1485 u32 link_mask; 1486 int i; 1487 1488 hdev = pdata->hw_pdata; 1489 link_mask = hdev->info.link_mask; 1490 1491 /* 1492 * Select SoundWire machine driver if needed using the 1493 * alternate tables. This case deals with SoundWire-only 1494 * machines, for mixed cases with I2C/I2S the detection relies 1495 * on the HID list. 1496 */ 1497 if (link_mask) { 1498 for (mach = pdata->desc->alt_machines; 1499 mach && mach->link_mask; mach++) { 1500 /* 1501 * On some platforms such as Up Extreme all links 1502 * are enabled but only one link can be used by 1503 * external codec. Instead of exact match of two masks, 1504 * first check whether link_mask of mach is subset of 1505 * link_mask supported by hw and then go on searching 1506 * link_adr 1507 */ 1508 if (~link_mask & mach->link_mask) 1509 continue; 1510 1511 /* No need to match adr if there is no links defined */ 1512 if (!mach->links) 1513 break; 1514 1515 link = mach->links; 1516 for (i = 0; i < hdev->info.count && link->num_adr; 1517 i++, link++) { 1518 /* 1519 * Try next machine if any expected Slaves 1520 * are not found on this link. 1521 */ 1522 if (!snd_soc_acpi_sdw_link_slaves_found(sdev->dev, link, 1523 hdev->sdw->ids, 1524 hdev->sdw->num_slaves)) 1525 break; 1526 } 1527 /* Found if all Slaves are checked */ 1528 if (i == hdev->info.count || !link->num_adr) 1529 break; 1530 } 1531 if (mach && mach->link_mask) { 1532 int dmic_num = 0; 1533 bool tplg_fixup; 1534 const char *tplg_filename; 1535 1536 mach->mach_params.links = mach->links; 1537 mach->mach_params.link_mask = mach->link_mask; 1538 mach->mach_params.platform = dev_name(sdev->dev); 1539 1540 if (pdata->tplg_filename) { 1541 tplg_fixup = false; 1542 } else { 1543 tplg_fixup = true; 1544 tplg_filename = mach->sof_tplg_filename; 1545 } 1546 1547 /* 1548 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1549 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1550 * if all conditions are true: 1551 * a) 2 or fewer links are used by SoundWire 1552 * b) the NHLT table reports the presence of microphones 1553 */ 1554 if (hweight_long(mach->link_mask) <= 2) { 1555 int ret; 1556 1557 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1558 &dmic_num, tplg_fixup); 1559 if (ret < 0) 1560 return NULL; 1561 } 1562 if (tplg_fixup) 1563 pdata->tplg_filename = tplg_filename; 1564 mach->mach_params.dmic_num = dmic_num; 1565 1566 dev_dbg(sdev->dev, 1567 "SoundWire machine driver %s topology %s\n", 1568 mach->drv_name, 1569 pdata->tplg_filename); 1570 1571 return mach; 1572 } 1573 1574 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1575 } 1576 1577 return NULL; 1578} 1579#else 1580static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1581{ 1582 return NULL; 1583} 1584#endif 1585 1586void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1587 struct snd_sof_dev *sdev) 1588{ 1589 struct snd_sof_pdata *pdata = sdev->pdata; 1590 const struct sof_dev_desc *desc = pdata->desc; 1591 struct snd_soc_acpi_mach_params *mach_params; 1592 1593 mach_params = &mach->mach_params; 1594 mach_params->platform = dev_name(sdev->dev); 1595 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1596 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1597 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1598 else 1599 mach_params->num_dai_drivers = desc->ops->num_drv; 1600 mach_params->dai_drivers = desc->ops->drv; 1601} 1602 1603struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1604{ 1605 u32 interface_mask = hda_get_interface_mask(sdev); 1606 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1607 const struct sof_dev_desc *desc = sof_pdata->desc; 1608 struct snd_soc_acpi_mach *mach = NULL; 1609 const char *tplg_filename; 1610 1611 /* Try I2S or DMIC if it is supported */ 1612 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1613 mach = snd_soc_acpi_find_machine(desc->machines); 1614 1615 if (mach) { 1616 bool add_extension = false; 1617 bool tplg_fixup = false; 1618 1619 /* 1620 * If tplg file name is overridden, use it instead of 1621 * the one set in mach table 1622 */ 1623 if (!sof_pdata->tplg_filename) { 1624 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1625 tplg_fixup = true; 1626 } 1627 1628 /* report to machine driver if any DMICs are found */ 1629 mach->mach_params.dmic_num = check_dmic_num(sdev); 1630 1631 if (tplg_fixup && 1632 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1633 mach->mach_params.dmic_num) { 1634 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1635 "%s%s%d%s", 1636 sof_pdata->tplg_filename, 1637 "-dmic", 1638 mach->mach_params.dmic_num, 1639 "ch"); 1640 if (!tplg_filename) 1641 return NULL; 1642 1643 sof_pdata->tplg_filename = tplg_filename; 1644 add_extension = true; 1645 } 1646 1647 if (mach->link_mask) { 1648 mach->mach_params.links = mach->links; 1649 mach->mach_params.link_mask = mach->link_mask; 1650 } 1651 1652 /* report SSP link mask to machine driver */ 1653 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1654 1655 if (tplg_fixup && 1656 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1657 mach->mach_params.i2s_link_mask) { 1658 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1659 int ssp_num; 1660 int mclk_mask; 1661 1662 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1663 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1664 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1665 1666 /* fls returns 1-based results, SSPs indices are 0-based */ 1667 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1668 1669 if (ssp_num >= chip->ssp_count) { 1670 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1671 ssp_num, chip->ssp_count); 1672 return NULL; 1673 } 1674 1675 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1676 "%s%s%d", 1677 sof_pdata->tplg_filename, 1678 "-ssp", 1679 ssp_num); 1680 if (!tplg_filename) 1681 return NULL; 1682 1683 sof_pdata->tplg_filename = tplg_filename; 1684 add_extension = true; 1685 1686 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1687 1688 if (mclk_mask < 0) { 1689 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1690 return NULL; 1691 } 1692 1693 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1694 1695 if (mclk_mask) { 1696 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1697 sdev->mclk_id_override = true; 1698 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1699 } 1700 } 1701 1702 if (tplg_fixup && add_extension) { 1703 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1704 "%s%s", 1705 sof_pdata->tplg_filename, 1706 ".tplg"); 1707 if (!tplg_filename) 1708 return NULL; 1709 1710 sof_pdata->tplg_filename = tplg_filename; 1711 } 1712 1713 /* check if mclk_id should be modified from topology defaults */ 1714 if (mclk_id_override >= 0) { 1715 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1716 sdev->mclk_id_override = true; 1717 sdev->mclk_id_quirk = mclk_id_override; 1718 } 1719 } 1720 1721 /* If I2S fails, try SoundWire if it is supported */ 1722 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1723 mach = hda_sdw_machine_select(sdev); 1724 1725 /* 1726 * Choose HDA generic machine driver if mach is NULL. 1727 * Otherwise, set certain mach params. 1728 */ 1729 hda_generic_machine_select(sdev, &mach); 1730 if (!mach) 1731 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1732 1733 return mach; 1734} 1735 1736int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1737{ 1738 int ret; 1739 1740 ret = snd_intel_dsp_driver_probe(pci); 1741 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1742 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1743 return -ENODEV; 1744 } 1745 1746 return sof_pci_probe(pci, pci_id); 1747} 1748EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1749 1750int hda_register_clients(struct snd_sof_dev *sdev) 1751{ 1752 return hda_probes_register(sdev); 1753} 1754 1755void hda_unregister_clients(struct snd_sof_dev *sdev) 1756{ 1757 hda_probes_unregister(sdev); 1758} 1759 1760MODULE_LICENSE("Dual BSD/GPL"); 1761MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1762MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1763MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1764MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1765MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1766MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1767MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1768MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1769