162306a36Sopenharmony_ci/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * This file is provided under a dual BSD/GPLv2 license. When using or 462306a36Sopenharmony_ci * redistributing this file, you may do so under either license. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * Copyright(c) 2017-2021 Intel Corporation. All rights reserved. 762306a36Sopenharmony_ci * 862306a36Sopenharmony_ci * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 962306a36Sopenharmony_ci */ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#ifndef __SOF_INTEL_ATOM_H 1262306a36Sopenharmony_ci#define __SOF_INTEL_ATOM_H 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* DSP memories */ 1562306a36Sopenharmony_ci#define IRAM_OFFSET 0x0C0000 1662306a36Sopenharmony_ci#define IRAM_SIZE (80 * 1024) 1762306a36Sopenharmony_ci#define DRAM_OFFSET 0x100000 1862306a36Sopenharmony_ci#define DRAM_SIZE (160 * 1024) 1962306a36Sopenharmony_ci#define SHIM_OFFSET 0x140000 2062306a36Sopenharmony_ci#define SHIM_SIZE_BYT 0x100 2162306a36Sopenharmony_ci#define SHIM_SIZE_CHT 0x118 2262306a36Sopenharmony_ci#define MBOX_OFFSET 0x144000 2362306a36Sopenharmony_ci#define MBOX_SIZE 0x1000 2462306a36Sopenharmony_ci#define EXCEPT_OFFSET 0x800 2562306a36Sopenharmony_ci#define EXCEPT_MAX_HDR_SIZE 0x400 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci/* DSP peripherals */ 2862306a36Sopenharmony_ci#define DMAC0_OFFSET 0x098000 2962306a36Sopenharmony_ci#define DMAC1_OFFSET 0x09c000 3062306a36Sopenharmony_ci#define DMAC2_OFFSET 0x094000 3162306a36Sopenharmony_ci#define DMAC_SIZE 0x420 3262306a36Sopenharmony_ci#define SSP0_OFFSET 0x0a0000 3362306a36Sopenharmony_ci#define SSP1_OFFSET 0x0a1000 3462306a36Sopenharmony_ci#define SSP2_OFFSET 0x0a2000 3562306a36Sopenharmony_ci#define SSP3_OFFSET 0x0a4000 3662306a36Sopenharmony_ci#define SSP4_OFFSET 0x0a5000 3762306a36Sopenharmony_ci#define SSP5_OFFSET 0x0a6000 3862306a36Sopenharmony_ci#define SSP_SIZE 0x100 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci#define STACK_DUMP_SIZE 32 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci#define PCI_BAR_SIZE 0x200000 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* 4762306a36Sopenharmony_ci * Debug 4862306a36Sopenharmony_ci */ 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci#define MBOX_DUMP_SIZE 0x30 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci/* BARs */ 5362306a36Sopenharmony_ci#define DSP_BAR 0 5462306a36Sopenharmony_ci#define PCI_BAR 1 5562306a36Sopenharmony_ci#define IMR_BAR 2 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciirqreturn_t atom_irq_handler(int irq, void *context); 5862306a36Sopenharmony_ciirqreturn_t atom_irq_thread(int irq, void *context); 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ciint atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 6162306a36Sopenharmony_ciint atom_get_mailbox_offset(struct snd_sof_dev *sdev); 6262306a36Sopenharmony_ciint atom_get_window_offset(struct snd_sof_dev *sdev, u32 id); 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ciint atom_run(struct snd_sof_dev *sdev); 6562306a36Sopenharmony_ciint atom_reset(struct snd_sof_dev *sdev); 6662306a36Sopenharmony_civoid atom_dump(struct snd_sof_dev *sdev, u32 flags); 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_cistruct snd_soc_acpi_mach *atom_machine_select(struct snd_sof_dev *sdev); 6962306a36Sopenharmony_civoid atom_set_mach_params(struct snd_soc_acpi_mach *mach, 7062306a36Sopenharmony_ci struct snd_sof_dev *sdev); 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ciextern struct snd_soc_dai_driver atom_dai[]; 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci#endif 75