1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11#ifndef _ACP_DSP_IP_OFFSET_H 12#define _ACP_DSP_IP_OFFSET_H 13 14/* Registers from ACP_DMA_0 block */ 15#define ACP_DMA_CNTL_0 0x00 16#define ACP_DMA_DSCR_STRT_IDX_0 0x20 17#define ACP_DMA_DSCR_CNT_0 0x40 18#define ACP_DMA_PRIO_0 0x60 19#define ACP_DMA_CUR_DSCR_0 0x80 20#define ACP_DMA_ERR_STS_0 0xC0 21#define ACP_DMA_DESC_BASE_ADDR 0xE0 22#define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4 23#define ACP_DMA_CH_STS 0xE8 24#define ACP_DMA_CH_GROUP 0xEC 25#define ACP_DMA_CH_RST_STS 0xF0 26 27/* Registers from ACP_DSP_0 block */ 28#define ACP_DSP0_RUNSTALL 0x414 29 30/* Registers from ACP_AXI2AXIATU block */ 31#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00 32#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04 33#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08 34#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C 35#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC10 36#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC14 37#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC18 38#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C 39#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 40#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 41#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC28 42#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C 43#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC30 44#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC34 45#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC38 46#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C 47#define ACPAXI2AXI_ATU_CTRL 0xC40 48#define ACP_SOFT_RESET 0x1000 49#define ACP_CONTROL 0x1004 50 51#define ACP3X_I2S_PIN_CONFIG 0x1400 52#define ACP5X_I2S_PIN_CONFIG 0x1400 53#define ACP6X_I2S_PIN_CONFIG 0x1440 54 55/* Registers offsets from ACP_PGFSM block */ 56#define ACP3X_PGFSM_BASE 0x141C 57#define ACP5X_PGFSM_BASE 0x1424 58#define ACP6X_PGFSM_BASE 0x1024 59#define PGFSM_CONTROL_OFFSET 0x0 60#define PGFSM_STATUS_OFFSET 0x4 61#define ACP3X_CLKMUX_SEL 0x1424 62#define ACP5X_CLKMUX_SEL 0x142C 63#define ACP6X_CLKMUX_SEL 0x102C 64 65/* Registers from ACP_INTR block */ 66#define ACP3X_EXT_INTR_STAT 0x1808 67#define ACP5X_EXT_INTR_STAT 0x1808 68#define ACP6X_EXT_INTR_STAT 0x1A0C 69 70#define ACP3X_DSP_SW_INTR_BASE 0x1814 71#define ACP5X_DSP_SW_INTR_BASE 0x1814 72#define ACP6X_DSP_SW_INTR_BASE 0x1808 73#define DSP_SW_INTR_CNTL_OFFSET 0x0 74#define DSP_SW_INTR_STAT_OFFSET 0x4 75#define DSP_SW_INTR_TRIG_OFFSET 0x8 76#define ACP_ERROR_STATUS 0x18C4 77#define ACP3X_AXI2DAGB_SEM_0 0x1880 78#define ACP5X_AXI2DAGB_SEM_0 0x1884 79#define ACP6X_AXI2DAGB_SEM_0 0x1874 80 81/* Registers from ACP_SHA block */ 82#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70 83#define ACP_SHA_DMA_CMD 0x1CB0 84#define ACP_SHA_MSG_LENGTH 0x1CB4 85#define ACP_SHA_DMA_STRT_ADDR 0x1CB8 86#define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC 87#define ACP_SHA_DMA_CMD_STS 0x1CC0 88#define ACP_SHA_DMA_ERR_STATUS 0x1CC4 89#define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8 90#define ACP_SHA_DMA_INCLUDE_HDR 0x1CCC 91#define ACP_SHA_PSP_ACK 0x1C74 92 93#define ACP_SCRATCH_REG_0 0x10000 94#define ACP6X_DSP_FUSION_RUNSTALL 0x0644 95 96/* Cache window registers */ 97#define ACP_DSP0_CACHE_OFFSET0 0x0420 98#define ACP_DSP0_CACHE_SIZE0 0x0424 99#endif 100