1// SPDX-License-Identifier: GPL-2.0-only 2// ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver 3 4// Copyright (c) 2018 Rockchip Electronics Co. Ltd. 5// Author: Sugar Zhang <sugar.zhang@rock-chips.com> 6// Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 7 8#include <linux/clk.h> 9#include <linux/clk-provider.h> 10#include <linux/delay.h> 11#include <linux/mfd/syscon.h> 12#include <linux/module.h> 13#include <linux/of_address.h> 14#include <linux/of_device.h> 15#include <linux/of_gpio.h> 16#include <linux/pm_runtime.h> 17#include <linux/regmap.h> 18#include <linux/reset.h> 19#include <linux/spinlock.h> 20#include <sound/dmaengine_pcm.h> 21#include <sound/pcm_params.h> 22 23#include "rockchip_i2s_tdm.h" 24 25#define DRV_NAME "rockchip-i2s-tdm" 26 27#define DEFAULT_MCLK_FS 256 28#define CH_GRP_MAX 4 /* The max channel 8 / 2 */ 29#define MULTIPLEX_CH_MAX 10 30 31#define TRCM_TXRX 0 32#define TRCM_TX 1 33#define TRCM_RX 2 34 35struct txrx_config { 36 u32 addr; 37 u32 reg; 38 u32 txonly; 39 u32 rxonly; 40}; 41 42struct rk_i2s_soc_data { 43 u32 softrst_offset; 44 u32 grf_reg_offset; 45 u32 grf_shift; 46 int config_count; 47 const struct txrx_config *configs; 48 int (*init)(struct device *dev, u32 addr); 49}; 50 51struct rk_i2s_tdm_dev { 52 struct device *dev; 53 struct clk *hclk; 54 struct clk *mclk_tx; 55 struct clk *mclk_rx; 56 struct regmap *regmap; 57 struct regmap *grf; 58 struct snd_dmaengine_dai_dma_data capture_dma_data; 59 struct snd_dmaengine_dai_dma_data playback_dma_data; 60 struct reset_control *tx_reset; 61 struct reset_control *rx_reset; 62 struct rk_i2s_soc_data *soc_data; 63 bool is_master_mode; 64 bool io_multiplex; 65 bool tdm_mode; 66 unsigned int frame_width; 67 unsigned int clk_trcm; 68 unsigned int i2s_sdis[CH_GRP_MAX]; 69 unsigned int i2s_sdos[CH_GRP_MAX]; 70 int refcount; 71 spinlock_t lock; /* xfer lock */ 72 bool has_playback; 73 bool has_capture; 74 struct snd_soc_dai_driver *dai; 75}; 76 77static int to_ch_num(unsigned int val) 78{ 79 switch (val) { 80 case I2S_CHN_4: 81 return 4; 82 case I2S_CHN_6: 83 return 6; 84 case I2S_CHN_8: 85 return 8; 86 default: 87 return 2; 88 } 89} 90 91static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 92{ 93 clk_disable_unprepare(i2s_tdm->mclk_tx); 94 clk_disable_unprepare(i2s_tdm->mclk_rx); 95} 96 97/** 98 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on 99 * failure. 100 * @i2s_tdm: rk_i2s_tdm_dev struct 101 * 102 * This function attempts to enable all mclk clocks, but cleans up after 103 * itself on failure. Guarantees to balance its calls. 104 * 105 * Returns success (0) or negative errno. 106 */ 107static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 108{ 109 int ret = 0; 110 111 ret = clk_prepare_enable(i2s_tdm->mclk_tx); 112 if (ret) 113 goto err_mclk_tx; 114 ret = clk_prepare_enable(i2s_tdm->mclk_rx); 115 if (ret) 116 goto err_mclk_rx; 117 118 return 0; 119 120err_mclk_rx: 121 clk_disable_unprepare(i2s_tdm->mclk_tx); 122err_mclk_tx: 123 return ret; 124} 125 126static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev) 127{ 128 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 129 130 regcache_cache_only(i2s_tdm->regmap, true); 131 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 132 133 clk_disable_unprepare(i2s_tdm->hclk); 134 135 return 0; 136} 137 138static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev) 139{ 140 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 141 int ret; 142 143 ret = clk_prepare_enable(i2s_tdm->hclk); 144 if (ret) 145 goto err_hclk; 146 147 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 148 if (ret) 149 goto err_mclk; 150 151 regcache_cache_only(i2s_tdm->regmap, false); 152 regcache_mark_dirty(i2s_tdm->regmap); 153 154 ret = regcache_sync(i2s_tdm->regmap); 155 if (ret) 156 goto err_regcache; 157 158 return 0; 159 160err_regcache: 161 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 162err_mclk: 163 clk_disable_unprepare(i2s_tdm->hclk); 164err_hclk: 165 return ret; 166} 167 168static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai) 169{ 170 return snd_soc_dai_get_drvdata(dai); 171} 172 173/* 174 * Makes sure that both tx and rx are reset at the same time to sync lrck 175 * when clk_trcm > 0. 176 */ 177static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm) 178{ 179 /* This is technically race-y. 180 * 181 * In an ideal world, we could atomically assert both resets at the 182 * same time, through an atomic bulk reset API. This API however does 183 * not exist, so what the downstream vendor code used to do was 184 * implement half a reset controller here and require the CRU to be 185 * passed to the driver as a device tree node. Violating abstractions 186 * like that is bad, especially when it influences something like the 187 * bindings which are supposed to describe the hardware, not whatever 188 * workarounds the driver needs, so it was dropped. 189 * 190 * In practice, asserting the resets one by one appears to work just 191 * fine for playback. During duplex (playback + capture) operation, 192 * this might become an issue, but that should be solved by the 193 * implementation of the aforementioned API, not by shoving a reset 194 * controller into an audio driver. 195 */ 196 197 reset_control_assert(i2s_tdm->tx_reset); 198 reset_control_assert(i2s_tdm->rx_reset); 199 udelay(10); 200 reset_control_deassert(i2s_tdm->tx_reset); 201 reset_control_deassert(i2s_tdm->rx_reset); 202 udelay(10); 203} 204 205static void rockchip_snd_reset(struct reset_control *rc) 206{ 207 reset_control_assert(rc); 208 udelay(10); 209 reset_control_deassert(rc); 210 udelay(10); 211} 212 213static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm, 214 unsigned int clr) 215{ 216 unsigned int xfer_mask = 0; 217 unsigned int xfer_val = 0; 218 unsigned int val; 219 int retry = 10; 220 bool tx = clr & I2S_CLR_TXC; 221 bool rx = clr & I2S_CLR_RXC; 222 223 if (!(rx || tx)) 224 return; 225 226 if (tx) { 227 xfer_mask = I2S_XFER_TXS_START; 228 xfer_val = I2S_XFER_TXS_STOP; 229 } 230 if (rx) { 231 xfer_mask |= I2S_XFER_RXS_START; 232 xfer_val |= I2S_XFER_RXS_STOP; 233 } 234 235 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val); 236 udelay(150); 237 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr); 238 239 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 240 /* Wait on the clear operation to finish */ 241 while (val) { 242 udelay(15); 243 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 244 retry--; 245 if (!retry) { 246 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n", 247 tx ? "tx" : "", rx ? "rx" : ""); 248 if (rx && tx) 249 rockchip_snd_xfer_sync_reset(i2s_tdm); 250 else if (tx) 251 rockchip_snd_reset(i2s_tdm->tx_reset); 252 else if (rx) 253 rockchip_snd_reset(i2s_tdm->rx_reset); 254 break; 255 } 256 } 257} 258 259static inline void rockchip_enable_tde(struct regmap *regmap) 260{ 261 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 262 I2S_DMACR_TDE_ENABLE); 263} 264 265static inline void rockchip_disable_tde(struct regmap *regmap) 266{ 267 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 268 I2S_DMACR_TDE_DISABLE); 269} 270 271static inline void rockchip_enable_rde(struct regmap *regmap) 272{ 273 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 274 I2S_DMACR_RDE_ENABLE); 275} 276 277static inline void rockchip_disable_rde(struct regmap *regmap) 278{ 279 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 280 I2S_DMACR_RDE_DISABLE); 281} 282 283/* only used when clk_trcm > 0 */ 284static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream, 285 struct snd_soc_dai *dai, int on) 286{ 287 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 288 unsigned long flags; 289 290 spin_lock_irqsave(&i2s_tdm->lock, flags); 291 if (on) { 292 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 293 rockchip_enable_tde(i2s_tdm->regmap); 294 else 295 rockchip_enable_rde(i2s_tdm->regmap); 296 297 if (++i2s_tdm->refcount == 1) { 298 rockchip_snd_xfer_sync_reset(i2s_tdm); 299 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 300 I2S_XFER_TXS_START | 301 I2S_XFER_RXS_START, 302 I2S_XFER_TXS_START | 303 I2S_XFER_RXS_START); 304 } 305 } else { 306 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 307 rockchip_disable_tde(i2s_tdm->regmap); 308 else 309 rockchip_disable_rde(i2s_tdm->regmap); 310 311 if (--i2s_tdm->refcount == 0) { 312 rockchip_snd_xfer_clear(i2s_tdm, 313 I2S_CLR_TXC | I2S_CLR_RXC); 314 } 315 } 316 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 317} 318 319static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 320{ 321 if (on) { 322 rockchip_enable_tde(i2s_tdm->regmap); 323 324 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 325 I2S_XFER_TXS_START, 326 I2S_XFER_TXS_START); 327 } else { 328 rockchip_disable_tde(i2s_tdm->regmap); 329 330 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC); 331 } 332} 333 334static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 335{ 336 if (on) { 337 rockchip_enable_rde(i2s_tdm->regmap); 338 339 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 340 I2S_XFER_RXS_START, 341 I2S_XFER_RXS_START); 342 } else { 343 rockchip_disable_rde(i2s_tdm->regmap); 344 345 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC); 346 } 347} 348 349static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai, 350 unsigned int fmt) 351{ 352 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai); 353 unsigned int mask, val, tdm_val, txcr_val, rxcr_val; 354 int ret; 355 bool is_tdm = i2s_tdm->tdm_mode; 356 357 ret = pm_runtime_resume_and_get(cpu_dai->dev); 358 if (ret < 0 && ret != -EACCES) 359 return ret; 360 361 mask = I2S_CKR_MSS_MASK; 362 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 363 case SND_SOC_DAIFMT_BP_FP: 364 val = I2S_CKR_MSS_MASTER; 365 i2s_tdm->is_master_mode = true; 366 break; 367 case SND_SOC_DAIFMT_BC_FC: 368 val = I2S_CKR_MSS_SLAVE; 369 i2s_tdm->is_master_mode = false; 370 break; 371 default: 372 ret = -EINVAL; 373 goto err_pm_put; 374 } 375 376 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 377 378 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 379 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 380 case SND_SOC_DAIFMT_NB_NF: 381 val = I2S_CKR_CKP_NORMAL | 382 I2S_CKR_TLP_NORMAL | 383 I2S_CKR_RLP_NORMAL; 384 break; 385 case SND_SOC_DAIFMT_NB_IF: 386 val = I2S_CKR_CKP_NORMAL | 387 I2S_CKR_TLP_INVERTED | 388 I2S_CKR_RLP_INVERTED; 389 break; 390 case SND_SOC_DAIFMT_IB_NF: 391 val = I2S_CKR_CKP_INVERTED | 392 I2S_CKR_TLP_NORMAL | 393 I2S_CKR_RLP_NORMAL; 394 break; 395 case SND_SOC_DAIFMT_IB_IF: 396 val = I2S_CKR_CKP_INVERTED | 397 I2S_CKR_TLP_INVERTED | 398 I2S_CKR_RLP_INVERTED; 399 break; 400 default: 401 ret = -EINVAL; 402 goto err_pm_put; 403 } 404 405 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 406 407 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 408 case SND_SOC_DAIFMT_RIGHT_J: 409 txcr_val = I2S_TXCR_IBM_RSJM; 410 rxcr_val = I2S_RXCR_IBM_RSJM; 411 break; 412 case SND_SOC_DAIFMT_LEFT_J: 413 txcr_val = I2S_TXCR_IBM_LSJM; 414 rxcr_val = I2S_RXCR_IBM_LSJM; 415 break; 416 case SND_SOC_DAIFMT_I2S: 417 txcr_val = I2S_TXCR_IBM_NORMAL; 418 rxcr_val = I2S_RXCR_IBM_NORMAL; 419 break; 420 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */ 421 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 422 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 423 break; 424 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 425 txcr_val = I2S_TXCR_TFS_PCM; 426 rxcr_val = I2S_RXCR_TFS_PCM; 427 break; 428 default: 429 ret = -EINVAL; 430 goto err_pm_put; 431 } 432 433 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 434 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val); 435 436 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 437 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val); 438 439 if (is_tdm) { 440 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 441 case SND_SOC_DAIFMT_RIGHT_J: 442 val = I2S_TXCR_TFS_TDM_I2S; 443 tdm_val = TDM_SHIFT_CTRL(2); 444 break; 445 case SND_SOC_DAIFMT_LEFT_J: 446 val = I2S_TXCR_TFS_TDM_I2S; 447 tdm_val = TDM_SHIFT_CTRL(1); 448 break; 449 case SND_SOC_DAIFMT_I2S: 450 val = I2S_TXCR_TFS_TDM_I2S; 451 tdm_val = TDM_SHIFT_CTRL(0); 452 break; 453 case SND_SOC_DAIFMT_DSP_A: 454 val = I2S_TXCR_TFS_TDM_PCM; 455 tdm_val = TDM_SHIFT_CTRL(0); 456 break; 457 case SND_SOC_DAIFMT_DSP_B: 458 val = I2S_TXCR_TFS_TDM_PCM; 459 tdm_val = TDM_SHIFT_CTRL(2); 460 break; 461 default: 462 ret = -EINVAL; 463 goto err_pm_put; 464 } 465 466 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1); 467 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME; 468 469 mask = I2S_TXCR_TFS_MASK; 470 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val); 471 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val); 472 473 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK | 474 TDM_SHIFT_CTRL_MSK; 475 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 476 mask, tdm_val); 477 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 478 mask, tdm_val); 479 } 480 481err_pm_put: 482 pm_runtime_put(cpu_dai->dev); 483 484 return ret; 485} 486 487static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream, 488 struct rk_i2s_tdm_dev *i2s_tdm) 489{ 490 int stream; 491 492 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 493 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 494 rockchip_disable_tde(i2s_tdm->regmap); 495 else 496 rockchip_disable_rde(i2s_tdm->regmap); 497 498 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC); 499} 500 501static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream, 502 struct rk_i2s_tdm_dev *i2s_tdm) 503{ 504 int stream; 505 506 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 507 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 508 rockchip_enable_tde(i2s_tdm->regmap); 509 else 510 rockchip_enable_rde(i2s_tdm->regmap); 511 512 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 513 I2S_XFER_TXS_START | 514 I2S_XFER_RXS_START, 515 I2S_XFER_TXS_START | 516 I2S_XFER_RXS_START); 517} 518 519static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture) 520{ 521 if (substream_capture) { 522 switch (ch) { 523 case I2S_CHN_4: 524 return I2S_IO_6CH_OUT_4CH_IN; 525 case I2S_CHN_6: 526 return I2S_IO_4CH_OUT_6CH_IN; 527 case I2S_CHN_8: 528 return I2S_IO_2CH_OUT_8CH_IN; 529 default: 530 return I2S_IO_8CH_OUT_2CH_IN; 531 } 532 } else { 533 switch (ch) { 534 case I2S_CHN_4: 535 return I2S_IO_4CH_OUT_6CH_IN; 536 case I2S_CHN_6: 537 return I2S_IO_6CH_OUT_4CH_IN; 538 case I2S_CHN_8: 539 return I2S_IO_8CH_OUT_2CH_IN; 540 default: 541 return I2S_IO_2CH_OUT_8CH_IN; 542 } 543 } 544} 545 546static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream, 547 struct snd_soc_dai *dai) 548{ 549 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 550 int usable_chs = MULTIPLEX_CH_MAX; 551 unsigned int val = 0; 552 553 if (!i2s_tdm->io_multiplex) 554 return 0; 555 556 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 557 dev_err(i2s_tdm->dev, 558 "io multiplex not supported for this device\n"); 559 return -EINVAL; 560 } 561 562 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 563 struct snd_pcm_str *playback_str = 564 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; 565 566 if (playback_str->substream_opened) { 567 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 568 val &= I2S_TXCR_CSR_MASK; 569 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 570 } 571 572 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 573 val &= I2S_RXCR_CSR_MASK; 574 575 if (to_ch_num(val) > usable_chs) { 576 dev_err(i2s_tdm->dev, 577 "Capture channels (%d) > usable channels (%d)\n", 578 to_ch_num(val), usable_chs); 579 return -EINVAL; 580 } 581 582 rockchip_i2s_ch_to_io(val, true); 583 } else { 584 struct snd_pcm_str *capture_str = 585 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; 586 587 if (capture_str->substream_opened) { 588 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 589 val &= I2S_RXCR_CSR_MASK; 590 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 591 } 592 593 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 594 val &= I2S_TXCR_CSR_MASK; 595 596 if (to_ch_num(val) > usable_chs) { 597 dev_err(i2s_tdm->dev, 598 "Playback channels (%d) > usable channels (%d)\n", 599 to_ch_num(val), usable_chs); 600 return -EINVAL; 601 } 602 } 603 604 val <<= i2s_tdm->soc_data->grf_shift; 605 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16; 606 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val); 607 608 return 0; 609} 610 611static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream, 612 struct snd_soc_dai *dai, 613 unsigned int div_bclk, 614 unsigned int div_lrck, 615 unsigned int fmt) 616{ 617 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 618 unsigned long flags; 619 620 if (!i2s_tdm->clk_trcm) 621 return 0; 622 623 spin_lock_irqsave(&i2s_tdm->lock, flags); 624 if (i2s_tdm->refcount) 625 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm); 626 627 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 628 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK, 629 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk)); 630 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 631 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK, 632 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck)); 633 634 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 635 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 636 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 637 fmt); 638 else 639 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 640 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 641 fmt); 642 643 if (i2s_tdm->refcount) 644 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm); 645 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 646 647 return 0; 648} 649 650static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream, 651 struct snd_pcm_hw_params *params, 652 struct snd_soc_dai *dai) 653{ 654 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 655 unsigned int val = 0; 656 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64; 657 int err; 658 659 if (i2s_tdm->is_master_mode) { 660 struct clk *mclk = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 661 i2s_tdm->mclk_tx : i2s_tdm->mclk_rx; 662 663 err = clk_set_rate(mclk, DEFAULT_MCLK_FS * params_rate(params)); 664 if (err) 665 return err; 666 667 mclk_rate = clk_get_rate(mclk); 668 bclk_rate = i2s_tdm->frame_width * params_rate(params); 669 if (!bclk_rate) 670 return -EINVAL; 671 672 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 673 div_lrck = bclk_rate / params_rate(params); 674 } 675 676 switch (params_format(params)) { 677 case SNDRV_PCM_FORMAT_S8: 678 val |= I2S_TXCR_VDW(8); 679 break; 680 case SNDRV_PCM_FORMAT_S16_LE: 681 val |= I2S_TXCR_VDW(16); 682 break; 683 case SNDRV_PCM_FORMAT_S20_3LE: 684 val |= I2S_TXCR_VDW(20); 685 break; 686 case SNDRV_PCM_FORMAT_S24_LE: 687 val |= I2S_TXCR_VDW(24); 688 break; 689 case SNDRV_PCM_FORMAT_S32_LE: 690 val |= I2S_TXCR_VDW(32); 691 break; 692 default: 693 return -EINVAL; 694 } 695 696 switch (params_channels(params)) { 697 case 8: 698 val |= I2S_CHN_8; 699 break; 700 case 6: 701 val |= I2S_CHN_6; 702 break; 703 case 4: 704 val |= I2S_CHN_4; 705 break; 706 case 2: 707 val |= I2S_CHN_2; 708 break; 709 default: 710 return -EINVAL; 711 } 712 713 if (i2s_tdm->clk_trcm) { 714 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val); 715 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 716 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 717 I2S_CLKDIV_TXM_MASK, 718 I2S_CLKDIV_TXM(div_bclk)); 719 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 720 I2S_CKR_TSD_MASK, 721 I2S_CKR_TSD(div_lrck)); 722 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 723 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 724 val); 725 } else { 726 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 727 I2S_CLKDIV_RXM_MASK, 728 I2S_CLKDIV_RXM(div_bclk)); 729 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 730 I2S_CKR_RSD_MASK, 731 I2S_CKR_RSD(div_lrck)); 732 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 733 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 734 val); 735 } 736 737 return rockchip_i2s_io_multiplex(substream, dai); 738} 739 740static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream, 741 int cmd, struct snd_soc_dai *dai) 742{ 743 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 744 745 switch (cmd) { 746 case SNDRV_PCM_TRIGGER_START: 747 case SNDRV_PCM_TRIGGER_RESUME: 748 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 749 if (i2s_tdm->clk_trcm) 750 rockchip_snd_txrxctrl(substream, dai, 1); 751 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 752 rockchip_snd_rxctrl(i2s_tdm, 1); 753 else 754 rockchip_snd_txctrl(i2s_tdm, 1); 755 break; 756 case SNDRV_PCM_TRIGGER_SUSPEND: 757 case SNDRV_PCM_TRIGGER_STOP: 758 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 759 if (i2s_tdm->clk_trcm) 760 rockchip_snd_txrxctrl(substream, dai, 0); 761 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 762 rockchip_snd_rxctrl(i2s_tdm, 0); 763 else 764 rockchip_snd_txctrl(i2s_tdm, 0); 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 return 0; 771} 772 773static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai) 774{ 775 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 776 777 if (i2s_tdm->has_capture) 778 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data); 779 if (i2s_tdm->has_playback) 780 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data); 781 782 return 0; 783} 784 785static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai, 786 unsigned int tx_mask, unsigned int rx_mask, 787 int slots, int slot_width) 788{ 789 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 790 unsigned int mask, val; 791 792 i2s_tdm->tdm_mode = true; 793 i2s_tdm->frame_width = slots * slot_width; 794 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK; 795 val = TDM_SLOT_BIT_WIDTH(slot_width) | 796 TDM_FRAME_WIDTH(slots * slot_width); 797 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 798 mask, val); 799 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 800 mask, val); 801 802 return 0; 803} 804 805static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai, 806 unsigned int ratio) 807{ 808 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 809 810 if (ratio < 32 || ratio > 512 || ratio % 2 == 1) 811 return -EINVAL; 812 813 i2s_tdm->frame_width = ratio; 814 815 return 0; 816} 817 818static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = { 819 .probe = rockchip_i2s_tdm_dai_probe, 820 .hw_params = rockchip_i2s_tdm_hw_params, 821 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio, 822 .set_fmt = rockchip_i2s_tdm_set_fmt, 823 .set_tdm_slot = rockchip_dai_tdm_slot, 824 .trigger = rockchip_i2s_tdm_trigger, 825}; 826 827static const struct snd_soc_component_driver rockchip_i2s_tdm_component = { 828 .name = DRV_NAME, 829 .legacy_dai_naming = 1, 830}; 831 832static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg) 833{ 834 switch (reg) { 835 case I2S_TXCR: 836 case I2S_RXCR: 837 case I2S_CKR: 838 case I2S_DMACR: 839 case I2S_INTCR: 840 case I2S_XFER: 841 case I2S_CLR: 842 case I2S_TXDR: 843 case I2S_TDM_TXCR: 844 case I2S_TDM_RXCR: 845 case I2S_CLKDIV: 846 return true; 847 default: 848 return false; 849 } 850} 851 852static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg) 853{ 854 switch (reg) { 855 case I2S_TXCR: 856 case I2S_RXCR: 857 case I2S_CKR: 858 case I2S_DMACR: 859 case I2S_INTCR: 860 case I2S_XFER: 861 case I2S_CLR: 862 case I2S_TXDR: 863 case I2S_RXDR: 864 case I2S_TXFIFOLR: 865 case I2S_INTSR: 866 case I2S_RXFIFOLR: 867 case I2S_TDM_TXCR: 868 case I2S_TDM_RXCR: 869 case I2S_CLKDIV: 870 return true; 871 default: 872 return false; 873 } 874} 875 876static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg) 877{ 878 switch (reg) { 879 case I2S_TXFIFOLR: 880 case I2S_INTSR: 881 case I2S_CLR: 882 case I2S_TXDR: 883 case I2S_RXDR: 884 case I2S_RXFIFOLR: 885 return true; 886 default: 887 return false; 888 } 889} 890 891static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg) 892{ 893 if (reg == I2S_RXDR) 894 return true; 895 return false; 896} 897 898static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = { 899 {0x00, 0x7200000f}, 900 {0x04, 0x01c8000f}, 901 {0x08, 0x00001f1f}, 902 {0x10, 0x001f0000}, 903 {0x14, 0x01f00000}, 904 {0x30, 0x00003eff}, 905 {0x34, 0x00003eff}, 906 {0x38, 0x00000707}, 907}; 908 909static const struct regmap_config rockchip_i2s_tdm_regmap_config = { 910 .reg_bits = 32, 911 .reg_stride = 4, 912 .val_bits = 32, 913 .max_register = I2S_CLKDIV, 914 .reg_defaults = rockchip_i2s_tdm_reg_defaults, 915 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults), 916 .writeable_reg = rockchip_i2s_tdm_wr_reg, 917 .readable_reg = rockchip_i2s_tdm_rd_reg, 918 .volatile_reg = rockchip_i2s_tdm_volatile_reg, 919 .precious_reg = rockchip_i2s_tdm_precious_reg, 920 .cache_type = REGCACHE_FLAT, 921}; 922 923static int common_soc_init(struct device *dev, u32 addr) 924{ 925 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 926 const struct txrx_config *configs = i2s_tdm->soc_data->configs; 927 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm; 928 int i; 929 930 if (trcm == TRCM_TXRX) 931 return 0; 932 933 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 934 dev_err(i2s_tdm->dev, 935 "no grf present but non-txrx TRCM specified\n"); 936 return -EINVAL; 937 } 938 939 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { 940 if (addr != configs[i].addr) 941 continue; 942 reg = configs[i].reg; 943 if (trcm == TRCM_TX) 944 val = configs[i].txonly; 945 else 946 val = configs[i].rxonly; 947 948 if (reg) 949 regmap_write(i2s_tdm->grf, reg, val); 950 } 951 952 return 0; 953} 954 955static const struct txrx_config px30_txrx_config[] = { 956 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY }, 957}; 958 959static const struct txrx_config rk1808_txrx_config[] = { 960 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY }, 961}; 962 963static const struct txrx_config rk3308_txrx_config[] = { 964 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY }, 965 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY }, 966}; 967 968static const struct txrx_config rk3568_txrx_config[] = { 969 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY }, 970 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE }, 971 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE }, 972 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY }, 973 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY }, 974 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE }, 975}; 976 977static const struct txrx_config rv1126_txrx_config[] = { 978 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY }, 979}; 980 981static struct rk_i2s_soc_data px30_i2s_soc_data = { 982 .softrst_offset = 0x0300, 983 .configs = px30_txrx_config, 984 .config_count = ARRAY_SIZE(px30_txrx_config), 985 .init = common_soc_init, 986}; 987 988static struct rk_i2s_soc_data rk1808_i2s_soc_data = { 989 .softrst_offset = 0x0300, 990 .configs = rk1808_txrx_config, 991 .config_count = ARRAY_SIZE(rk1808_txrx_config), 992 .init = common_soc_init, 993}; 994 995static struct rk_i2s_soc_data rk3308_i2s_soc_data = { 996 .softrst_offset = 0x0400, 997 .grf_reg_offset = 0x0308, 998 .grf_shift = 5, 999 .configs = rk3308_txrx_config, 1000 .config_count = ARRAY_SIZE(rk3308_txrx_config), 1001 .init = common_soc_init, 1002}; 1003 1004static struct rk_i2s_soc_data rk3568_i2s_soc_data = { 1005 .softrst_offset = 0x0400, 1006 .configs = rk3568_txrx_config, 1007 .config_count = ARRAY_SIZE(rk3568_txrx_config), 1008 .init = common_soc_init, 1009}; 1010 1011static struct rk_i2s_soc_data rv1126_i2s_soc_data = { 1012 .softrst_offset = 0x0300, 1013 .configs = rv1126_txrx_config, 1014 .config_count = ARRAY_SIZE(rv1126_txrx_config), 1015 .init = common_soc_init, 1016}; 1017 1018static const struct of_device_id rockchip_i2s_tdm_match[] = { 1019 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data }, 1020 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, 1021 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, 1022 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, 1023 { .compatible = "rockchip,rk3588-i2s-tdm" }, 1024 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, 1025 {}, 1026}; 1027 1028static const struct snd_soc_dai_driver i2s_tdm_dai = { 1029 .ops = &rockchip_i2s_tdm_dai_ops, 1030}; 1031 1032static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm) 1033{ 1034 struct snd_soc_dai_driver *dai; 1035 struct property *dma_names; 1036 const char *dma_name; 1037 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | 1038 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | 1039 SNDRV_PCM_FMTBIT_S32_LE); 1040 struct device_node *node = i2s_tdm->dev->of_node; 1041 1042 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1043 if (!strcmp(dma_name, "tx")) 1044 i2s_tdm->has_playback = true; 1045 if (!strcmp(dma_name, "rx")) 1046 i2s_tdm->has_capture = true; 1047 } 1048 1049 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai, 1050 sizeof(*dai), GFP_KERNEL); 1051 if (!dai) 1052 return -ENOMEM; 1053 1054 if (i2s_tdm->has_playback) { 1055 dai->playback.stream_name = "Playback"; 1056 dai->playback.channels_min = 2; 1057 dai->playback.channels_max = 8; 1058 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 1059 dai->playback.formats = formats; 1060 } 1061 1062 if (i2s_tdm->has_capture) { 1063 dai->capture.stream_name = "Capture"; 1064 dai->capture.channels_min = 2; 1065 dai->capture.channels_max = 8; 1066 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 1067 dai->capture.formats = formats; 1068 } 1069 1070 if (i2s_tdm->clk_trcm != TRCM_TXRX) 1071 dai->symmetric_rate = 1; 1072 1073 i2s_tdm->dai = dai; 1074 1075 return 0; 1076} 1077 1078static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm, 1079 int num, 1080 bool is_rx_path) 1081{ 1082 unsigned int *i2s_data; 1083 int i, j; 1084 1085 if (is_rx_path) 1086 i2s_data = i2s_tdm->i2s_sdis; 1087 else 1088 i2s_data = i2s_tdm->i2s_sdos; 1089 1090 for (i = 0; i < num; i++) { 1091 if (i2s_data[i] > CH_GRP_MAX - 1) { 1092 dev_err(i2s_tdm->dev, 1093 "%s path i2s_data[%d]: %d is too high, max is: %d\n", 1094 is_rx_path ? "RX" : "TX", 1095 i, i2s_data[i], CH_GRP_MAX); 1096 return -EINVAL; 1097 } 1098 1099 for (j = 0; j < num; j++) { 1100 if (i == j) 1101 continue; 1102 1103 if (i2s_data[i] == i2s_data[j]) { 1104 dev_err(i2s_tdm->dev, 1105 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n", 1106 is_rx_path ? "RX" : "TX", 1107 i, i2s_data[i], 1108 j, i2s_data[j]); 1109 return -EINVAL; 1110 } 1111 } 1112 } 1113 1114 return 0; 1115} 1116 1117static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1118 int num) 1119{ 1120 int idx; 1121 1122 for (idx = 0; idx < num; idx++) { 1123 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 1124 I2S_TXCR_PATH_MASK(idx), 1125 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx])); 1126 } 1127} 1128 1129static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1130 int num) 1131{ 1132 int idx; 1133 1134 for (idx = 0; idx < num; idx++) { 1135 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 1136 I2S_RXCR_PATH_MASK(idx), 1137 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx])); 1138 } 1139} 1140 1141static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1142 int num, bool is_rx_path) 1143{ 1144 if (is_rx_path) 1145 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num); 1146 else 1147 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num); 1148} 1149 1150static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1151 struct device_node *np, 1152 bool is_rx_path) 1153{ 1154 char *i2s_tx_path_prop = "rockchip,i2s-tx-route"; 1155 char *i2s_rx_path_prop = "rockchip,i2s-rx-route"; 1156 char *i2s_path_prop; 1157 unsigned int *i2s_data; 1158 int num, ret = 0; 1159 1160 if (is_rx_path) { 1161 i2s_path_prop = i2s_rx_path_prop; 1162 i2s_data = i2s_tdm->i2s_sdis; 1163 } else { 1164 i2s_path_prop = i2s_tx_path_prop; 1165 i2s_data = i2s_tdm->i2s_sdos; 1166 } 1167 1168 num = of_count_phandle_with_args(np, i2s_path_prop, NULL); 1169 if (num < 0) { 1170 if (num != -ENOENT) { 1171 dev_err(i2s_tdm->dev, 1172 "Failed to read '%s' num: %d\n", 1173 i2s_path_prop, num); 1174 ret = num; 1175 } 1176 return ret; 1177 } else if (num != CH_GRP_MAX) { 1178 dev_err(i2s_tdm->dev, 1179 "The num: %d should be: %d\n", num, CH_GRP_MAX); 1180 return -EINVAL; 1181 } 1182 1183 ret = of_property_read_u32_array(np, i2s_path_prop, 1184 i2s_data, num); 1185 if (ret < 0) { 1186 dev_err(i2s_tdm->dev, 1187 "Failed to read '%s': %d\n", 1188 i2s_path_prop, ret); 1189 return ret; 1190 } 1191 1192 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path); 1193 if (ret < 0) { 1194 dev_err(i2s_tdm->dev, 1195 "Failed to check i2s data bus: %d\n", ret); 1196 return ret; 1197 } 1198 1199 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path); 1200 1201 return 0; 1202} 1203 1204static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1205 struct device_node *np) 1206{ 1207 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0); 1208} 1209 1210static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1211 struct device_node *np) 1212{ 1213 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1); 1214} 1215 1216static int rockchip_i2s_tdm_probe(struct platform_device *pdev) 1217{ 1218 struct device_node *node = pdev->dev.of_node; 1219 const struct of_device_id *of_id; 1220 struct rk_i2s_tdm_dev *i2s_tdm; 1221 struct resource *res; 1222 void __iomem *regs; 1223 int ret; 1224 1225 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL); 1226 if (!i2s_tdm) 1227 return -ENOMEM; 1228 1229 i2s_tdm->dev = &pdev->dev; 1230 1231 of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev); 1232 if (!of_id) 1233 return -EINVAL; 1234 1235 spin_lock_init(&i2s_tdm->lock); 1236 i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data; 1237 1238 i2s_tdm->frame_width = 64; 1239 1240 i2s_tdm->clk_trcm = TRCM_TXRX; 1241 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only")) 1242 i2s_tdm->clk_trcm = TRCM_TX; 1243 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) { 1244 if (i2s_tdm->clk_trcm) { 1245 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n"); 1246 return -EINVAL; 1247 } 1248 i2s_tdm->clk_trcm = TRCM_RX; 1249 } 1250 1251 ret = rockchip_i2s_tdm_init_dai(i2s_tdm); 1252 if (ret) 1253 return ret; 1254 1255 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 1256 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1257 "tx-m"); 1258 if (IS_ERR(i2s_tdm->tx_reset)) { 1259 ret = PTR_ERR(i2s_tdm->tx_reset); 1260 return dev_err_probe(i2s_tdm->dev, ret, 1261 "Error in tx-m reset control\n"); 1262 } 1263 1264 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1265 "rx-m"); 1266 if (IS_ERR(i2s_tdm->rx_reset)) { 1267 ret = PTR_ERR(i2s_tdm->rx_reset); 1268 return dev_err_probe(i2s_tdm->dev, ret, 1269 "Error in rx-m reset control\n"); 1270 } 1271 1272 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk"); 1273 if (IS_ERR(i2s_tdm->hclk)) { 1274 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk), 1275 "Failed to get clock hclk\n"); 1276 } 1277 1278 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); 1279 if (IS_ERR(i2s_tdm->mclk_tx)) { 1280 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx), 1281 "Failed to get clock mclk_tx\n"); 1282 } 1283 1284 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); 1285 if (IS_ERR(i2s_tdm->mclk_rx)) { 1286 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx), 1287 "Failed to get clock mclk_rx\n"); 1288 } 1289 1290 i2s_tdm->io_multiplex = 1291 of_property_read_bool(node, "rockchip,io-multiplex"); 1292 1293 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1294 if (IS_ERR(regs)) { 1295 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs), 1296 "Failed to get resource IORESOURCE_MEM\n"); 1297 } 1298 1299 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1300 &rockchip_i2s_tdm_regmap_config); 1301 if (IS_ERR(i2s_tdm->regmap)) { 1302 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap), 1303 "Failed to initialise regmap\n"); 1304 } 1305 1306 if (i2s_tdm->has_playback) { 1307 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR; 1308 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1309 i2s_tdm->playback_dma_data.maxburst = 8; 1310 } 1311 1312 if (i2s_tdm->has_capture) { 1313 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR; 1314 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1315 i2s_tdm->capture_dma_data.maxburst = 8; 1316 } 1317 1318 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node); 1319 if (ret < 0) { 1320 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret); 1321 return ret; 1322 } 1323 1324 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node); 1325 if (ret < 0) { 1326 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret); 1327 return ret; 1328 } 1329 1330 dev_set_drvdata(&pdev->dev, i2s_tdm); 1331 1332 ret = clk_prepare_enable(i2s_tdm->hclk); 1333 if (ret) { 1334 return dev_err_probe(i2s_tdm->dev, ret, 1335 "Failed to enable clock hclk\n"); 1336 } 1337 1338 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 1339 if (ret) { 1340 ret = dev_err_probe(i2s_tdm->dev, ret, 1341 "Failed to enable one or more mclks\n"); 1342 goto err_disable_hclk; 1343 } 1344 1345 pm_runtime_enable(&pdev->dev); 1346 1347 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 1348 I2S_DMACR_TDL(16)); 1349 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 1350 I2S_DMACR_RDL(16)); 1351 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK, 1352 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT); 1353 1354 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init) 1355 i2s_tdm->soc_data->init(&pdev->dev, res->start); 1356 1357 ret = devm_snd_soc_register_component(&pdev->dev, 1358 &rockchip_i2s_tdm_component, 1359 i2s_tdm->dai, 1); 1360 1361 if (ret) { 1362 dev_err(&pdev->dev, "Could not register DAI\n"); 1363 goto err_suspend; 1364 } 1365 1366 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1367 if (ret) { 1368 dev_err(&pdev->dev, "Could not register PCM\n"); 1369 goto err_suspend; 1370 } 1371 1372 return 0; 1373 1374err_suspend: 1375 if (!pm_runtime_status_suspended(&pdev->dev)) 1376 i2s_tdm_runtime_suspend(&pdev->dev); 1377 pm_runtime_disable(&pdev->dev); 1378 1379err_disable_hclk: 1380 clk_disable_unprepare(i2s_tdm->hclk); 1381 1382 return ret; 1383} 1384 1385static int rockchip_i2s_tdm_remove(struct platform_device *pdev) 1386{ 1387 if (!pm_runtime_status_suspended(&pdev->dev)) 1388 i2s_tdm_runtime_suspend(&pdev->dev); 1389 1390 pm_runtime_disable(&pdev->dev); 1391 1392 return 0; 1393} 1394 1395static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev) 1396{ 1397 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1398 1399 regcache_mark_dirty(i2s_tdm->regmap); 1400 1401 return 0; 1402} 1403 1404static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev) 1405{ 1406 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1407 int ret; 1408 1409 ret = pm_runtime_resume_and_get(dev); 1410 if (ret < 0) 1411 return ret; 1412 ret = regcache_sync(i2s_tdm->regmap); 1413 pm_runtime_put(dev); 1414 1415 return ret; 1416} 1417 1418static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = { 1419 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume, 1420 NULL) 1421 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend, 1422 rockchip_i2s_tdm_resume) 1423}; 1424 1425static struct platform_driver rockchip_i2s_tdm_driver = { 1426 .probe = rockchip_i2s_tdm_probe, 1427 .remove = rockchip_i2s_tdm_remove, 1428 .driver = { 1429 .name = DRV_NAME, 1430 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match), 1431 .pm = &rockchip_i2s_tdm_pm_ops, 1432 }, 1433}; 1434module_platform_driver(rockchip_i2s_tdm_driver); 1435 1436MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface"); 1437MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1438MODULE_LICENSE("GPL v2"); 1439MODULE_ALIAS("platform:" DRV_NAME); 1440MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match); 1441