1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2021, Linaro Limited
3
4#include <linux/err.h>
5#include <linux/init.h>
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/device.h>
9#include <linux/platform_device.h>
10#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
11#include "q6dsp-lpass-clocks.h"
12#include "q6prm.h"
13
14#define Q6PRM_CLK(id) {					\
15		.clk_id	= id,				\
16		.q6dsp_clk_id	= Q6PRM_##id,		\
17		.name = #id,				\
18		.rate = 19200000,			\
19	}
20
21static const struct q6dsp_clk_init q6prm_clks[] = {
22	Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
23	Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
24	Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
25	Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
26	Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
27	Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
28	Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
29	Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
30	Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
31	Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
32	Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
33	Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
34	Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
35	Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
36	Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
37	Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
38	Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
39	Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
40	Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
41	Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
42	Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
43	Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
44	Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
45	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
46	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
47	Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
48	Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
49	Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
50	Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
51	Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
52	Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
53	Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
54	Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
55	Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
56	Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
57	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
58	Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
59	Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
60	Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
61	Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
62	Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
63		       "LPASS_HW_MACRO"),
64	Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
65		       "LPASS_HW_DCODEC"),
66};
67
68static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {
69	.clks = q6prm_clks,
70	.num_clks = ARRAY_SIZE(q6prm_clks),
71	.lpass_set_clk = q6prm_set_lpass_clock,
72	.lpass_vote_clk = q6prm_vote_lpass_core_hw,
73	.lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
74};
75
76#ifdef CONFIG_OF
77static const struct of_device_id q6prm_clock_device_id[] = {
78	{ .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm },
79	{},
80};
81MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
82#endif
83
84static struct platform_driver q6prm_clock_platform_driver = {
85	.driver = {
86		.name = "q6prm-lpass-clock",
87		.of_match_table = of_match_ptr(q6prm_clock_device_id),
88	},
89	.probe = q6dsp_clock_dev_probe,
90};
91module_platform_driver(q6prm_clock_platform_driver);
92
93MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver");
94MODULE_LICENSE("GPL");
95