1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef __Q6AFE_H__ 4#define __Q6AFE_H__ 5 6#include <dt-bindings/sound/qcom,q6afe.h> 7 8#define AFE_PORT_MAX 129 9 10#define MSM_AFE_PORT_TYPE_RX 0 11#define MSM_AFE_PORT_TYPE_TX 1 12#define AFE_MAX_PORTS AFE_PORT_MAX 13 14#define Q6AFE_MAX_MI2S_LINES 4 15 16#define AFE_MAX_CHAN_COUNT 8 17#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 18 19#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 20#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 21 22#define LPAIF_DIG_CLK 1 23#define LPAIF_BIT_CLK 2 24#define LPAIF_OSR_CLK 3 25 26/* Clock ID for Primary I2S IBIT */ 27#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 28/* Clock ID for Primary I2S EBIT */ 29#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 30/* Clock ID for Secondary I2S IBIT */ 31#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 32/* Clock ID for Secondary I2S EBIT */ 33#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 34/* Clock ID for Tertiary I2S IBIT */ 35#define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 36/* Clock ID for Tertiary I2S EBIT */ 37#define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 38/* Clock ID for Quartnery I2S IBIT */ 39#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 40/* Clock ID for Quartnery I2S EBIT */ 41#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 42/* Clock ID for Speaker I2S IBIT */ 43#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 44/* Clock ID for Speaker I2S EBIT */ 45#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 46/* Clock ID for Speaker I2S OSR */ 47#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A 48 49/* Clock ID for QUINARY I2S IBIT */ 50#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B 51/* Clock ID for QUINARY I2S EBIT */ 52#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C 53/* Clock ID for SENARY I2S IBIT */ 54#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D 55/* Clock ID for SENARY I2S EBIT */ 56#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E 57/* Clock ID for INT0 I2S IBIT */ 58#define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F 59/* Clock ID for INT1 I2S IBIT */ 60#define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 61/* Clock ID for INT2 I2S IBIT */ 62#define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 63/* Clock ID for INT3 I2S IBIT */ 64#define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 65/* Clock ID for INT4 I2S IBIT */ 66#define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 67/* Clock ID for INT5 I2S IBIT */ 68#define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 69/* Clock ID for INT6 I2S IBIT */ 70#define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 71 72/* Clock ID for QUINARY MI2S OSR CLK */ 73#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 74 75/* Clock ID for Primary PCM IBIT */ 76#define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200 77/* Clock ID for Primary PCM EBIT */ 78#define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201 79/* Clock ID for Secondary PCM IBIT */ 80#define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202 81/* Clock ID for Secondary PCM EBIT */ 82#define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203 83/* Clock ID for Tertiary PCM IBIT */ 84#define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204 85/* Clock ID for Tertiary PCM EBIT */ 86#define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205 87/* Clock ID for Quartery PCM IBIT */ 88#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206 89/* Clock ID for Quartery PCM EBIT */ 90#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207 91/* Clock ID for Quinary PCM IBIT */ 92#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208 93/* Clock ID for Quinary PCM EBIT */ 94#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209 95/* Clock ID for QUINARY PCM OSR */ 96#define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A 97 98/** Clock ID for Primary TDM IBIT */ 99#define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200 100/** Clock ID for Primary TDM EBIT */ 101#define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201 102/** Clock ID for Secondary TDM IBIT */ 103#define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202 104/** Clock ID for Secondary TDM EBIT */ 105#define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203 106/** Clock ID for Tertiary TDM IBIT */ 107#define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204 108/** Clock ID for Tertiary TDM EBIT */ 109#define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205 110/** Clock ID for Quartery TDM IBIT */ 111#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206 112/** Clock ID for Quartery TDM EBIT */ 113#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207 114/** Clock ID for Quinary TDM IBIT */ 115#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208 116/** Clock ID for Quinary TDM EBIT */ 117#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209 118/** Clock ID for Quinary TDM OSR */ 119#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A 120 121/* Clock ID for MCLK1 */ 122#define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300 123/* Clock ID for MCLK2 */ 124#define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301 125/* Clock ID for MCLK3 */ 126#define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302 127/* Clock ID for MCLK4 */ 128#define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304 129/* Clock ID for Internal Digital Codec Core */ 130#define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303 131/* Clock ID for INT MCLK0 */ 132#define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305 133/* Clock ID for INT MCLK1 */ 134#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306 135 136#define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309 137#define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a 138#define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c 139#define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d 140#define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e 141#define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f 142#define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b 143#define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310 144 145#define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2 146#define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3 147#define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4 148 149/* Clock attribute for invalid use (reserved for internal usage) */ 150#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0 151/* Clock attribute for no couple case */ 152#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 153/* Clock attribute for dividend couple case */ 154#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 155/* Clock attribute for divisor couple case */ 156#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 157/* Clock attribute for invert and no couple case */ 158#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4 159 160#define Q6AFE_CMAP_INVALID 0xFFFF 161 162struct q6afe_hdmi_cfg { 163 u16 datatype; 164 u16 channel_allocation; 165 u32 sample_rate; 166 u16 bit_width; 167}; 168 169struct q6afe_slim_cfg { 170 u32 sample_rate; 171 u16 bit_width; 172 u16 data_format; 173 u16 num_channels; 174 u8 ch_mapping[AFE_MAX_CHAN_COUNT]; 175}; 176 177struct q6afe_i2s_cfg { 178 u32 sample_rate; 179 u16 bit_width; 180 u16 data_format; 181 u16 num_channels; 182 u32 sd_line_mask; 183 int fmt; 184}; 185 186struct q6afe_tdm_cfg { 187 u16 num_channels; 188 u32 sample_rate; 189 u16 bit_width; 190 u16 data_format; 191 u16 sync_mode; 192 u16 sync_src; 193 u16 nslots_per_frame; 194 u16 slot_width; 195 u16 slot_mask; 196 u32 data_align_type; 197 u16 ch_mapping[AFE_MAX_CHAN_COUNT]; 198}; 199 200struct q6afe_cdc_dma_cfg { 201 u16 sample_rate; 202 u16 bit_width; 203 u16 data_format; 204 u16 num_channels; 205 u16 active_channels_mask; 206}; 207 208 209struct q6afe_port_config { 210 struct q6afe_hdmi_cfg hdmi; 211 struct q6afe_slim_cfg slim; 212 struct q6afe_i2s_cfg i2s_cfg; 213 struct q6afe_tdm_cfg tdm; 214 struct q6afe_cdc_dma_cfg dma_cfg; 215}; 216 217struct q6afe_port; 218 219struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id); 220int q6afe_port_start(struct q6afe_port *port); 221int q6afe_port_stop(struct q6afe_port *port); 222void q6afe_port_put(struct q6afe_port *port); 223int q6afe_get_port_id(int index); 224void q6afe_hdmi_port_prepare(struct q6afe_port *port, 225 struct q6afe_hdmi_cfg *cfg); 226void q6afe_slim_port_prepare(struct q6afe_port *port, 227 struct q6afe_slim_cfg *cfg); 228int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg); 229void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg); 230void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 231 struct q6afe_cdc_dma_cfg *cfg); 232 233int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 234 int clk_src, int clk_root, 235 unsigned int freq, int dir); 236int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 237 int clk_root, unsigned int freq); 238int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 239 const char *client_name, uint32_t *client_handle); 240int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 241 uint32_t client_handle); 242#endif /* __Q6AFE_H__ */ 243