1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef __AUDIOREACH_H__ 4#define __AUDIOREACH_H__ 5#include <linux/types.h> 6#include <linux/soc/qcom/apr.h> 7#include <sound/soc.h> 8struct q6apm; 9struct q6apm_graph; 10 11/* Module IDs */ 12#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 13#define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 14#define MODULE_ID_GAIN 0x07001002 15#define MODULE_ID_PCM_CNV 0x07001003 16#define MODULE_ID_PCM_ENC 0x07001004 17#define MODULE_ID_PCM_DEC 0x07001005 18#define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 19#define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 20#define MODULE_ID_SAL 0x07001010 21#define MODULE_ID_MFC 0x07001015 22#define MODULE_ID_CODEC_DMA_SINK 0x07001023 23#define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 24#define MODULE_ID_I2S_SINK 0x0700100A 25#define MODULE_ID_I2S_SOURCE 0x0700100B 26#define MODULE_ID_DATA_LOGGING 0x0700101A 27#define MODULE_ID_AAC_DEC 0x0700101F 28#define MODULE_ID_FLAC_DEC 0x0700102F 29#define MODULE_ID_MP3_DECODE 0x0700103B 30#define MODULE_ID_GAPLESS 0x0700104D 31#define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 32 33#define APM_CMD_GET_SPF_STATE 0x01001021 34#define APM_CMD_RSP_GET_SPF_STATE 0x02001007 35 36#define APM_MODULE_INSTANCE_ID 0x00000001 37#define PRM_MODULE_INSTANCE_ID 0x00000002 38#define AMDB_MODULE_INSTANCE_ID 0x00000003 39#define VCPM_MODULE_INSTANCE_ID 0x00000004 40#define AR_MODULE_INSTANCE_ID_START 0x00006000 41#define AR_MODULE_INSTANCE_ID_END 0x00007000 42#define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 43#define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 44#define AR_CONT_INSTANCE_ID_START 0x00005000 45#define AR_CONT_INSTANCE_ID_END 0x00006000 46#define AR_SG_INSTANCE_ID_START 0x00004000 47 48#define APM_CMD_GRAPH_OPEN 0x01001000 49#define APM_CMD_GRAPH_PREPARE 0x01001001 50#define APM_CMD_GRAPH_START 0x01001002 51#define APM_CMD_GRAPH_STOP 0x01001003 52#define APM_CMD_GRAPH_CLOSE 0x01001004 53#define APM_CMD_GRAPH_FLUSH 0x01001005 54#define APM_CMD_SET_CFG 0x01001006 55#define APM_CMD_GET_CFG 0x01001007 56#define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 57#define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 58#define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 59#define APM_CMD_RSP_GET_CFG 0x02001000 60#define APM_CMD_CLOSE_ALL 0x01001013 61#define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 62 63#define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 64 65struct apm_cmd_shared_mem_map_regions { 66 uint16_t mem_pool_id; 67 uint16_t num_regions; 68 uint32_t property_flag; 69} __packed; 70 71struct apm_shared_map_region_payload { 72 uint32_t shm_addr_lsw; 73 uint32_t shm_addr_msw; 74 uint32_t mem_size_bytes; 75} __packed; 76 77struct apm_cmd_shared_mem_unmap_regions { 78 uint32_t mem_map_handle; 79} __packed; 80 81struct apm_cmd_rsp_shared_mem_map_regions { 82 uint32_t mem_map_handle; 83} __packed; 84 85/* APM module */ 86#define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 87 88#define APM_PARAM_ID_MODULE_LIST 0x08001002 89 90struct apm_param_id_modules_list { 91 uint32_t num_modules_list; 92} __packed; 93 94#define APM_PARAM_ID_MODULE_PROP 0x08001003 95 96struct apm_param_id_module_prop { 97 uint32_t num_modules_prop_cfg; 98} __packed; 99 100struct apm_module_prop_cfg { 101 uint32_t instance_id; 102 uint32_t num_props; 103} __packed; 104 105#define APM_PARAM_ID_MODULE_CONN 0x08001004 106 107struct apm_param_id_module_conn { 108 uint32_t num_connections; 109} __packed; 110 111struct apm_module_conn_obj { 112 uint32_t src_mod_inst_id; 113 uint32_t src_mod_op_port_id; 114 uint32_t dst_mod_inst_id; 115 uint32_t dst_mod_ip_port_id; 116} __packed; 117 118#define APM_PARAM_ID_GAIN 0x08001006 119 120struct param_id_gain_cfg { 121 uint16_t gain; 122 uint16_t reserved; 123} __packed; 124 125#define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 126 127struct param_id_pcm_output_format_cfg { 128 uint32_t data_format; 129 uint32_t fmt_id; 130 uint32_t payload_size; 131} __packed; 132 133struct payload_pcm_output_format_cfg { 134 uint16_t bit_width; 135 uint16_t alignment; 136 uint16_t bits_per_sample; 137 uint16_t q_factor; 138 uint16_t endianness; 139 uint16_t interleaved; 140 uint16_t reserved; 141 uint16_t num_channels; 142 uint8_t channel_mapping[]; 143} __packed; 144 145#define PARAM_ID_ENC_BITRATE 0x08001052 146 147struct param_id_enc_bitrate_param { 148 uint32_t bitrate; 149} __packed; 150 151#define DATA_FORMAT_FIXED_POINT 1 152#define DATA_FORMAT_GENERIC_COMPRESSED 5 153#define DATA_FORMAT_RAW_COMPRESSED 6 154#define PCM_LSB_ALIGNED 1 155#define PCM_MSB_ALIGNED 2 156#define PCM_LITTLE_ENDIAN 1 157#define PCM_BIT_ENDIAN 2 158 159#define MEDIA_FMT_ID_PCM 0x09001000 160#define MEDIA_FMT_ID_MP3 0x09001009 161#define PCM_CHANNEL_L 1 162#define PCM_CHANNEL_R 2 163#define SAMPLE_RATE_48K 48000 164#define BIT_WIDTH_16 16 165 166#define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 167 168struct apm_modules_prop_info { 169 uint32_t max_ip_port; 170 uint32_t max_op_port; 171} __packed; 172 173/* Shared memory module */ 174#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 175#define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 176#define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 177#define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 178#define WR_SH_MEM_EP_EOF_FLAG BIT(4) 179 180struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 181 uint32_t buf_addr_lsw; 182 uint32_t buf_addr_msw; 183 uint32_t mem_map_handle; 184 uint32_t buf_size; 185 uint32_t timestamp_lsw; 186 uint32_t timestamp_msw; 187 uint32_t flags; 188} __packed; 189 190#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 191 192struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 193 uint32_t buf_addr_lsw; 194 uint32_t buf_addr_msw; 195 uint32_t mem_map_handle; 196 uint32_t buf_size; 197 uint32_t timestamp_lsw; 198 uint32_t timestamp_msw; 199 uint32_t flags; 200 uint32_t md_addr_lsw; 201 uint32_t md_addr_msw; 202 uint32_t md_map_handle; 203 uint32_t md_buf_size; 204} __packed; 205 206#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 207 208struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 209 uint32_t buf_addr_lsw; 210 uint32_t buf_addr_msw; 211 uint32_t mem_map_handle; 212 uint32_t status; 213 214} __packed; 215 216#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 217 218struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 219 uint32_t buf_addr_lsw; 220 uint32_t buf_addr_msw; 221 uint32_t mem_map_handle; 222 uint32_t status; 223 uint32_t md_buf_addr_lsw; 224 uint32_t md_buf_addr_msw; 225 uint32_t md_mem_map_handle; 226 uint32_t md_status; 227} __packed; 228 229#define PARAM_ID_MEDIA_FORMAT 0x0800100C 230#define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 231 232struct apm_media_format { 233 uint32_t data_format; 234 uint32_t fmt_id; 235 uint32_t payload_size; 236} __packed; 237 238#define MEDIA_FMT_ID_FLAC 0x09001004 239 240struct payload_media_fmt_flac_t { 241 uint16_t num_channels; 242 uint16_t sample_size; 243 uint16_t min_blk_size; 244 uint16_t max_blk_size; 245 uint32_t sample_rate; 246 uint32_t min_frame_size; 247 uint32_t max_frame_size; 248} __packed; 249 250#define MEDIA_FMT_ID_AAC 0x09001001 251 252struct payload_media_fmt_aac_t { 253 uint16_t aac_fmt_flag; 254 uint16_t audio_obj_type; 255 uint16_t num_channels; 256 uint16_t total_size_of_PCE_bits; 257 uint32_t sample_rate; 258} __packed; 259 260#define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 261#define WR_SH_MEM_EP_EOS_POLICY_LAST 1 262#define WR_SH_MEM_EP_EOS_POLICY_EACH 2 263 264struct data_cmd_wr_sh_mem_ep_eos { 265 uint32_t policy; 266 267} __packed; 268 269#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 270 271struct data_cmd_rd_sh_mem_ep_data_buffer { 272 uint32_t buf_addr_lsw; 273 uint32_t buf_addr_msw; 274 uint32_t mem_map_handle; 275 uint32_t buf_size; 276} __packed; 277 278#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 279 280struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 281 uint32_t status; 282 uint32_t buf_addr_lsw; 283 uint32_t buf_addr_msw; 284 uint32_t mem_map_handle; 285 uint32_t data_size; 286 uint32_t offset; 287 uint32_t timestamp_lsw; 288 uint32_t timestamp_msw; 289 uint32_t flags; 290 uint32_t num_frames; 291} __packed; 292 293#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 294 295struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 296 uint32_t buf_addr_lsw; 297 uint32_t buf_addr_msw; 298 uint32_t mem_map_handle; 299 uint32_t buf_size; 300 uint32_t md_buf_addr_lsw; 301 uint32_t md_buf_addr_msw; 302 uint32_t md_mem_map_handle; 303 uint32_t md_buf_size; 304} __packed; 305 306#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 307 308struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 309 uint32_t status; 310 uint32_t buf_addr_lsw; 311 uint32_t buf_addr_msw; 312 uint32_t mem_map_handle; 313 uint32_t data_size; 314 uint32_t offset; 315 uint32_t timestamp_lsw; 316 uint32_t timestamp_msw; 317 uint32_t flags; 318 uint32_t num_frames; 319 uint32_t md_status; 320 uint32_t md_buf_addr_lsw; 321 uint32_t md_buf_addr_msw; 322 uint32_t md_mem_map_handle; 323 uint32_t md_size; 324} __packed; 325 326#define PARAM_ID_RD_SH_MEM_CFG 0x08001007 327 328struct param_id_rd_sh_mem_cfg { 329 uint32_t num_frames_per_buffer; 330 uint32_t metadata_control_flags; 331 332} __packed; 333 334#define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 335 336struct data_cmd_wr_sh_mem_ep_eos_rendered { 337 uint32_t module_instance_id; 338 uint32_t render_status; 339} __packed; 340 341#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 342 343struct apm_cmd_header { 344 uint32_t payload_address_lsw; 345 uint32_t payload_address_msw; 346 uint32_t mem_map_handle; 347 uint32_t payload_size; 348} __packed; 349 350#define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 351 352struct apm_module_param_data { 353 uint32_t module_instance_id; 354 uint32_t param_id; 355 uint32_t param_size; 356 uint32_t error_code; 357} __packed; 358 359#define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 360 361struct apm_module_param_shared_data { 362 uint32_t param_id; 363 uint32_t param_size; 364} __packed; 365 366struct apm_prop_data { 367 uint32_t prop_id; 368 uint32_t prop_size; 369} __packed; 370 371/* Sub-Graph Properties */ 372#define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 373 374struct apm_param_id_sub_graph_cfg { 375 uint32_t num_sub_graphs; 376} __packed; 377 378struct apm_sub_graph_cfg { 379 uint32_t sub_graph_id; 380 uint32_t num_sub_graph_prop; 381} __packed; 382 383#define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 384 385struct apm_sg_prop_id_perf_mode { 386 uint32_t perf_mode; 387} __packed; 388 389#define APM_SG_PROP_ID_PERF_MODE_SIZE 4 390 391#define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 392 393struct apm_sg_prop_id_direction { 394 uint32_t direction; 395} __packed; 396 397#define APM_SG_PROP_ID_DIR_SIZE 4 398 399#define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 400#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 401#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 402#define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 403 404struct apm_sg_prop_id_scenario_id { 405 uint32_t scenario_id; 406} __packed; 407 408#define APM_SG_PROP_ID_SID_SIZE 4 409/* container api */ 410#define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 411 412struct apm_param_id_container_cfg { 413 uint32_t num_containers; 414} __packed; 415 416struct apm_container_cfg { 417 uint32_t container_id; 418 uint32_t num_prop; 419} __packed; 420 421struct apm_cont_capability { 422 uint32_t capability_id; 423} __packed; 424 425#define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 426#define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 427 428#define APM_PROP_ID_INVALID 0x0 429#define APM_CONTAINER_CAP_ID_PP 0x1 430#define APM_CONTAINER_CAP_ID_PP 0x1 431 432struct apm_cont_prop_id_cap_list { 433 uint32_t num_capability_id; 434} __packed; 435 436#define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 437 438struct apm_cont_prop_id_graph_pos { 439 uint32_t graph_pos; 440} __packed; 441 442#define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 443 444struct apm_cont_prop_id_stack_size { 445 uint32_t stack_size; 446} __packed; 447 448#define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 449 450struct apm_cont_prop_id_domain { 451 uint32_t proc_domain; 452} __packed; 453 454#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 455#define CONFIG_I2S_WS_SRC_INTERNAL 0x1 456 457#define PARAM_ID_I2S_INTF_CFG 0x08001019 458struct param_id_i2s_intf_cfg { 459 uint32_t lpaif_type; 460 uint32_t intf_idx; 461 uint16_t sd_line_idx; 462 uint16_t ws_src; 463} __packed; 464 465#define I2S_INTF_TYPE_PRIMARY 0 466#define I2S_INTF_TYPE_SECOINDARY 1 467#define I2S_INTF_TYPE_TERTINARY 2 468#define I2S_INTF_TYPE_QUATERNARY 3 469#define I2S_INTF_TYPE_QUINARY 4 470#define I2S_SD0 1 471#define I2S_SD1 2 472#define I2S_SD2 3 473#define I2S_SD3 4 474 475#define PORT_ID_I2S_INPUT 2 476#define PORT_ID_I2S_OUPUT 1 477#define I2S_STACK_SIZE 2048 478 479#define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 480 481struct param_id_display_port_intf_cfg { 482 uint32_t channel_allocation; 483 /* Multi-Steam Transport index */ 484 uint32_t mst_idx; 485 uint32_t dptx_idx; 486} __packed; 487 488#define PARAM_ID_HW_EP_MF_CFG 0x08001017 489struct param_id_hw_ep_mf { 490 uint32_t sample_rate; 491 uint16_t bit_width; 492 uint16_t num_channels; 493 uint32_t data_format; 494} __packed; 495 496#define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 497 498struct param_id_fram_size_factor { 499 uint32_t frame_size_factor; 500} __packed; 501 502#define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 503 504struct apm_cont_prop_id_parent_container { 505 uint32_t parent_container_id; 506} __packed; 507 508#define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 509#define APM_CONT_HEAP_DEFAULT 0x1 510#define APM_CONT_HEAP_LOW_POWER 0x2 511 512struct apm_cont_prop_id_headp_id { 513 uint32_t heap_id; 514} __packed; 515 516struct apm_modules_list { 517 uint32_t sub_graph_id; 518 uint32_t container_id; 519 uint32_t num_modules; 520} __packed; 521 522struct apm_module_obj { 523 uint32_t module_id; 524 uint32_t instance_id; 525} __packed; 526 527#define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 528#define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 529struct apm_module_prop_id_port_info { 530 uint32_t max_ip_port; 531 uint32_t max_op_port; 532} __packed; 533 534#define DATA_LOGGING_MAX_INPUT_PORTS 0x1 535#define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 536#define DATA_LOGGING_STACK_SIZE 2048 537#define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 538 539struct data_logging_config { 540 uint32_t log_code; 541 uint32_t log_tap_point_id; 542 uint32_t mode; 543} __packed; 544 545#define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 546struct param_id_sal_output_config { 547 uint32_t bits_per_sample; 548} __packed; 549 550#define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 551struct param_id_sal_limiter_enable { 552 uint32_t enable_lim; 553} __packed; 554 555#define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 556#define PARAM_ID_EARLY_EOS_DELAY 0x0800114C 557#define EARLY_EOS_DELAY_MS 150 558 559struct param_id_mfc_media_format { 560 uint32_t sample_rate; 561 uint16_t bit_width; 562 uint16_t num_channels; 563 uint16_t channel_mapping[]; 564} __packed; 565 566struct param_id_gapless_early_eos_delay_t { 567 uint32_t early_eos_delay_ms; 568} __packed; 569 570struct media_format { 571 uint32_t data_format; 572 uint32_t fmt_id; 573 uint32_t payload_size; 574} __packed; 575 576struct payload_media_fmt_pcm { 577 uint32_t sample_rate; 578 uint16_t bit_width; 579 uint16_t alignment; 580 uint16_t bits_per_sample; 581 uint16_t q_factor; 582 uint16_t endianness; 583 uint16_t num_channels; 584 uint8_t channel_mapping[]; 585} __packed; 586 587#define PARAM_ID_MODULE_ENABLE 0x08001026 588struct param_id_module_enable { 589 uint32_t enable; 590} __packed; 591 592#define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 593 594struct param_id_codec_dma_intf_cfg { 595 /* 1 - RXTX 596 * 2 - WSA 597 * 3 - VA 598 * 4 - AXI 599 */ 600 uint32_t lpaif_type; 601 /* 602 * RX0 | TX0 = 1 603 * RX1 | TX1 = 2 604 * RX2 | TX2 = 3... so on 605 */ 606 uint32_t intf_index; 607 uint32_t active_channels_mask; 608} __packed; 609 610struct audio_hw_clk_cfg { 611 uint32_t clock_id; 612 uint32_t clock_freq; 613 uint32_t clock_attri; 614 uint32_t clock_root; 615} __packed; 616 617struct audio_hw_clk_rel_cfg { 618 uint32_t clock_id; 619} __packed; 620 621#define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 622#define AR_HW_EP_POWER_MODE_0 0 /* default */ 623#define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 624#define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 625 626struct param_id_hw_ep_power_mode_cfg { 627 uint32_t power_mode; 628} __packed; 629 630#define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 631#define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 632#define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 633#define AR_PCM_MAX_NUM_CHANNEL 8 634 635struct param_id_hw_ep_dma_data_align { 636 uint32_t dma_data_align; 637} __packed; 638 639#define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 640#define VOL_CTRL_DEFAULT_GAIN 0x2000 641 642struct param_id_vol_ctrl_master_gain { 643 uint16_t master_gain; 644 uint16_t reserved; 645} __packed; 646 647 648#define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B 649#define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D 650 651#define PARAM_ID_REAL_MODULE_ID 0x0800100B 652 653struct param_id_placeholder_real_module_id { 654 uint32_t real_module_id; 655} __packed; 656 657/* Graph */ 658struct audioreach_connection { 659 /* Connections */ 660 uint32_t src_mod_inst_id; 661 uint32_t src_mod_op_port_id; 662 uint32_t dst_mod_inst_id; 663 uint32_t dst_mod_ip_port_id; 664 struct list_head node; 665}; 666 667struct audioreach_graph_info { 668 int id; 669 uint32_t num_sub_graphs; 670 struct list_head sg_list; 671 /* DPCM connection from FE Graph to BE graph */ 672 uint32_t src_mod_inst_id; 673 uint32_t src_mod_op_port_id; 674 uint32_t dst_mod_inst_id; 675 uint32_t dst_mod_ip_port_id; 676}; 677 678struct audioreach_sub_graph { 679 uint32_t sub_graph_id; 680 uint32_t perf_mode; 681 uint32_t direction; 682 uint32_t scenario_id; 683 struct list_head node; 684 685 struct audioreach_graph_info *info; 686 uint32_t num_containers; 687 struct list_head container_list; 688}; 689 690struct audioreach_container { 691 uint32_t container_id; 692 uint32_t capability_id; 693 uint32_t graph_pos; 694 uint32_t stack_size; 695 uint32_t proc_domain; 696 struct list_head node; 697 698 uint32_t num_modules; 699 struct list_head modules_list; 700 struct audioreach_sub_graph *sub_graph; 701}; 702 703#define AR_MAX_MOD_LINKS 8 704 705struct audioreach_module { 706 uint32_t module_id; 707 uint32_t instance_id; 708 709 uint32_t max_ip_port; 710 uint32_t max_op_port; 711 712 uint32_t in_port; 713 uint32_t out_port; 714 715 uint32_t num_connections; 716 /* Connections */ 717 uint32_t src_mod_inst_id; 718 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 719 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 720 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 721 722 /* Format specifics */ 723 uint32_t ch_fmt; 724 uint32_t rate; 725 uint32_t bit_depth; 726 727 /* I2S module */ 728 uint32_t hw_interface_idx; 729 uint32_t sd_line_idx; 730 uint32_t ws_src; 731 uint32_t frame_size_factor; 732 uint32_t data_format; 733 uint32_t hw_interface_type; 734 735 /* PCM module specific */ 736 uint32_t interleave_type; 737 738 /* GAIN/Vol Control Module */ 739 uint16_t gain; 740 741 /* Logging */ 742 uint32_t log_code; 743 uint32_t log_tap_point_id; 744 uint32_t log_mode; 745 746 /* bookkeeping */ 747 struct list_head node; 748 struct audioreach_container *container; 749 struct snd_soc_dapm_widget *widget; 750}; 751 752struct audioreach_module_config { 753 int direction; 754 u32 sample_rate; 755 u16 bit_width; 756 u16 bits_per_sample; 757 758 u16 data_format; 759 u16 num_channels; 760 u16 active_channels_mask; 761 u16 dp_idx; 762 u32 channel_allocation; 763 u32 sd_line_mask; 764 int fmt; 765 struct snd_codec codec; 766 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 767}; 768 769/* Packet Allocation routines */ 770void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 771 token); 772void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 773 uint32_t token, uint32_t src_port, 774 uint32_t dest_port); 775void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 776 uint32_t src_port); 777void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 778 uint32_t token, uint32_t src_port, 779 uint32_t dest_port); 780void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 781 *info); 782/* Topology specific */ 783int audioreach_tplg_init(struct snd_soc_component *component); 784 785/* Module specific */ 786void audioreach_graph_free_buf(struct q6apm_graph *graph); 787int audioreach_map_memory_regions(struct q6apm_graph *graph, 788 unsigned int dir, size_t period_sz, 789 unsigned int periods, 790 bool is_contiguous); 791int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 792 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 793 struct gpr_pkt *pkt, uint32_t rsp_opcode); 794int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 795 uint32_t rsp_opcode); 796int audioreach_set_media_format(struct q6apm_graph *graph, 797 struct audioreach_module *module, 798 struct audioreach_module_config *cfg); 799int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 800int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 801 struct audioreach_module *module, int vol); 802int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module, 803 uint32_t param_id, uint32_t param_val); 804int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg); 805 806#endif /* __AUDIOREACH_H__ */ 807