162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * mt8188-audsys-clk.h -- MediaTek 8188 audsys clock definition 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2022 MediaTek Inc. 662306a36Sopenharmony_ci * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#ifndef _MT8188_AUDSYS_CLK_H_ 1062306a36Sopenharmony_ci#define _MT8188_AUDSYS_CLK_H_ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciint mt8188_audsys_clk_register(struct mtk_base_afe *afe); 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#endif 15