1// SPDX-License-Identifier: GPL-2.0 2/* 3 * mt8188-audsys-clk.c -- MediaTek 8188 audsys clock control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 7 */ 8 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/clkdev.h> 12#include "mt8188-afe-common.h" 13#include "mt8188-audsys-clk.h" 14#include "mt8188-audsys-clkid.h" 15#include "mt8188-reg.h" 16 17struct afe_gate { 18 int id; 19 const char *name; 20 const char *parent_name; 21 int reg; 22 u8 bit; 23 const struct clk_ops *ops; 24 unsigned long flags; 25 u8 cg_flags; 26}; 27 28#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 29 .id = _id, \ 30 .name = _name, \ 31 .parent_name = _parent, \ 32 .reg = _reg, \ 33 .bit = _bit, \ 34 .flags = _flags, \ 35 .cg_flags = _cgflags, \ 36 } 37 38#define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \ 40 CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE) 41 42#define GATE_AUD0(_id, _name, _parent, _bit) \ 43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit) 44 45#define GATE_AUD1(_id, _name, _parent, _bit) \ 46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit) 47 48#define GATE_AUD3(_id, _name, _parent, _bit) \ 49 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit) 50 51#define GATE_AUD4(_id, _name, _parent, _bit) \ 52 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit) 53 54#define GATE_AUD5(_id, _name, _parent, _bit) \ 55 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit) 56 57#define GATE_AUD6(_id, _name, _parent, _bit) \ 58 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit) 59 60static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = { 61 /* AUD0 */ 62 GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2), 63 GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4), 64 GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10), 65 GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11), 66 GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18), 67 GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19), 68 GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20), 69 GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21), 70 GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23), 71 GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24), 72 GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25), 73 GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26), 74 GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27), 75 GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28), 76 GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31), 77 78 /* AUD1 */ 79 GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2), 80 GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10), 81 GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11), 82 GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12), 83 GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13), 84 GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14), 85 GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16), 86 GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17), 87 88 /* AUD3 */ 89 GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5), 90 GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7), 91 92 /* AUD4 */ 93 GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0), 94 GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1), 95 GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6), 96 GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7), 97 GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8), 98 GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16), 99 GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17), 100 GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19), 101 GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20), 102 GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21), 103 GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys", 22), 104 GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24), 105 GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys", 30), 106 GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys", 31), 107 108 /* AUD5 */ 109 GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0), 110 GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1), 111 GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2), 112 GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3), 113 GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4), 114 GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5), 115 GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7), 116 GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8), 117 GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9), 118 GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18), 119 GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19), 120 GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22), 121 GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23), 122 GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24), 123 GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26), 124 GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27), 125 126 /* AUD6 */ 127 GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0), 128 GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1), 129 GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2), 130 GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3), 131 GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4), 132 GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5), 133 GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6), 134 GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7), 135 GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8), 136 GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9), 137 GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10), 138 GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11), 139}; 140 141static void mt8188_audsys_clk_unregister(void *data) 142{ 143 struct mtk_base_afe *afe = data; 144 struct mt8188_afe_private *afe_priv = afe->platform_priv; 145 struct clk *clk; 146 struct clk_lookup *cl; 147 int i; 148 149 if (!afe_priv) 150 return; 151 152 for (i = 0; i < CLK_AUD_NR_CLK; i++) { 153 cl = afe_priv->lookup[i]; 154 if (!cl) 155 continue; 156 157 clk = cl->clk; 158 clk_unregister_gate(clk); 159 160 clkdev_drop(cl); 161 } 162} 163 164int mt8188_audsys_clk_register(struct mtk_base_afe *afe) 165{ 166 struct mt8188_afe_private *afe_priv = afe->platform_priv; 167 struct clk *clk; 168 struct clk_lookup *cl; 169 int i; 170 171 afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK, 172 sizeof(*afe_priv->lookup), 173 GFP_KERNEL); 174 175 if (!afe_priv->lookup) 176 return -ENOMEM; 177 178 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 179 const struct afe_gate *gate = &aud_clks[i]; 180 181 clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 182 gate->flags, afe->base_addr + gate->reg, 183 gate->bit, gate->cg_flags, NULL); 184 185 if (IS_ERR(clk)) { 186 dev_err(afe->dev, "Failed to register clk %s: %ld\n", 187 gate->name, PTR_ERR(clk)); 188 continue; 189 } 190 191 /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */ 192 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 193 if (!cl) 194 return -ENOMEM; 195 196 cl->clk = clk; 197 cl->con_id = gate->name; 198 cl->dev_id = dev_name(afe->dev); 199 cl->clk_hw = NULL; 200 clkdev_add(cl); 201 202 afe_priv->lookup[i] = cl; 203 } 204 205 return devm_add_action_or_reset(afe->dev, mt8188_audsys_clk_unregister, afe); 206} 207