1// SPDX-License-Identifier: GPL-2.0
2//
3// mt8186-audsys-clk.h  --  Mediatek 8186 audsys clock control
4//
5// Copyright (c) 2022 MediaTek Inc.
6// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/clkdev.h>
11#include "mt8186-afe-common.h"
12#include "mt8186-audsys-clk.h"
13#include "mt8186-audsys-clkid.h"
14#include "mt8186-reg.h"
15
16struct afe_gate {
17	int id;
18	const char *name;
19	const char *parent_name;
20	int reg;
21	u8 bit;
22	const struct clk_ops *ops;
23	unsigned long flags;
24	u8 cg_flags;
25};
26
27#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
28		.id = _id,					\
29		.name = _name,					\
30		.parent_name = _parent,				\
31		.reg = _reg,					\
32		.bit = _bit,					\
33		.flags = _flags,				\
34		.cg_flags = _cgflags,				\
35	}
36
37#define GATE_AFE(_id, _name, _parent, _reg, _bit)		\
38	GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,		\
39		       CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
40
41#define GATE_AUD0(_id, _name, _parent, _bit)			\
42	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
43
44#define GATE_AUD1(_id, _name, _parent, _bit)			\
45	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
46
47#define GATE_AUD2(_id, _name, _parent, _bit)			\
48	GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
49
50static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
51	/* AUD0 */
52	GATE_AUD0(CLK_AUD_AFE, "aud_afe_clk", "top_audio", 2),
53	GATE_AUD0(CLK_AUD_22M, "aud_apll22m_clk", "top_aud_engen1", 8),
54	GATE_AUD0(CLK_AUD_24M, "aud_apll24m_clk", "top_aud_engen2", 9),
55	GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner_clk", "top_aud_engen2", 18),
56	GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner_clk", "top_aud_engen1", 19),
57	GATE_AUD0(CLK_AUD_TDM, "aud_tdm_clk", "top_aud_1", 20),
58	GATE_AUD0(CLK_AUD_ADC, "aud_adc_clk", "top_audio", 24),
59	GATE_AUD0(CLK_AUD_DAC, "aud_dac_clk", "top_audio", 25),
60	GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis_clk", "top_audio", 26),
61	GATE_AUD0(CLK_AUD_TML, "aud_tml_clk", "top_audio", 27),
62	GATE_AUD0(CLK_AUD_NLE, "aud_nle_clk", "top_audio", 28),
63
64	/* AUD1 */
65	GATE_AUD1(CLK_AUD_I2S1_BCLK, "aud_i2s1_bclk", "top_audio", 4),
66	GATE_AUD1(CLK_AUD_I2S2_BCLK, "aud_i2s2_bclk", "top_audio", 5),
67	GATE_AUD1(CLK_AUD_I2S3_BCLK, "aud_i2s3_bclk", "top_audio", 6),
68	GATE_AUD1(CLK_AUD_I2S4_BCLK, "aud_i2s4_bclk", "top_audio", 7),
69	GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "top_audio", 12),
70	GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "top_audio", 13),
71	GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "top_audio", 14),
72	GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires_clk", "top_audio_h", 15),
73	GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires_clk", "top_audio_h", 16),
74	GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "top_audio_h", 17),
75	GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_audio", 20),
76	GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 21),
77	GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "top_audio", 28),
78	GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "top_audio", 29),
79	GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "top_audio", 30),
80	GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "top_audio_h", 31),
81
82	/* AUD2 */
83	GATE_AUD2(CLK_AUD_ETDM_IN1_BCLK, "aud_etdm_in1_bclk", "top_audio", 23),
84	GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24),
85};
86
87static void mt8186_audsys_clk_unregister(void *data)
88{
89	struct mtk_base_afe *afe = data;
90	struct mt8186_afe_private *afe_priv = afe->platform_priv;
91	struct clk *clk;
92	struct clk_lookup *cl;
93	int i;
94
95	if (!afe_priv)
96		return;
97
98	for (i = 0; i < CLK_AUD_NR_CLK; i++) {
99		cl = afe_priv->lookup[i];
100		if (!cl)
101			continue;
102
103		clk = cl->clk;
104		clk_unregister_gate(clk);
105
106		clkdev_drop(cl);
107	}
108}
109
110int mt8186_audsys_clk_register(struct mtk_base_afe *afe)
111{
112	struct mt8186_afe_private *afe_priv = afe->platform_priv;
113	struct clk *clk;
114	struct clk_lookup *cl;
115	int i;
116
117	afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
118					sizeof(*afe_priv->lookup),
119					GFP_KERNEL);
120
121	if (!afe_priv->lookup)
122		return -ENOMEM;
123
124	for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
125		const struct afe_gate *gate = &aud_clks[i];
126
127		clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
128					gate->flags, afe->base_addr + gate->reg,
129					gate->bit, gate->cg_flags, NULL);
130
131		if (IS_ERR(clk)) {
132			dev_err(afe->dev, "Failed to register clk %s: %ld\n",
133				gate->name, PTR_ERR(clk));
134			continue;
135		}
136
137		/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
138		cl = kzalloc(sizeof(*cl), GFP_KERNEL);
139		if (!cl)
140			return -ENOMEM;
141
142		cl->clk = clk;
143		cl->con_id = gate->name;
144		cl->dev_id = dev_name(afe->dev);
145		clkdev_add(cl);
146
147		afe_priv->lookup[i] = cl;
148	}
149
150	return devm_add_action_or_reset(afe->dev, mt8186_audsys_clk_unregister, afe);
151}
152
153