162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * mt2701-afe-clock-ctrl.h -- Mediatek 2701 afe clock ctrl definition 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2016 MediaTek Inc. 662306a36Sopenharmony_ci * Author: Garlic Tseng <garlic.tseng@mediatek.com> 762306a36Sopenharmony_ci * Ryder Lee <ryder.lee@mediatek.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef _MT2701_AFE_CLOCK_CTRL_H_ 1162306a36Sopenharmony_ci#define _MT2701_AFE_CLOCK_CTRL_H_ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cistruct mtk_base_afe; 1462306a36Sopenharmony_cistruct mt2701_i2s_path; 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciint mt2701_init_clock(struct mtk_base_afe *afe); 1762306a36Sopenharmony_ciint mt2701_afe_enable_clock(struct mtk_base_afe *afe); 1862306a36Sopenharmony_ciint mt2701_afe_disable_clock(struct mtk_base_afe *afe); 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciint mt2701_afe_enable_i2s(struct mtk_base_afe *afe, 2162306a36Sopenharmony_ci struct mt2701_i2s_path *i2s_path, 2262306a36Sopenharmony_ci int dir); 2362306a36Sopenharmony_civoid mt2701_afe_disable_i2s(struct mtk_base_afe *afe, 2462306a36Sopenharmony_ci struct mt2701_i2s_path *i2s_path, 2562306a36Sopenharmony_ci int dir); 2662306a36Sopenharmony_ciint mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id); 2762306a36Sopenharmony_civoid mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id); 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ciint mt2701_enable_btmrg_clk(struct mtk_base_afe *afe); 3062306a36Sopenharmony_civoid mt2701_disable_btmrg_clk(struct mtk_base_afe *afe); 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ciint mt2701_mclk_configuration(struct mtk_base_afe *afe, int id); 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#endif 35