1// SPDX-License-Identifier: GPL-2.0 2// 3// Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4// 5// Copyright (C) 2013 Freescale Semiconductor, Inc. 6// 7// Based on stmp3xxx_spdif_dai.c 8// Vladimir Barinov <vbarinov@embeddedalley.com> 9// Copyright 2008 SigmaTel, Inc 10// Copyright 2008 Embedded Alley Solutions, Inc 11 12#include <linux/bitrev.h> 13#include <linux/clk.h> 14#include <linux/module.h> 15#include <linux/of_address.h> 16#include <linux/of_device.h> 17#include <linux/of_irq.h> 18#include <linux/regmap.h> 19#include <linux/pm_runtime.h> 20 21#include <sound/asoundef.h> 22#include <sound/dmaengine_pcm.h> 23#include <sound/soc.h> 24 25#include "fsl_spdif.h" 26#include "fsl_utils.h" 27#include "imx-pcm.h" 28 29#define FSL_SPDIF_TXFIFO_WML 0x8 30#define FSL_SPDIF_RXFIFO_WML 0x8 31 32#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 33#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 34 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 35 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 36 INT_LOSS_LOCK | INT_DPLL_LOCKED) 37 38#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 39 40/* Index list for the values that has if (DPLL Locked) condition */ 41static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 42#define SRPC_NODPLL_START1 0x5 43#define SRPC_NODPLL_START2 0xc 44 45#define DEFAULT_RXCLK_SRC 1 46 47#define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate" 48 49/** 50 * struct fsl_spdif_soc_data: soc specific data 51 * 52 * @imx: for imx platform 53 * @shared_root_clock: flag of sharing a clock source with others; 54 * so the driver shouldn't set root clock rate 55 * @raw_capture_mode: if raw capture mode support 56 * @cchannel_192b: if there are registers for 192bits C channel data 57 * @interrupts: interrupt number 58 * @tx_burst: tx maxburst size 59 * @rx_burst: rx maxburst size 60 * @tx_formats: tx supported data format 61 */ 62struct fsl_spdif_soc_data { 63 bool imx; 64 bool shared_root_clock; 65 bool raw_capture_mode; 66 bool cchannel_192b; 67 u32 interrupts; 68 u32 tx_burst; 69 u32 rx_burst; 70 u64 tx_formats; 71}; 72 73/* 74 * SPDIF control structure 75 * Defines channel status, subcode and Q sub 76 */ 77struct spdif_mixer_control { 78 /* spinlock to access control data */ 79 spinlock_t ctl_lock; 80 81 /* IEC958 channel tx status bit */ 82 unsigned char ch_status[4]; 83 84 /* User bits */ 85 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 86 87 /* Q subcode part of user bits */ 88 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 89 90 /* Buffer offset for U/Q */ 91 u32 upos; 92 u32 qpos; 93 94 /* Ready buffer index of the two buffers */ 95 u32 ready_buf; 96}; 97 98/** 99 * struct fsl_spdif_priv - Freescale SPDIF private data 100 * @soc: SPDIF soc data 101 * @fsl_spdif_control: SPDIF control data 102 * @cpu_dai_drv: cpu dai driver 103 * @snd_card: sound card pointer 104 * @rxrate_kcontrol: kcontrol for RX Sample Rate 105 * @pdev: platform device pointer 106 * @regmap: regmap handler 107 * @dpll_locked: dpll lock flag 108 * @txrate: the best rates for playback 109 * @txclk_df: STC_TXCLK_DF dividers value for playback 110 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 111 * @txclk_src: STC_TXCLK_SRC values for playback 112 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 113 * @txclk: tx clock sources for playback 114 * @rxclk: rx clock sources for capture 115 * @coreclk: core clock for register access via DMA 116 * @sysclk: system clock for rx clock rate measurement 117 * @spbaclk: SPBA clock (optional, depending on SoC design) 118 * @dma_params_tx: DMA parameters for transmit channel 119 * @dma_params_rx: DMA parameters for receive channel 120 * @regcache_srpc: regcache for SRPC 121 * @bypass: status of bypass input to output 122 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz 123 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz 124 */ 125struct fsl_spdif_priv { 126 const struct fsl_spdif_soc_data *soc; 127 struct spdif_mixer_control fsl_spdif_control; 128 struct snd_soc_dai_driver cpu_dai_drv; 129 struct snd_card *snd_card; 130 struct snd_kcontrol *rxrate_kcontrol; 131 struct platform_device *pdev; 132 struct regmap *regmap; 133 bool dpll_locked; 134 u32 txrate[SPDIF_TXRATE_MAX]; 135 u8 txclk_df[SPDIF_TXRATE_MAX]; 136 u16 sysclk_df[SPDIF_TXRATE_MAX]; 137 u8 txclk_src[SPDIF_TXRATE_MAX]; 138 u8 rxclk_src; 139 struct clk *txclk[STC_TXCLK_SRC_MAX]; 140 struct clk *rxclk; 141 struct clk *coreclk; 142 struct clk *sysclk; 143 struct clk *spbaclk; 144 struct snd_dmaengine_dai_dma_data dma_params_tx; 145 struct snd_dmaengine_dai_dma_data dma_params_rx; 146 /* regcache for SRPC */ 147 u32 regcache_srpc; 148 bool bypass; 149 struct clk *pll8k_clk; 150 struct clk *pll11k_clk; 151}; 152 153static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 154 .imx = false, 155 .shared_root_clock = false, 156 .raw_capture_mode = false, 157 .interrupts = 1, 158 .tx_burst = FSL_SPDIF_TXFIFO_WML, 159 .rx_burst = FSL_SPDIF_RXFIFO_WML, 160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 161}; 162 163static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 164 .imx = true, 165 .shared_root_clock = false, 166 .raw_capture_mode = false, 167 .interrupts = 1, 168 .tx_burst = FSL_SPDIF_TXFIFO_WML, 169 .rx_burst = FSL_SPDIF_RXFIFO_WML, 170 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 171}; 172 173static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 174 .imx = true, 175 .shared_root_clock = true, 176 .raw_capture_mode = false, 177 .interrupts = 1, 178 .tx_burst = FSL_SPDIF_TXFIFO_WML, 179 .rx_burst = FSL_SPDIF_RXFIFO_WML, 180 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 181 182}; 183 184static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 185 .imx = true, 186 .shared_root_clock = true, 187 .raw_capture_mode = false, 188 .interrupts = 2, 189 .tx_burst = 2, /* Applied for EDMA */ 190 .rx_burst = 2, /* Applied for EDMA */ 191 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 192}; 193 194static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 195 .imx = true, 196 .shared_root_clock = false, 197 .raw_capture_mode = true, 198 .interrupts = 1, 199 .tx_burst = FSL_SPDIF_TXFIFO_WML, 200 .rx_burst = FSL_SPDIF_RXFIFO_WML, 201 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 202}; 203 204static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = { 205 .imx = true, 206 .shared_root_clock = true, 207 .raw_capture_mode = false, 208 .interrupts = 1, 209 .tx_burst = 2, /* Applied for EDMA */ 210 .rx_burst = 2, /* Applied for EDMA */ 211 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 212 .cchannel_192b = true, 213}; 214 215/* Check if clk is a root clock that does not share clock source with others */ 216static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 217{ 218 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 219} 220 221/* DPLL locked and lock loss interrupt handler */ 222static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 223{ 224 struct regmap *regmap = spdif_priv->regmap; 225 struct platform_device *pdev = spdif_priv->pdev; 226 u32 locked; 227 228 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 229 locked &= SRPC_DPLL_LOCKED; 230 231 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 232 locked ? "locked" : "loss lock"); 233 234 spdif_priv->dpll_locked = locked ? true : false; 235 236 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) { 237 snd_ctl_notify(spdif_priv->snd_card, 238 SNDRV_CTL_EVENT_MASK_VALUE, 239 &spdif_priv->rxrate_kcontrol->id); 240 } 241} 242 243/* Receiver found illegal symbol interrupt handler */ 244static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 245{ 246 struct regmap *regmap = spdif_priv->regmap; 247 struct platform_device *pdev = spdif_priv->pdev; 248 249 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 250 251 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 252 if (!spdif_priv->dpll_locked) 253 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 254} 255 256/* U/Q Channel receive register full */ 257static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 258{ 259 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 260 struct regmap *regmap = spdif_priv->regmap; 261 struct platform_device *pdev = spdif_priv->pdev; 262 u32 *pos, size, val, reg; 263 264 switch (name) { 265 case 'U': 266 pos = &ctrl->upos; 267 size = SPDIF_UBITS_SIZE; 268 reg = REG_SPDIF_SRU; 269 break; 270 case 'Q': 271 pos = &ctrl->qpos; 272 size = SPDIF_QSUB_SIZE; 273 reg = REG_SPDIF_SRQ; 274 break; 275 default: 276 dev_err(&pdev->dev, "unsupported channel name\n"); 277 return; 278 } 279 280 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 281 282 if (*pos >= size * 2) { 283 *pos = 0; 284 } else if (unlikely((*pos % size) + 3 > size)) { 285 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 286 return; 287 } 288 289 regmap_read(regmap, reg, &val); 290 ctrl->subcode[*pos++] = val >> 16; 291 ctrl->subcode[*pos++] = val >> 8; 292 ctrl->subcode[*pos++] = val; 293} 294 295/* U/Q Channel sync found */ 296static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 297{ 298 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 299 struct platform_device *pdev = spdif_priv->pdev; 300 301 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 302 303 /* U/Q buffer reset */ 304 if (ctrl->qpos == 0) 305 return; 306 307 /* Set ready to this buffer */ 308 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 309} 310 311/* U/Q Channel framing error */ 312static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 313{ 314 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 315 struct regmap *regmap = spdif_priv->regmap; 316 struct platform_device *pdev = spdif_priv->pdev; 317 u32 val; 318 319 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 320 321 /* Read U/Q data to clear the irq and do buffer reset */ 322 regmap_read(regmap, REG_SPDIF_SRU, &val); 323 regmap_read(regmap, REG_SPDIF_SRQ, &val); 324 325 /* Drop this U/Q buffer */ 326 ctrl->ready_buf = 0; 327 ctrl->upos = 0; 328 ctrl->qpos = 0; 329} 330 331/* Get spdif interrupt status and clear the interrupt */ 332static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 333{ 334 struct regmap *regmap = spdif_priv->regmap; 335 u32 val, val2; 336 337 regmap_read(regmap, REG_SPDIF_SIS, &val); 338 regmap_read(regmap, REG_SPDIF_SIE, &val2); 339 340 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 341 342 return val; 343} 344 345static irqreturn_t spdif_isr(int irq, void *devid) 346{ 347 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 348 struct platform_device *pdev = spdif_priv->pdev; 349 u32 sis; 350 351 sis = spdif_intr_status_clear(spdif_priv); 352 353 if (sis & INT_DPLL_LOCKED) 354 spdif_irq_dpll_lock(spdif_priv); 355 356 if (sis & INT_TXFIFO_UNOV) 357 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 358 359 if (sis & INT_TXFIFO_RESYNC) 360 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 361 362 if (sis & INT_CNEW) 363 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 364 365 if (sis & INT_VAL_NOGOOD) 366 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 367 368 if (sis & INT_SYM_ERR) 369 spdif_irq_sym_error(spdif_priv); 370 371 if (sis & INT_BIT_ERR) 372 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 373 374 if (sis & INT_URX_FUL) 375 spdif_irq_uqrx_full(spdif_priv, 'U'); 376 377 if (sis & INT_URX_OV) 378 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 379 380 if (sis & INT_QRX_FUL) 381 spdif_irq_uqrx_full(spdif_priv, 'Q'); 382 383 if (sis & INT_QRX_OV) 384 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 385 386 if (sis & INT_UQ_SYNC) 387 spdif_irq_uq_sync(spdif_priv); 388 389 if (sis & INT_UQ_ERR) 390 spdif_irq_uq_err(spdif_priv); 391 392 if (sis & INT_RXFIFO_UNOV) 393 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 394 395 if (sis & INT_RXFIFO_RESYNC) 396 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 397 398 if (sis & INT_LOSS_LOCK) 399 spdif_irq_dpll_lock(spdif_priv); 400 401 /* FIXME: Write Tx FIFO to clear TxEm */ 402 if (sis & INT_TX_EM) 403 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 404 405 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 406 if (sis & INT_RXFIFO_FUL) 407 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 408 409 return IRQ_HANDLED; 410} 411 412static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 413{ 414 struct regmap *regmap = spdif_priv->regmap; 415 u32 val, cycle = 1000; 416 417 regcache_cache_bypass(regmap, true); 418 419 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 420 421 /* 422 * RESET bit would be cleared after finishing its reset procedure, 423 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 424 */ 425 do { 426 regmap_read(regmap, REG_SPDIF_SCR, &val); 427 } while ((val & SCR_SOFT_RESET) && cycle--); 428 429 regcache_cache_bypass(regmap, false); 430 regcache_mark_dirty(regmap); 431 regcache_sync(regmap); 432 433 if (cycle) 434 return 0; 435 else 436 return -EBUSY; 437} 438 439static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 440 u8 mask, u8 cstatus) 441{ 442 ctrl->ch_status[3] &= ~mask; 443 ctrl->ch_status[3] |= cstatus & mask; 444} 445 446static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 447{ 448 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 449 struct regmap *regmap = spdif_priv->regmap; 450 struct platform_device *pdev = spdif_priv->pdev; 451 u32 ch_status; 452 453 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 454 (bitrev8(ctrl->ch_status[1]) << 8) | 455 bitrev8(ctrl->ch_status[2]); 456 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 457 458 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 459 460 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 461 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 462 463 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 464 465 if (spdif_priv->soc->cchannel_192b) { 466 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | 467 (bitrev8(ctrl->ch_status[1]) << 16) | 468 (bitrev8(ctrl->ch_status[2]) << 8) | 469 bitrev8(ctrl->ch_status[3]); 470 471 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000); 472 473 /* 474 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register, 475 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP 476 * then can get correct result with HDMI analyzer capture. 477 * There is a hardware bug here. 478 */ 479 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status); 480 } 481} 482 483/* Set SPDIF PhaseConfig register for rx clock */ 484static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 485 enum spdif_gainsel gainsel, int dpll_locked) 486{ 487 struct regmap *regmap = spdif_priv->regmap; 488 u8 clksrc = spdif_priv->rxclk_src; 489 490 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 491 return -EINVAL; 492 493 regmap_update_bits(regmap, REG_SPDIF_SRPC, 494 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 495 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 496 497 return 0; 498} 499 500static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index); 501 502static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 503 int sample_rate) 504{ 505 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 506 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 507 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 508 struct regmap *regmap = spdif_priv->regmap; 509 struct platform_device *pdev = spdif_priv->pdev; 510 unsigned long csfs = 0; 511 u32 stc, mask, rate; 512 u16 sysclk_df; 513 u8 clk, txclk_df; 514 int ret; 515 516 switch (sample_rate) { 517 case 22050: 518 rate = SPDIF_TXRATE_22050; 519 csfs = IEC958_AES3_CON_FS_22050; 520 break; 521 case 32000: 522 rate = SPDIF_TXRATE_32000; 523 csfs = IEC958_AES3_CON_FS_32000; 524 break; 525 case 44100: 526 rate = SPDIF_TXRATE_44100; 527 csfs = IEC958_AES3_CON_FS_44100; 528 break; 529 case 48000: 530 rate = SPDIF_TXRATE_48000; 531 csfs = IEC958_AES3_CON_FS_48000; 532 break; 533 case 88200: 534 rate = SPDIF_TXRATE_88200; 535 csfs = IEC958_AES3_CON_FS_88200; 536 break; 537 case 96000: 538 rate = SPDIF_TXRATE_96000; 539 csfs = IEC958_AES3_CON_FS_96000; 540 break; 541 case 176400: 542 rate = SPDIF_TXRATE_176400; 543 csfs = IEC958_AES3_CON_FS_176400; 544 break; 545 case 192000: 546 rate = SPDIF_TXRATE_192000; 547 csfs = IEC958_AES3_CON_FS_192000; 548 break; 549 default: 550 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 551 return -EINVAL; 552 } 553 554 ret = fsl_spdif_probe_txclk(spdif_priv, rate); 555 if (ret) 556 return ret; 557 558 clk = spdif_priv->txclk_src[rate]; 559 if (clk >= STC_TXCLK_SRC_MAX) { 560 dev_err(&pdev->dev, "tx clock source is out of range\n"); 561 return -EINVAL; 562 } 563 564 txclk_df = spdif_priv->txclk_df[rate]; 565 if (txclk_df == 0) { 566 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 567 return -EINVAL; 568 } 569 570 sysclk_df = spdif_priv->sysclk_df[rate]; 571 572 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 573 goto clk_set_bypass; 574 575 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 576 ret = clk_set_rate(spdif_priv->txclk[clk], 577 64 * sample_rate * txclk_df); 578 if (ret) { 579 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 580 return ret; 581 } 582 583clk_set_bypass: 584 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 585 (64 * sample_rate * txclk_df * sysclk_df)); 586 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 587 clk_get_rate(spdif_priv->txclk[clk])); 588 589 /* set fs field in consumer channel status */ 590 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 591 592 /* select clock source and divisor */ 593 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 594 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 595 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 596 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 597 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 598 599 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 600 spdif_priv->txrate[rate], sample_rate); 601 602 return 0; 603} 604 605static int fsl_spdif_startup(struct snd_pcm_substream *substream, 606 struct snd_soc_dai *cpu_dai) 607{ 608 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 609 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 610 struct platform_device *pdev = spdif_priv->pdev; 611 struct regmap *regmap = spdif_priv->regmap; 612 u32 scr, mask; 613 int ret; 614 615 /* Reset module and interrupts only for first initialization */ 616 if (!snd_soc_dai_active(cpu_dai)) { 617 ret = spdif_softreset(spdif_priv); 618 if (ret) { 619 dev_err(&pdev->dev, "failed to soft reset\n"); 620 return ret; 621 } 622 623 /* Disable all the interrupts */ 624 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 625 } 626 627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 628 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 629 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 630 SCR_TXFIFO_FSEL_IF8; 631 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 632 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 633 SCR_TXFIFO_FSEL_MASK; 634 } else { 635 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 636 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 637 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 638 } 639 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 640 641 /* Power up SPDIF module */ 642 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 643 644 return 0; 645} 646 647static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 648 struct snd_soc_dai *cpu_dai) 649{ 650 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 651 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 652 struct regmap *regmap = spdif_priv->regmap; 653 u32 scr, mask; 654 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 656 scr = 0; 657 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 658 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 659 SCR_TXFIFO_FSEL_MASK; 660 /* Disable TX clock */ 661 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0); 662 } else { 663 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 664 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 665 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 666 } 667 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 668 669 /* Power down SPDIF module only if tx&rx are both inactive */ 670 if (!snd_soc_dai_active(cpu_dai)) { 671 spdif_intr_status_clear(spdif_priv); 672 regmap_update_bits(regmap, REG_SPDIF_SCR, 673 SCR_LOW_POWER, SCR_LOW_POWER); 674 } 675} 676 677static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate) 678{ 679 struct platform_device *pdev = spdif_priv->pdev; 680 struct clk *clk; 681 int ret; 682 683 /* Reparent clock if required condition is true */ 684 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT)) 685 return 0; 686 687 /* Get root clock */ 688 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; 689 690 /* Disable clock first, for it was enabled by pm_runtime */ 691 clk_disable_unprepare(clk); 692 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, 693 spdif_priv->pll11k_clk, sample_rate); 694 ret = clk_prepare_enable(clk); 695 if (ret) 696 return ret; 697 698 return 0; 699} 700static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 701 struct snd_pcm_hw_params *params, 702 struct snd_soc_dai *dai) 703{ 704 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 705 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 706 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 707 struct platform_device *pdev = spdif_priv->pdev; 708 u32 sample_rate = params_rate(params); 709 int ret = 0; 710 711 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 712 ret = spdif_reparent_rootclk(spdif_priv, sample_rate); 713 if (ret) { 714 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", 715 __func__, sample_rate); 716 return ret; 717 } 718 719 ret = spdif_set_sample_rate(substream, sample_rate); 720 if (ret) { 721 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 722 __func__, sample_rate); 723 return ret; 724 } 725 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 726 IEC958_AES3_CON_CLOCK_1000PPM); 727 spdif_write_channel_status(spdif_priv); 728 } else { 729 /* Setup rx clock source */ 730 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 731 } 732 733 return ret; 734} 735 736static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 737 int cmd, struct snd_soc_dai *dai) 738{ 739 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 740 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 741 struct regmap *regmap = spdif_priv->regmap; 742 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 743 u32 intr = SIE_INTR_FOR(tx); 744 u32 dmaen = SCR_DMA_xX_EN(tx); 745 746 switch (cmd) { 747 case SNDRV_PCM_TRIGGER_START: 748 case SNDRV_PCM_TRIGGER_RESUME: 749 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 750 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 751 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 752 break; 753 case SNDRV_PCM_TRIGGER_STOP: 754 case SNDRV_PCM_TRIGGER_SUSPEND: 755 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 756 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 757 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 758 regmap_write(regmap, REG_SPDIF_STL, 0x0); 759 regmap_write(regmap, REG_SPDIF_STR, 0x0); 760 break; 761 default: 762 return -EINVAL; 763 } 764 765 return 0; 766} 767 768/* 769 * FSL SPDIF IEC958 controller(mixer) functions 770 * 771 * Channel status get/put control 772 * User bit value get/put control 773 * Valid bit value get control 774 * DPLL lock status get control 775 * User bit sync mode selection control 776 */ 777 778static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 779 struct snd_ctl_elem_info *uinfo) 780{ 781 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 782 uinfo->count = 1; 783 784 return 0; 785} 786 787static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 788 struct snd_ctl_elem_value *uvalue) 789{ 790 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 791 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 792 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 793 794 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 795 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 796 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 797 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 798 799 return 0; 800} 801 802static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 803 struct snd_ctl_elem_value *uvalue) 804{ 805 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 806 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 807 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 808 809 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 810 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 811 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 812 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 813 814 spdif_write_channel_status(spdif_priv); 815 816 return 0; 817} 818 819/* Get channel status from SPDIF_RX_CCHAN register */ 820static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 821 struct snd_ctl_elem_value *ucontrol) 822{ 823 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 824 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 825 struct regmap *regmap = spdif_priv->regmap; 826 u32 cstatus, val; 827 828 regmap_read(regmap, REG_SPDIF_SIS, &val); 829 if (!(val & INT_CNEW)) 830 return -EAGAIN; 831 832 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 833 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 834 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 835 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 836 837 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 838 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 839 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 840 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 841 842 /* Clear intr */ 843 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 844 845 return 0; 846} 847 848/* 849 * Get User bits (subcode) from chip value which readed out 850 * in UChannel register. 851 */ 852static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 853 struct snd_ctl_elem_value *ucontrol) 854{ 855 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 856 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 857 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 858 unsigned long flags; 859 int ret = -EAGAIN; 860 861 spin_lock_irqsave(&ctrl->ctl_lock, flags); 862 if (ctrl->ready_buf) { 863 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 864 memcpy(&ucontrol->value.iec958.subcode[0], 865 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 866 ret = 0; 867 } 868 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 869 870 return ret; 871} 872 873/* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 874static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 875 struct snd_ctl_elem_info *uinfo) 876{ 877 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 878 uinfo->count = SPDIF_QSUB_SIZE; 879 880 return 0; 881} 882 883/* Get Q subcode from chip value which readed out in QChannel register */ 884static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 885 struct snd_ctl_elem_value *ucontrol) 886{ 887 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 888 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 889 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 890 unsigned long flags; 891 int ret = -EAGAIN; 892 893 spin_lock_irqsave(&ctrl->ctl_lock, flags); 894 if (ctrl->ready_buf) { 895 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 896 memcpy(&ucontrol->value.bytes.data[0], 897 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 898 ret = 0; 899 } 900 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 901 902 return ret; 903} 904 905/* Get valid good bit from interrupt status register */ 906static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 907 struct snd_ctl_elem_value *ucontrol) 908{ 909 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 910 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 911 struct regmap *regmap = spdif_priv->regmap; 912 u32 val; 913 914 regmap_read(regmap, REG_SPDIF_SIS, &val); 915 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 916 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 917 918 return 0; 919} 920 921static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 922 struct snd_ctl_elem_value *ucontrol) 923{ 924 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 925 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 926 struct regmap *regmap = spdif_priv->regmap; 927 u32 val; 928 929 regmap_read(regmap, REG_SPDIF_SCR, &val); 930 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 931 val = 1 - val; 932 ucontrol->value.integer.value[0] = val; 933 934 return 0; 935} 936 937static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 938 struct snd_ctl_elem_value *ucontrol) 939{ 940 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 941 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 942 struct regmap *regmap = spdif_priv->regmap; 943 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 944 945 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 946 947 return 0; 948} 949 950static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 951 struct snd_ctl_elem_value *ucontrol) 952{ 953 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 954 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 955 struct regmap *regmap = spdif_priv->regmap; 956 u32 val; 957 958 regmap_read(regmap, REG_SPDIF_SCR, &val); 959 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 960 ucontrol->value.integer.value[0] = val; 961 962 return 0; 963} 964 965static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 966 struct snd_ctl_elem_value *ucontrol) 967{ 968 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 969 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 970 struct regmap *regmap = spdif_priv->regmap; 971 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 972 973 if (val) 974 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 975 else 976 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 977 978 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 979 980 return 0; 981} 982 983static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol, 984 struct snd_ctl_elem_value *ucontrol) 985{ 986 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 987 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 988 989 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; 990 991 return 0; 992} 993 994static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol, 995 struct snd_ctl_elem_value *ucontrol) 996{ 997 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 998 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 999 struct snd_soc_card *card = dai->component->card; 1000 bool set = (ucontrol->value.integer.value[0] != 0); 1001 struct regmap *regmap = priv->regmap; 1002 struct snd_soc_pcm_runtime *rtd; 1003 u32 scr, mask; 1004 int stream; 1005 1006 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 1007 1008 if (priv->bypass == set) 1009 return 0; /* nothing to do */ 1010 1011 if (snd_soc_dai_active(dai)) { 1012 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); 1013 return -EBUSY; 1014 } 1015 1016 pm_runtime_get_sync(dai->dev); 1017 1018 if (set) { 1019 /* Disable interrupts */ 1020 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 1021 1022 /* Configure BYPASS mode */ 1023 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF; 1024 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK | 1025 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK; 1026 /* Power up SPDIF module */ 1027 mask |= SCR_LOW_POWER; 1028 } else { 1029 /* Power down SPDIF module, disable TX */ 1030 scr = SCR_LOW_POWER | SCR_TXSEL_OFF; 1031 mask = SCR_LOW_POWER | SCR_TXSEL_MASK; 1032 } 1033 1034 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 1035 1036 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */ 1037 for_each_pcm_streams(stream) 1038 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); 1039 1040 priv->bypass = set; 1041 pm_runtime_put_sync(dai->dev); 1042 1043 return 0; 1044} 1045 1046/* DPLL lock information */ 1047static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 1048 struct snd_ctl_elem_info *uinfo) 1049{ 1050 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1051 uinfo->count = 1; 1052 uinfo->value.integer.min = 16000; 1053 uinfo->value.integer.max = 192000; 1054 1055 return 0; 1056} 1057 1058static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 1059 24, 16, 12, 8, 6, 4, 3, 1060}; 1061 1062/* Get RX data clock rate given the SPDIF bus_clk */ 1063static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 1064 enum spdif_gainsel gainsel) 1065{ 1066 struct regmap *regmap = spdif_priv->regmap; 1067 struct platform_device *pdev = spdif_priv->pdev; 1068 u64 tmpval64, busclk_freq = 0; 1069 u32 freqmeas, phaseconf; 1070 u8 clksrc; 1071 1072 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 1073 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 1074 1075 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 1076 1077 /* Get bus clock from system */ 1078 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 1079 busclk_freq = clk_get_rate(spdif_priv->sysclk); 1080 1081 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 1082 tmpval64 = (u64) busclk_freq * freqmeas; 1083 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 1084 do_div(tmpval64, 128 * 1024); 1085 1086 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 1087 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 1088 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 1089 1090 return (int)tmpval64; 1091} 1092 1093/* 1094 * Get DPLL lock or not info from stable interrupt status register. 1095 * User application must use this control to get locked, 1096 * then can do next PCM operation 1097 */ 1098static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 1099 struct snd_ctl_elem_value *ucontrol) 1100{ 1101 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1102 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1103 int rate = 0; 1104 1105 if (spdif_priv->dpll_locked) 1106 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 1107 1108 ucontrol->value.integer.value[0] = rate; 1109 1110 return 0; 1111} 1112 1113/* 1114 * User bit sync mode: 1115 * 1 CD User channel subcode 1116 * 0 Non-CD data 1117 */ 1118static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 1119 struct snd_ctl_elem_value *ucontrol) 1120{ 1121 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1122 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1123 struct regmap *regmap = spdif_priv->regmap; 1124 u32 val; 1125 1126 regmap_read(regmap, REG_SPDIF_SRCD, &val); 1127 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 1128 1129 return 0; 1130} 1131 1132/* 1133 * User bit sync mode: 1134 * 1 CD User channel subcode 1135 * 0 Non-CD data 1136 */ 1137static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 1138 struct snd_ctl_elem_value *ucontrol) 1139{ 1140 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1141 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1142 struct regmap *regmap = spdif_priv->regmap; 1143 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 1144 1145 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 1146 1147 return 0; 1148} 1149 1150/* FSL SPDIF IEC958 controller defines */ 1151static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1152 /* Status cchanel controller */ 1153 { 1154 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1155 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1156 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1157 SNDRV_CTL_ELEM_ACCESS_WRITE | 1158 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1159 .info = fsl_spdif_info, 1160 .get = fsl_spdif_pb_get, 1161 .put = fsl_spdif_pb_put, 1162 }, 1163 { 1164 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1165 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1166 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1167 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1168 .info = fsl_spdif_info, 1169 .get = fsl_spdif_capture_get, 1170 }, 1171 /* User bits controller */ 1172 { 1173 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1174 .name = "IEC958 Subcode Capture Default", 1175 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1176 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1177 .info = fsl_spdif_info, 1178 .get = fsl_spdif_subcode_get, 1179 }, 1180 { 1181 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1182 .name = "IEC958 Q-subcode Capture Default", 1183 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1184 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1185 .info = fsl_spdif_qinfo, 1186 .get = fsl_spdif_qget, 1187 }, 1188 /* Valid bit error controller */ 1189 { 1190 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1191 .name = "IEC958 RX V-Bit Errors", 1192 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1193 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1194 .info = snd_ctl_boolean_mono_info, 1195 .get = fsl_spdif_rx_vbit_get, 1196 }, 1197 { 1198 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1199 .name = "IEC958 TX V-Bit", 1200 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1201 SNDRV_CTL_ELEM_ACCESS_WRITE | 1202 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1203 .info = snd_ctl_boolean_mono_info, 1204 .get = fsl_spdif_tx_vbit_get, 1205 .put = fsl_spdif_tx_vbit_put, 1206 }, 1207 /* DPLL lock info get controller */ 1208 { 1209 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1210 .name = RX_SAMPLE_RATE_KCONTROL, 1211 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1212 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1213 .info = fsl_spdif_rxrate_info, 1214 .get = fsl_spdif_rxrate_get, 1215 }, 1216 /* RX bypass controller */ 1217 { 1218 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1219 .name = "Bypass Mode", 1220 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1221 .info = snd_ctl_boolean_mono_info, 1222 .get = fsl_spdif_bypass_get, 1223 .put = fsl_spdif_bypass_put, 1224 }, 1225 /* User bit sync mode set/get controller */ 1226 { 1227 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1228 .name = "IEC958 USyncMode CDText", 1229 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1230 SNDRV_CTL_ELEM_ACCESS_WRITE | 1231 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1232 .info = snd_ctl_boolean_mono_info, 1233 .get = fsl_spdif_usync_get, 1234 .put = fsl_spdif_usync_put, 1235 }, 1236}; 1237 1238static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1239 { 1240 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1241 .name = "IEC958 Raw Capture Mode", 1242 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1243 SNDRV_CTL_ELEM_ACCESS_WRITE | 1244 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1245 .info = snd_ctl_boolean_mono_info, 1246 .get = fsl_spdif_rx_rcm_get, 1247 .put = fsl_spdif_rx_rcm_put, 1248 }, 1249}; 1250 1251static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1252{ 1253 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1254 1255 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1256 &spdif_private->dma_params_rx); 1257 1258 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1259 1260 if (spdif_private->soc->raw_capture_mode) 1261 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1262 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1263 1264 spdif_private->snd_card = dai->component->card->snd_card; 1265 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card, 1266 RX_SAMPLE_RATE_KCONTROL); 1267 if (!spdif_private->rxrate_kcontrol) 1268 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n", 1269 RX_SAMPLE_RATE_KCONTROL); 1270 1271 /*Clear the val bit for Tx*/ 1272 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1273 SCR_VAL_MASK, SCR_VAL_CLEAR); 1274 1275 return 0; 1276} 1277 1278static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 1279 .probe = fsl_spdif_dai_probe, 1280 .startup = fsl_spdif_startup, 1281 .hw_params = fsl_spdif_hw_params, 1282 .trigger = fsl_spdif_trigger, 1283 .shutdown = fsl_spdif_shutdown, 1284}; 1285 1286static struct snd_soc_dai_driver fsl_spdif_dai = { 1287 .playback = { 1288 .stream_name = "CPU-Playback", 1289 .channels_min = 2, 1290 .channels_max = 2, 1291 .rates = FSL_SPDIF_RATES_PLAYBACK, 1292 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1293 }, 1294 .capture = { 1295 .stream_name = "CPU-Capture", 1296 .channels_min = 2, 1297 .channels_max = 2, 1298 .rates = FSL_SPDIF_RATES_CAPTURE, 1299 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1300 }, 1301 .ops = &fsl_spdif_dai_ops, 1302}; 1303 1304static const struct snd_soc_component_driver fsl_spdif_component = { 1305 .name = "fsl-spdif", 1306 .legacy_dai_naming = 1, 1307}; 1308 1309/* FSL SPDIF REGMAP */ 1310static const struct reg_default fsl_spdif_reg_defaults[] = { 1311 {REG_SPDIF_SCR, 0x00000400}, 1312 {REG_SPDIF_SRCD, 0x00000000}, 1313 {REG_SPDIF_SIE, 0x00000000}, 1314 {REG_SPDIF_STL, 0x00000000}, 1315 {REG_SPDIF_STR, 0x00000000}, 1316 {REG_SPDIF_STCSCH, 0x00000000}, 1317 {REG_SPDIF_STCSCL, 0x00000000}, 1318 {REG_SPDIF_STCSPH, 0x00000000}, 1319 {REG_SPDIF_STCSPL, 0x00000000}, 1320 {REG_SPDIF_STC, 0x00020f00}, 1321}; 1322 1323static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1324{ 1325 switch (reg) { 1326 case REG_SPDIF_SCR: 1327 case REG_SPDIF_SRCD: 1328 case REG_SPDIF_SRPC: 1329 case REG_SPDIF_SIE: 1330 case REG_SPDIF_SIS: 1331 case REG_SPDIF_SRL: 1332 case REG_SPDIF_SRR: 1333 case REG_SPDIF_SRCSH: 1334 case REG_SPDIF_SRCSL: 1335 case REG_SPDIF_SRU: 1336 case REG_SPDIF_SRQ: 1337 case REG_SPDIF_STCSCH: 1338 case REG_SPDIF_STCSCL: 1339 case REG_SPDIF_STCSPH: 1340 case REG_SPDIF_STCSPL: 1341 case REG_SPDIF_SRFM: 1342 case REG_SPDIF_STC: 1343 case REG_SPDIF_SRCCA_31_0: 1344 case REG_SPDIF_SRCCA_63_32: 1345 case REG_SPDIF_SRCCA_95_64: 1346 case REG_SPDIF_SRCCA_127_96: 1347 case REG_SPDIF_SRCCA_159_128: 1348 case REG_SPDIF_SRCCA_191_160: 1349 case REG_SPDIF_STCCA_31_0: 1350 case REG_SPDIF_STCCA_63_32: 1351 case REG_SPDIF_STCCA_95_64: 1352 case REG_SPDIF_STCCA_127_96: 1353 case REG_SPDIF_STCCA_159_128: 1354 case REG_SPDIF_STCCA_191_160: 1355 return true; 1356 default: 1357 return false; 1358 } 1359} 1360 1361static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1362{ 1363 switch (reg) { 1364 case REG_SPDIF_SRPC: 1365 case REG_SPDIF_SIS: 1366 case REG_SPDIF_SRL: 1367 case REG_SPDIF_SRR: 1368 case REG_SPDIF_SRCSH: 1369 case REG_SPDIF_SRCSL: 1370 case REG_SPDIF_SRU: 1371 case REG_SPDIF_SRQ: 1372 case REG_SPDIF_SRFM: 1373 case REG_SPDIF_SRCCA_31_0: 1374 case REG_SPDIF_SRCCA_63_32: 1375 case REG_SPDIF_SRCCA_95_64: 1376 case REG_SPDIF_SRCCA_127_96: 1377 case REG_SPDIF_SRCCA_159_128: 1378 case REG_SPDIF_SRCCA_191_160: 1379 return true; 1380 default: 1381 return false; 1382 } 1383} 1384 1385static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1386{ 1387 switch (reg) { 1388 case REG_SPDIF_SCR: 1389 case REG_SPDIF_SRCD: 1390 case REG_SPDIF_SRPC: 1391 case REG_SPDIF_SIE: 1392 case REG_SPDIF_SIC: 1393 case REG_SPDIF_STL: 1394 case REG_SPDIF_STR: 1395 case REG_SPDIF_STCSCH: 1396 case REG_SPDIF_STCSCL: 1397 case REG_SPDIF_STCSPH: 1398 case REG_SPDIF_STCSPL: 1399 case REG_SPDIF_STC: 1400 case REG_SPDIF_STCCA_31_0: 1401 case REG_SPDIF_STCCA_63_32: 1402 case REG_SPDIF_STCCA_95_64: 1403 case REG_SPDIF_STCCA_127_96: 1404 case REG_SPDIF_STCCA_159_128: 1405 case REG_SPDIF_STCCA_191_160: 1406 return true; 1407 default: 1408 return false; 1409 } 1410} 1411 1412static const struct regmap_config fsl_spdif_regmap_config = { 1413 .reg_bits = 32, 1414 .reg_stride = 4, 1415 .val_bits = 32, 1416 1417 .max_register = REG_SPDIF_STCCA_191_160, 1418 .reg_defaults = fsl_spdif_reg_defaults, 1419 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1420 .readable_reg = fsl_spdif_readable_reg, 1421 .volatile_reg = fsl_spdif_volatile_reg, 1422 .writeable_reg = fsl_spdif_writeable_reg, 1423 .cache_type = REGCACHE_FLAT, 1424}; 1425 1426static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1427 struct clk *clk, u64 savesub, 1428 enum spdif_txrate index, bool round) 1429{ 1430 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400, 1431 192000, }; 1432 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1433 u64 rate_ideal, rate_actual, sub; 1434 u32 arate; 1435 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1436 u8 txclk_df; 1437 1438 /* The sysclk has an extra divisor [2, 512] */ 1439 sysclk_dfmin = is_sysclk ? 2 : 1; 1440 sysclk_dfmax = is_sysclk ? 512 : 1; 1441 1442 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1443 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1444 rate_ideal = rate[index] * txclk_df * 64ULL; 1445 if (round) 1446 rate_actual = clk_round_rate(clk, rate_ideal); 1447 else 1448 rate_actual = clk_get_rate(clk); 1449 1450 arate = rate_actual / 64; 1451 arate /= txclk_df * sysclk_df; 1452 1453 if (arate == rate[index]) { 1454 /* We are lucky */ 1455 savesub = 0; 1456 spdif_priv->txclk_df[index] = txclk_df; 1457 spdif_priv->sysclk_df[index] = sysclk_df; 1458 spdif_priv->txrate[index] = arate; 1459 goto out; 1460 } else if (arate / rate[index] == 1) { 1461 /* A little bigger than expect */ 1462 sub = (u64)(arate - rate[index]) * 100000; 1463 do_div(sub, rate[index]); 1464 if (sub >= savesub) 1465 continue; 1466 savesub = sub; 1467 spdif_priv->txclk_df[index] = txclk_df; 1468 spdif_priv->sysclk_df[index] = sysclk_df; 1469 spdif_priv->txrate[index] = arate; 1470 } else if (rate[index] / arate == 1) { 1471 /* A little smaller than expect */ 1472 sub = (u64)(rate[index] - arate) * 100000; 1473 do_div(sub, rate[index]); 1474 if (sub >= savesub) 1475 continue; 1476 savesub = sub; 1477 spdif_priv->txclk_df[index] = txclk_df; 1478 spdif_priv->sysclk_df[index] = sysclk_df; 1479 spdif_priv->txrate[index] = arate; 1480 } 1481 } 1482 } 1483 1484out: 1485 return savesub; 1486} 1487 1488static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1489 enum spdif_txrate index) 1490{ 1491 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400, 1492 192000, }; 1493 struct platform_device *pdev = spdif_priv->pdev; 1494 struct device *dev = &pdev->dev; 1495 u64 savesub = 100000, ret; 1496 struct clk *clk; 1497 int i; 1498 1499 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1500 clk = spdif_priv->txclk[i]; 1501 if (IS_ERR(clk)) { 1502 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1503 return PTR_ERR(clk); 1504 } 1505 if (!clk_get_rate(clk)) 1506 continue; 1507 1508 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1509 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1510 if (savesub == ret) 1511 continue; 1512 1513 savesub = ret; 1514 spdif_priv->txclk_src[index] = i; 1515 1516 /* To quick catch a divisor, we allow a 0.1% deviation */ 1517 if (savesub < 100) 1518 break; 1519 } 1520 1521 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1522 spdif_priv->txclk_src[index], rate[index]); 1523 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1524 spdif_priv->txclk_df[index], rate[index]); 1525 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) 1526 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1527 spdif_priv->sysclk_df[index], rate[index]); 1528 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1529 rate[index], spdif_priv->txrate[index]); 1530 1531 return 0; 1532} 1533 1534static int fsl_spdif_probe(struct platform_device *pdev) 1535{ 1536 struct fsl_spdif_priv *spdif_priv; 1537 struct spdif_mixer_control *ctrl; 1538 struct resource *res; 1539 void __iomem *regs; 1540 int irq, ret, i; 1541 char tmp[16]; 1542 1543 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1544 if (!spdif_priv) 1545 return -ENOMEM; 1546 1547 spdif_priv->pdev = pdev; 1548 1549 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1550 1551 /* Initialize this copy of the CPU DAI driver structure */ 1552 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1553 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1554 spdif_priv->cpu_dai_drv.playback.formats = 1555 spdif_priv->soc->tx_formats; 1556 1557 /* Get the addresses and IRQ */ 1558 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1559 if (IS_ERR(regs)) 1560 return PTR_ERR(regs); 1561 1562 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1563 if (IS_ERR(spdif_priv->regmap)) { 1564 dev_err(&pdev->dev, "regmap init failed\n"); 1565 return PTR_ERR(spdif_priv->regmap); 1566 } 1567 1568 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1569 irq = platform_get_irq(pdev, i); 1570 if (irq < 0) 1571 return irq; 1572 1573 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1574 dev_name(&pdev->dev), spdif_priv); 1575 if (ret) { 1576 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1577 return ret; 1578 } 1579 } 1580 1581 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1582 sprintf(tmp, "rxtx%d", i); 1583 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); 1584 if (IS_ERR(spdif_priv->txclk[i])) { 1585 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); 1586 return PTR_ERR(spdif_priv->txclk[i]); 1587 } 1588 } 1589 1590 /* Get system clock for rx clock rate calculation */ 1591 spdif_priv->sysclk = spdif_priv->txclk[5]; 1592 if (IS_ERR(spdif_priv->sysclk)) { 1593 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1594 return PTR_ERR(spdif_priv->sysclk); 1595 } 1596 1597 /* Get core clock for data register access via DMA */ 1598 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1599 if (IS_ERR(spdif_priv->coreclk)) { 1600 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1601 return PTR_ERR(spdif_priv->coreclk); 1602 } 1603 1604 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1605 if (IS_ERR(spdif_priv->spbaclk)) 1606 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1607 1608 /* Select clock source for rx/tx clock */ 1609 spdif_priv->rxclk = spdif_priv->txclk[1]; 1610 if (IS_ERR(spdif_priv->rxclk)) { 1611 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1612 return PTR_ERR(spdif_priv->rxclk); 1613 } 1614 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1615 1616 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, 1617 &spdif_priv->pll11k_clk); 1618 1619 /* Initial spinlock for control data */ 1620 ctrl = &spdif_priv->fsl_spdif_control; 1621 spin_lock_init(&ctrl->ctl_lock); 1622 1623 /* Init tx channel status default value */ 1624 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1625 IEC958_AES0_CON_EMPHASIS_5015; 1626 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1627 ctrl->ch_status[2] = 0x00; 1628 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1629 IEC958_AES3_CON_CLOCK_1000PPM; 1630 1631 spdif_priv->dpll_locked = false; 1632 1633 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1634 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1635 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1636 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1637 1638 /* Register with ASoC */ 1639 dev_set_drvdata(&pdev->dev, spdif_priv); 1640 pm_runtime_enable(&pdev->dev); 1641 regcache_cache_only(spdif_priv->regmap, true); 1642 1643 /* 1644 * Register platform component before registering cpu dai for there 1645 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1646 */ 1647 ret = imx_pcm_dma_init(pdev); 1648 if (ret) { 1649 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1650 goto err_pm_disable; 1651 } 1652 1653 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1654 &spdif_priv->cpu_dai_drv, 1); 1655 if (ret) { 1656 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1657 goto err_pm_disable; 1658 } 1659 1660 return ret; 1661 1662err_pm_disable: 1663 pm_runtime_disable(&pdev->dev); 1664 return ret; 1665} 1666 1667static void fsl_spdif_remove(struct platform_device *pdev) 1668{ 1669 pm_runtime_disable(&pdev->dev); 1670} 1671 1672#ifdef CONFIG_PM 1673static int fsl_spdif_runtime_suspend(struct device *dev) 1674{ 1675 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1676 int i; 1677 1678 /* Disable all the interrupts */ 1679 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1680 1681 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1682 &spdif_priv->regcache_srpc); 1683 regcache_cache_only(spdif_priv->regmap, true); 1684 1685 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) 1686 clk_disable_unprepare(spdif_priv->txclk[i]); 1687 1688 if (!IS_ERR(spdif_priv->spbaclk)) 1689 clk_disable_unprepare(spdif_priv->spbaclk); 1690 clk_disable_unprepare(spdif_priv->coreclk); 1691 1692 return 0; 1693} 1694 1695static int fsl_spdif_runtime_resume(struct device *dev) 1696{ 1697 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1698 int ret; 1699 int i; 1700 1701 ret = clk_prepare_enable(spdif_priv->coreclk); 1702 if (ret) { 1703 dev_err(dev, "failed to enable core clock\n"); 1704 return ret; 1705 } 1706 1707 if (!IS_ERR(spdif_priv->spbaclk)) { 1708 ret = clk_prepare_enable(spdif_priv->spbaclk); 1709 if (ret) { 1710 dev_err(dev, "failed to enable spba clock\n"); 1711 goto disable_core_clk; 1712 } 1713 } 1714 1715 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1716 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1717 if (ret) 1718 goto disable_tx_clk; 1719 } 1720 1721 regcache_cache_only(spdif_priv->regmap, false); 1722 regcache_mark_dirty(spdif_priv->regmap); 1723 1724 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1725 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1726 spdif_priv->regcache_srpc); 1727 1728 ret = regcache_sync(spdif_priv->regmap); 1729 if (ret) 1730 goto disable_tx_clk; 1731 1732 return 0; 1733 1734disable_tx_clk: 1735 for (i--; i >= 0; i--) 1736 clk_disable_unprepare(spdif_priv->txclk[i]); 1737 if (!IS_ERR(spdif_priv->spbaclk)) 1738 clk_disable_unprepare(spdif_priv->spbaclk); 1739disable_core_clk: 1740 clk_disable_unprepare(spdif_priv->coreclk); 1741 1742 return ret; 1743} 1744#endif /* CONFIG_PM */ 1745 1746static const struct dev_pm_ops fsl_spdif_pm = { 1747 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1748 pm_runtime_force_resume) 1749 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1750 NULL) 1751}; 1752 1753static const struct of_device_id fsl_spdif_dt_ids[] = { 1754 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1755 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1756 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1757 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1758 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1759 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, }, 1760 {} 1761}; 1762MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1763 1764static struct platform_driver fsl_spdif_driver = { 1765 .driver = { 1766 .name = "fsl-spdif-dai", 1767 .of_match_table = fsl_spdif_dt_ids, 1768 .pm = &fsl_spdif_pm, 1769 }, 1770 .probe = fsl_spdif_probe, 1771 .remove_new = fsl_spdif_remove, 1772}; 1773 1774module_platform_driver(fsl_spdif_driver); 1775 1776MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1777MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1778MODULE_LICENSE("GPL v2"); 1779MODULE_ALIAS("platform:fsl-spdif-dai"); 1780