1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4// 5// Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7#include <linux/clk.h> 8#include <linux/delay.h> 9#include <linux/dmaengine.h> 10#include <linux/module.h> 11#include <linux/of_address.h> 12#include <linux/of_device.h> 13#include <linux/pinctrl/consumer.h> 14#include <linux/pm_qos.h> 15#include <linux/pm_runtime.h> 16#include <linux/regmap.h> 17#include <linux/slab.h> 18#include <linux/time.h> 19#include <sound/core.h> 20#include <sound/dmaengine_pcm.h> 21#include <sound/pcm_params.h> 22#include <linux/mfd/syscon.h> 23#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25#include "fsl_sai.h" 26#include "fsl_utils.h" 27#include "imx-pcm.h" 28 29#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37}; 38 39static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42}; 43 44/** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55{ 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60} 61 62static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63{ 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85} 86 87static irqreturn_t fsl_sai_isr(int irq, void *devid) 88{ 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163out: 164 return iret; 165} 166 167static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169{ 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176} 177 178static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180{ 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186} 187 188static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190{ 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216} 217 218static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219{ 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231} 232 233static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235{ 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271} 272 273static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275{ 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 sai->is_dsp_mode = false; 285 /* DAI mode */ 286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 287 case SND_SOC_DAIFMT_I2S: 288 /* 289 * Frame low, 1clk before data, one word length for frame sync, 290 * frame sync starts one serial clock cycle earlier, 291 * that is, together with the last bit of the previous 292 * data word. 293 */ 294 val_cr2 |= FSL_SAI_CR2_BCP; 295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 296 break; 297 case SND_SOC_DAIFMT_LEFT_J: 298 /* 299 * Frame high, one word length for frame sync, 300 * frame sync asserts with the first bit of the frame. 301 */ 302 val_cr2 |= FSL_SAI_CR2_BCP; 303 break; 304 case SND_SOC_DAIFMT_DSP_A: 305 /* 306 * Frame high, 1clk before data, one bit for frame sync, 307 * frame sync starts one serial clock cycle earlier, 308 * that is, together with the last bit of the previous 309 * data word. 310 */ 311 val_cr2 |= FSL_SAI_CR2_BCP; 312 val_cr4 |= FSL_SAI_CR4_FSE; 313 sai->is_dsp_mode = true; 314 break; 315 case SND_SOC_DAIFMT_DSP_B: 316 /* 317 * Frame high, one bit for frame sync, 318 * frame sync asserts with the first bit of the frame. 319 */ 320 val_cr2 |= FSL_SAI_CR2_BCP; 321 sai->is_dsp_mode = true; 322 break; 323 case SND_SOC_DAIFMT_PDM: 324 val_cr2 |= FSL_SAI_CR2_BCP; 325 val_cr4 &= ~FSL_SAI_CR4_MF; 326 sai->is_pdm_mode = true; 327 break; 328 case SND_SOC_DAIFMT_RIGHT_J: 329 /* To be done */ 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 /* Invert both clocks */ 338 val_cr2 ^= FSL_SAI_CR2_BCP; 339 val_cr4 ^= FSL_SAI_CR4_FSP; 340 break; 341 case SND_SOC_DAIFMT_IB_NF: 342 /* Invert bit clock */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 break; 345 case SND_SOC_DAIFMT_NB_IF: 346 /* Invert frame clock */ 347 val_cr4 ^= FSL_SAI_CR4_FSP; 348 break; 349 case SND_SOC_DAIFMT_NB_NF: 350 /* Nothing to do for both normal cases */ 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 /* DAI clock provider masks */ 357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 358 case SND_SOC_DAIFMT_BP_FP: 359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 361 sai->is_consumer_mode = false; 362 break; 363 case SND_SOC_DAIFMT_BC_FC: 364 sai->is_consumer_mode = true; 365 break; 366 case SND_SOC_DAIFMT_BP_FC: 367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 368 sai->is_consumer_mode = false; 369 break; 370 case SND_SOC_DAIFMT_BC_FP: 371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 372 sai->is_consumer_mode = true; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 383 384 return 0; 385} 386 387static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388{ 389 int ret; 390 391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 392 if (ret) { 393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 394 return ret; 395 } 396 397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 398 if (ret) 399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 400 401 return ret; 402} 403 404static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 405{ 406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 407 unsigned int reg, ofs = sai->soc_data->reg_offset; 408 unsigned long clk_rate; 409 u32 savediv = 0, ratio, bestdiff = freq; 410 int adir = tx ? RX : TX; 411 int dir = tx ? TX : RX; 412 u32 id; 413 bool support_1_1_ratio = sai->verid.version >= 0x0301; 414 415 /* Don't apply to consumer mode */ 416 if (sai->is_consumer_mode) 417 return 0; 418 419 /* 420 * There is no point in polling MCLK0 if it is identical to MCLK1. 421 * And given that MQS use case has to use MCLK1 though two clocks 422 * are the same, we simply skip MCLK0 and start to find from MCLK1. 423 */ 424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 425 426 for (; id < FSL_SAI_MCLK_MAX; id++) { 427 int diff; 428 429 clk_rate = clk_get_rate(sai->mclk_clk[id]); 430 if (!clk_rate) 431 continue; 432 433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 434 if (!ratio || ratio > 512) 435 continue; 436 if (ratio == 1 && !support_1_1_ratio) 437 continue; 438 if ((ratio & 1) && ratio > 1) 439 continue; 440 441 diff = abs((long)clk_rate - ratio * freq); 442 443 /* 444 * Drop the source that can not be 445 * divided into the required rate. 446 */ 447 if (diff != 0 && clk_rate / diff < 1000) 448 continue; 449 450 dev_dbg(dai->dev, 451 "ratio %d for freq %dHz based on clock %ldHz\n", 452 ratio, freq, clk_rate); 453 454 455 if (diff < bestdiff) { 456 savediv = ratio; 457 sai->mclk_id[tx] = id; 458 bestdiff = diff; 459 } 460 461 if (diff == 0) 462 break; 463 } 464 465 if (savediv == 0) { 466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 467 tx ? 'T' : 'R', freq); 468 return -EINVAL; 469 } 470 471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 472 sai->mclk_id[tx], savediv, bestdiff); 473 474 /* 475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 476 * set TCR2 register for playback. 477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 478 * and capture. 479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 480 * and capture. 481 * 4) For Tx and Rx are both Synchronous with another SAI, we just 482 * ignore it. 483 */ 484 if (fsl_sai_dir_is_synced(sai, adir)) 485 reg = FSL_SAI_xCR2(!tx, ofs); 486 else if (!sai->synchronous[dir]) 487 reg = FSL_SAI_xCR2(tx, ofs); 488 else 489 return 0; 490 491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 493 494 if (savediv == 1) { 495 regmap_update_bits(sai->regmap, reg, 496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 497 FSL_SAI_CR2_BYP); 498 if (fsl_sai_dir_is_synced(sai, adir)) 499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 501 else 502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 503 FSL_SAI_CR2_BCI, 0); 504 } else { 505 regmap_update_bits(sai->regmap, reg, 506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 507 savediv / 2 - 1); 508 } 509 510 return 0; 511} 512 513static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct snd_soc_dai *cpu_dai) 516{ 517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 518 unsigned int ofs = sai->soc_data->reg_offset; 519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 520 unsigned int channels = params_channels(params); 521 struct snd_dmaengine_dai_dma_data *dma_params; 522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 523 u32 word_width = params_width(params); 524 int trce_mask = 0, dl_cfg_idx = 0; 525 int dl_cfg_cnt = sai->dl_cfg_cnt; 526 u32 dl_type = FSL_SAI_DL_I2S; 527 u32 val_cr4 = 0, val_cr5 = 0; 528 u32 slots = (channels == 1) ? 2 : channels; 529 u32 slot_width = word_width; 530 int adir = tx ? RX : TX; 531 u32 pins, bclk; 532 u32 watermark; 533 int ret, i; 534 535 if (sai->slot_width) 536 slot_width = sai->slot_width; 537 538 if (sai->slots) 539 slots = sai->slots; 540 else if (sai->bclk_ratio) 541 slots = sai->bclk_ratio / slot_width; 542 543 pins = DIV_ROUND_UP(channels, slots); 544 545 /* 546 * PDM mode, channels are independent 547 * each channels are on one dataline/FIFO. 548 */ 549 if (sai->is_pdm_mode) { 550 pins = channels; 551 dl_type = FSL_SAI_DL_PDM; 552 } 553 554 for (i = 0; i < dl_cfg_cnt; i++) { 555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 556 dl_cfg_idx = i; 557 break; 558 } 559 } 560 561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 562 dev_err(cpu_dai->dev, "channel not supported\n"); 563 return -EINVAL; 564 } 565 566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 567 568 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 570 if (!IS_ERR_OR_NULL(sai->pins_state)) { 571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 572 if (ret) { 573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 574 return ret; 575 } 576 } 577 } 578 579 if (!sai->is_consumer_mode) { 580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 581 if (ret) 582 return ret; 583 584 /* Do not enable the clock if it is already enabled */ 585 if (!(sai->mclk_streams & BIT(substream->stream))) { 586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 587 if (ret) 588 return ret; 589 590 sai->mclk_streams |= BIT(substream->stream); 591 } 592 } 593 594 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 596 597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 599 600 if (sai->is_lsb_first || sai->is_pdm_mode) 601 val_cr5 |= FSL_SAI_CR5_FBT(0); 602 else 603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 604 605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 606 607 /* Set to output mode to avoid tri-stated data pins */ 608 if (tx) 609 val_cr4 |= FSL_SAI_CR4_CHMOD; 610 611 /* 612 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 613 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 614 * RCR5(TCR5) for playback(capture), or there will be sync error. 615 */ 616 617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 619 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 620 FSL_SAI_CR4_CHMOD_MASK, 621 val_cr4); 622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 623 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 624 FSL_SAI_CR5_FBT_MASK, val_cr5); 625 } 626 627 /* 628 * Combine mode has limation: 629 * - Can't used for singel dataline/FIFO case except the FIFO0 630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 631 * are successive and start from FIFO0 632 * 633 * So for common usage, all multi fifo case disable the combine mode. 634 */ 635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 637 FSL_SAI_CR4_FCOMB_MASK, 0); 638 else 639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 640 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 641 642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 644 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 645 646 if (sai->is_multi_fifo_dma) { 647 sai->audio_config[tx].words_per_fifo = min(slots, channels); 648 if (tx) { 649 sai->audio_config[tx].n_fifos_dst = pins; 650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 651 } else { 652 sai->audio_config[tx].n_fifos_src = pins; 653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 654 } 655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 656 dma_params->peripheral_config = &sai->audio_config[tx]; 657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 658 659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 660 (dma_params->maxburst - 1); 661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 663 watermark); 664 } 665 666 /* Find a proper tcre setting */ 667 for (i = 0; i < sai->soc_data->pins; i++) { 668 trce_mask = (1 << (i + 1)) - 1; 669 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 670 break; 671 } 672 673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 674 FSL_SAI_CR3_TRCE_MASK, 675 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 676 677 /* 678 * When the TERE and FSD_MSTR enabled before configuring the word width 679 * There will be no frame sync clock issue, because word width impact 680 * the generation of frame sync clock. 681 * 682 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 683 * We need to disable FSD_MSTR before configuring word width, then enable 684 * FSD_MSTR bit for this specific case. 685 */ 686 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 687 !sai->is_consumer_mode) 688 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 689 FSL_SAI_CR4_FSD_MSTR, 0); 690 691 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 692 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 693 FSL_SAI_CR4_CHMOD_MASK, 694 val_cr4); 695 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 696 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 697 FSL_SAI_CR5_FBT_MASK, val_cr5); 698 699 /* Enable FSD_MSTR after configuring word width */ 700 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 701 !sai->is_consumer_mode) 702 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 703 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 704 705 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 706 ~0UL - ((1 << min(channels, slots)) - 1)); 707 708 return 0; 709} 710 711static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 712 struct snd_soc_dai *cpu_dai) 713{ 714 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 715 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 716 unsigned int ofs = sai->soc_data->reg_offset; 717 718 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 719 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 720 721 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 722 FSL_SAI_CR3_TRCE_MASK, 0); 723 724 if (!sai->is_consumer_mode && 725 sai->mclk_streams & BIT(substream->stream)) { 726 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 727 sai->mclk_streams &= ~BIT(substream->stream); 728 } 729 730 return 0; 731} 732 733static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 734{ 735 unsigned int ofs = sai->soc_data->reg_offset; 736 bool tx = dir == TX; 737 u32 xcsr, count = 100, mask; 738 739 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 740 mask = FSL_SAI_CSR_TERE; 741 else 742 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 743 744 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 745 mask, 0); 746 747 /* TERE will remain set till the end of current frame */ 748 do { 749 udelay(10); 750 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 751 } while (--count && xcsr & FSL_SAI_CSR_TERE); 752 753 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 754 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 755 756 /* 757 * For sai master mode, after several open/close sai, 758 * there will be no frame clock, and can't recover 759 * anymore. Add software reset to fix this issue. 760 * This is a hardware bug, and will be fix in the 761 * next sai version. 762 */ 763 if (!sai->is_consumer_mode) { 764 /* Software Reset */ 765 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 766 /* Clear SR bit to finish the reset */ 767 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 768 } 769} 770 771static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 772 struct snd_soc_dai *cpu_dai) 773{ 774 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 775 unsigned int ofs = sai->soc_data->reg_offset; 776 777 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 778 int adir = tx ? RX : TX; 779 int dir = tx ? TX : RX; 780 u32 xcsr; 781 782 /* 783 * Asynchronous mode: Clear SYNC for both Tx and Rx. 784 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 785 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 786 */ 787 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 788 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 789 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 790 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 791 792 /* 793 * It is recommended that the transmitter is the last enabled 794 * and the first disabled. 795 */ 796 switch (cmd) { 797 case SNDRV_PCM_TRIGGER_START: 798 case SNDRV_PCM_TRIGGER_RESUME: 799 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 800 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 801 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 802 803 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 804 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 805 /* 806 * Enable the opposite direction for synchronous mode 807 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 808 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 809 * 810 * RM recommends to enable RE after TE for case 1 and to enable 811 * TE after RE for case 2, but we here may not always guarantee 812 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 813 * TE after RE, which is against what RM recommends but should 814 * be safe to do, judging by years of testing results. 815 */ 816 if (fsl_sai_dir_is_synced(sai, adir)) 817 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 818 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 819 820 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 821 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 822 break; 823 case SNDRV_PCM_TRIGGER_STOP: 824 case SNDRV_PCM_TRIGGER_SUSPEND: 825 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 826 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 827 FSL_SAI_CSR_FRDE, 0); 828 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 829 FSL_SAI_CSR_xIE_MASK, 0); 830 831 /* Check if the opposite FRDE is also disabled */ 832 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 833 834 /* 835 * If opposite stream provides clocks for synchronous mode and 836 * it is inactive, disable it before disabling the current one 837 */ 838 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 839 fsl_sai_config_disable(sai, adir); 840 841 /* 842 * Disable current stream if either of: 843 * 1. current stream doesn't provide clocks for synchronous mode 844 * 2. current stream provides clocks for synchronous mode but no 845 * more stream is active. 846 */ 847 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 848 fsl_sai_config_disable(sai, dir); 849 850 break; 851 default: 852 return -EINVAL; 853 } 854 855 return 0; 856} 857 858static int fsl_sai_startup(struct snd_pcm_substream *substream, 859 struct snd_soc_dai *cpu_dai) 860{ 861 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 862 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 863 int ret; 864 865 /* 866 * EDMA controller needs period size to be a multiple of 867 * tx/rx maxburst 868 */ 869 if (sai->soc_data->use_edma) 870 snd_pcm_hw_constraint_step(substream->runtime, 0, 871 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 872 tx ? sai->dma_params_tx.maxburst : 873 sai->dma_params_rx.maxburst); 874 875 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 876 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 877 878 return ret; 879} 880 881static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 882{ 883 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 884 unsigned int ofs = sai->soc_data->reg_offset; 885 886 /* Software Reset for both Tx and Rx */ 887 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 888 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 889 /* Clear SR bit to finish the reset */ 890 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 891 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 892 893 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 894 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 895 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 896 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 897 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 898 sai->dma_params_rx.maxburst - 1); 899 900 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 901 &sai->dma_params_rx); 902 903 return 0; 904} 905 906static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 907 .probe = fsl_sai_dai_probe, 908 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 909 .set_sysclk = fsl_sai_set_dai_sysclk, 910 .set_fmt = fsl_sai_set_dai_fmt, 911 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 912 .hw_params = fsl_sai_hw_params, 913 .hw_free = fsl_sai_hw_free, 914 .trigger = fsl_sai_trigger, 915 .startup = fsl_sai_startup, 916}; 917 918static int fsl_sai_dai_resume(struct snd_soc_component *component) 919{ 920 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 921 struct device *dev = &sai->pdev->dev; 922 int ret; 923 924 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 925 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 926 if (ret) { 927 dev_err(dev, "failed to set proper pins state: %d\n", ret); 928 return ret; 929 } 930 } 931 932 return 0; 933} 934 935static struct snd_soc_dai_driver fsl_sai_dai_template = { 936 .playback = { 937 .stream_name = "CPU-Playback", 938 .channels_min = 1, 939 .channels_max = 32, 940 .rate_min = 8000, 941 .rate_max = 2822400, 942 .rates = SNDRV_PCM_RATE_KNOT, 943 .formats = FSL_SAI_FORMATS, 944 }, 945 .capture = { 946 .stream_name = "CPU-Capture", 947 .channels_min = 1, 948 .channels_max = 32, 949 .rate_min = 8000, 950 .rate_max = 2822400, 951 .rates = SNDRV_PCM_RATE_KNOT, 952 .formats = FSL_SAI_FORMATS, 953 }, 954 .ops = &fsl_sai_pcm_dai_ops, 955}; 956 957static const struct snd_soc_component_driver fsl_component = { 958 .name = "fsl-sai", 959 .resume = fsl_sai_dai_resume, 960 .legacy_dai_naming = 1, 961}; 962 963static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 964 {FSL_SAI_TCR1(0), 0}, 965 {FSL_SAI_TCR2(0), 0}, 966 {FSL_SAI_TCR3(0), 0}, 967 {FSL_SAI_TCR4(0), 0}, 968 {FSL_SAI_TCR5(0), 0}, 969 {FSL_SAI_TDR0, 0}, 970 {FSL_SAI_TDR1, 0}, 971 {FSL_SAI_TDR2, 0}, 972 {FSL_SAI_TDR3, 0}, 973 {FSL_SAI_TDR4, 0}, 974 {FSL_SAI_TDR5, 0}, 975 {FSL_SAI_TDR6, 0}, 976 {FSL_SAI_TDR7, 0}, 977 {FSL_SAI_TMR, 0}, 978 {FSL_SAI_RCR1(0), 0}, 979 {FSL_SAI_RCR2(0), 0}, 980 {FSL_SAI_RCR3(0), 0}, 981 {FSL_SAI_RCR4(0), 0}, 982 {FSL_SAI_RCR5(0), 0}, 983 {FSL_SAI_RMR, 0}, 984}; 985 986static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 987 {FSL_SAI_TCR1(8), 0}, 988 {FSL_SAI_TCR2(8), 0}, 989 {FSL_SAI_TCR3(8), 0}, 990 {FSL_SAI_TCR4(8), 0}, 991 {FSL_SAI_TCR5(8), 0}, 992 {FSL_SAI_TDR0, 0}, 993 {FSL_SAI_TDR1, 0}, 994 {FSL_SAI_TDR2, 0}, 995 {FSL_SAI_TDR3, 0}, 996 {FSL_SAI_TDR4, 0}, 997 {FSL_SAI_TDR5, 0}, 998 {FSL_SAI_TDR6, 0}, 999 {FSL_SAI_TDR7, 0}, 1000 {FSL_SAI_TMR, 0}, 1001 {FSL_SAI_RCR1(8), 0}, 1002 {FSL_SAI_RCR2(8), 0}, 1003 {FSL_SAI_RCR3(8), 0}, 1004 {FSL_SAI_RCR4(8), 0}, 1005 {FSL_SAI_RCR5(8), 0}, 1006 {FSL_SAI_RMR, 0}, 1007 {FSL_SAI_MCTL, 0}, 1008 {FSL_SAI_MDIV, 0}, 1009}; 1010 1011static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1012{ 1013 struct fsl_sai *sai = dev_get_drvdata(dev); 1014 unsigned int ofs = sai->soc_data->reg_offset; 1015 1016 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1017 return true; 1018 1019 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1020 return true; 1021 1022 switch (reg) { 1023 case FSL_SAI_TFR0: 1024 case FSL_SAI_TFR1: 1025 case FSL_SAI_TFR2: 1026 case FSL_SAI_TFR3: 1027 case FSL_SAI_TFR4: 1028 case FSL_SAI_TFR5: 1029 case FSL_SAI_TFR6: 1030 case FSL_SAI_TFR7: 1031 case FSL_SAI_TMR: 1032 case FSL_SAI_RDR0: 1033 case FSL_SAI_RDR1: 1034 case FSL_SAI_RDR2: 1035 case FSL_SAI_RDR3: 1036 case FSL_SAI_RDR4: 1037 case FSL_SAI_RDR5: 1038 case FSL_SAI_RDR6: 1039 case FSL_SAI_RDR7: 1040 case FSL_SAI_RFR0: 1041 case FSL_SAI_RFR1: 1042 case FSL_SAI_RFR2: 1043 case FSL_SAI_RFR3: 1044 case FSL_SAI_RFR4: 1045 case FSL_SAI_RFR5: 1046 case FSL_SAI_RFR6: 1047 case FSL_SAI_RFR7: 1048 case FSL_SAI_RMR: 1049 case FSL_SAI_MCTL: 1050 case FSL_SAI_MDIV: 1051 case FSL_SAI_VERID: 1052 case FSL_SAI_PARAM: 1053 case FSL_SAI_TTCTN: 1054 case FSL_SAI_RTCTN: 1055 case FSL_SAI_TTCTL: 1056 case FSL_SAI_TBCTN: 1057 case FSL_SAI_TTCAP: 1058 case FSL_SAI_RTCTL: 1059 case FSL_SAI_RBCTN: 1060 case FSL_SAI_RTCAP: 1061 return true; 1062 default: 1063 return false; 1064 } 1065} 1066 1067static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1068{ 1069 struct fsl_sai *sai = dev_get_drvdata(dev); 1070 unsigned int ofs = sai->soc_data->reg_offset; 1071 1072 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1073 return true; 1074 1075 /* Set VERID and PARAM be volatile for reading value in probe */ 1076 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1077 return true; 1078 1079 switch (reg) { 1080 case FSL_SAI_TFR0: 1081 case FSL_SAI_TFR1: 1082 case FSL_SAI_TFR2: 1083 case FSL_SAI_TFR3: 1084 case FSL_SAI_TFR4: 1085 case FSL_SAI_TFR5: 1086 case FSL_SAI_TFR6: 1087 case FSL_SAI_TFR7: 1088 case FSL_SAI_RFR0: 1089 case FSL_SAI_RFR1: 1090 case FSL_SAI_RFR2: 1091 case FSL_SAI_RFR3: 1092 case FSL_SAI_RFR4: 1093 case FSL_SAI_RFR5: 1094 case FSL_SAI_RFR6: 1095 case FSL_SAI_RFR7: 1096 case FSL_SAI_RDR0: 1097 case FSL_SAI_RDR1: 1098 case FSL_SAI_RDR2: 1099 case FSL_SAI_RDR3: 1100 case FSL_SAI_RDR4: 1101 case FSL_SAI_RDR5: 1102 case FSL_SAI_RDR6: 1103 case FSL_SAI_RDR7: 1104 return true; 1105 default: 1106 return false; 1107 } 1108} 1109 1110static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1111{ 1112 struct fsl_sai *sai = dev_get_drvdata(dev); 1113 unsigned int ofs = sai->soc_data->reg_offset; 1114 1115 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1116 return true; 1117 1118 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1119 return true; 1120 1121 switch (reg) { 1122 case FSL_SAI_TDR0: 1123 case FSL_SAI_TDR1: 1124 case FSL_SAI_TDR2: 1125 case FSL_SAI_TDR3: 1126 case FSL_SAI_TDR4: 1127 case FSL_SAI_TDR5: 1128 case FSL_SAI_TDR6: 1129 case FSL_SAI_TDR7: 1130 case FSL_SAI_TMR: 1131 case FSL_SAI_RMR: 1132 case FSL_SAI_MCTL: 1133 case FSL_SAI_MDIV: 1134 case FSL_SAI_TTCTL: 1135 case FSL_SAI_RTCTL: 1136 return true; 1137 default: 1138 return false; 1139 } 1140} 1141 1142static struct regmap_config fsl_sai_regmap_config = { 1143 .reg_bits = 32, 1144 .reg_stride = 4, 1145 .val_bits = 32, 1146 .fast_io = true, 1147 1148 .max_register = FSL_SAI_RMR, 1149 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1150 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1151 .readable_reg = fsl_sai_readable_reg, 1152 .volatile_reg = fsl_sai_volatile_reg, 1153 .writeable_reg = fsl_sai_writeable_reg, 1154 .cache_type = REGCACHE_FLAT, 1155}; 1156 1157static int fsl_sai_check_version(struct device *dev) 1158{ 1159 struct fsl_sai *sai = dev_get_drvdata(dev); 1160 unsigned char ofs = sai->soc_data->reg_offset; 1161 unsigned int val; 1162 int ret; 1163 1164 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1165 return 0; 1166 1167 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1168 if (ret < 0) 1169 return ret; 1170 1171 dev_dbg(dev, "VERID: 0x%016X\n", val); 1172 1173 sai->verid.version = val & 1174 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1175 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1176 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1177 1178 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1179 if (ret < 0) 1180 return ret; 1181 1182 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1183 1184 /* Max slots per frame, power of 2 */ 1185 sai->param.slot_num = 1 << 1186 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1187 1188 /* Words per fifo, power of 2 */ 1189 sai->param.fifo_depth = 1 << 1190 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1191 1192 /* Number of datalines implemented */ 1193 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1194 1195 return 0; 1196} 1197 1198/* 1199 * Calculate the offset between first two datalines, don't 1200 * different offset in one case. 1201 */ 1202static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1203{ 1204 int fbidx, nbidx, offset; 1205 1206 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1207 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1208 offset = nbidx - fbidx - 1; 1209 1210 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1211} 1212 1213/* 1214 * read the fsl,dataline property from dts file. 1215 * It has 3 value for each configuration, first one means the type: 1216 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1217 * dataline mask for 'tx'. for example 1218 * 1219 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1220 * 1221 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1222 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1223 * 1224 */ 1225static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1226{ 1227 struct platform_device *pdev = sai->pdev; 1228 struct device_node *np = pdev->dev.of_node; 1229 struct device *dev = &pdev->dev; 1230 int ret, elems, i, index, num_cfg; 1231 char *propname = "fsl,dataline"; 1232 struct fsl_sai_dl_cfg *cfg; 1233 unsigned long dl_mask; 1234 unsigned int soc_dl; 1235 u32 rx, tx, type; 1236 1237 elems = of_property_count_u32_elems(np, propname); 1238 1239 if (elems <= 0) { 1240 elems = 0; 1241 } else if (elems % 3) { 1242 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1243 return -EINVAL; 1244 } 1245 1246 num_cfg = elems / 3; 1247 /* Add one more for default value */ 1248 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1249 if (!cfg) 1250 return -ENOMEM; 1251 1252 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1253 soc_dl = BIT(sai->soc_data->pins) - 1; 1254 cfg[0].type = FSL_SAI_DL_DEFAULT; 1255 cfg[0].pins[0] = sai->soc_data->pins; 1256 cfg[0].mask[0] = soc_dl; 1257 cfg[0].start_off[0] = 0; 1258 cfg[0].next_off[0] = 0; 1259 1260 cfg[0].pins[1] = sai->soc_data->pins; 1261 cfg[0].mask[1] = soc_dl; 1262 cfg[0].start_off[1] = 0; 1263 cfg[0].next_off[1] = 0; 1264 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1265 /* 1266 * type of dataline 1267 * 0 means default mode 1268 * 1 means I2S mode 1269 * 2 means PDM mode 1270 */ 1271 ret = of_property_read_u32_index(np, propname, index++, &type); 1272 if (ret) 1273 return -EINVAL; 1274 1275 ret = of_property_read_u32_index(np, propname, index++, &rx); 1276 if (ret) 1277 return -EINVAL; 1278 1279 ret = of_property_read_u32_index(np, propname, index++, &tx); 1280 if (ret) 1281 return -EINVAL; 1282 1283 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1284 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1285 return -EINVAL; 1286 } 1287 1288 rx = rx & soc_dl; 1289 tx = tx & soc_dl; 1290 1291 cfg[i].type = type; 1292 cfg[i].pins[0] = hweight8(rx); 1293 cfg[i].mask[0] = rx; 1294 dl_mask = rx; 1295 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1296 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1297 1298 cfg[i].pins[1] = hweight8(tx); 1299 cfg[i].mask[1] = tx; 1300 dl_mask = tx; 1301 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1302 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1303 } 1304 1305 sai->dl_cfg = cfg; 1306 sai->dl_cfg_cnt = num_cfg + 1; 1307 return 0; 1308} 1309 1310static int fsl_sai_runtime_suspend(struct device *dev); 1311static int fsl_sai_runtime_resume(struct device *dev); 1312 1313static int fsl_sai_probe(struct platform_device *pdev) 1314{ 1315 struct device_node *np = pdev->dev.of_node; 1316 struct device *dev = &pdev->dev; 1317 struct fsl_sai *sai; 1318 struct regmap *gpr; 1319 void __iomem *base; 1320 char tmp[8]; 1321 int irq, ret, i; 1322 int index; 1323 u32 dmas[4]; 1324 1325 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1326 if (!sai) 1327 return -ENOMEM; 1328 1329 sai->pdev = pdev; 1330 sai->soc_data = of_device_get_match_data(dev); 1331 1332 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1333 1334 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1335 if (IS_ERR(base)) 1336 return PTR_ERR(base); 1337 1338 if (sai->soc_data->reg_offset == 8) { 1339 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1340 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1341 fsl_sai_regmap_config.num_reg_defaults = 1342 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1343 } 1344 1345 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1346 if (IS_ERR(sai->regmap)) { 1347 dev_err(dev, "regmap init failed\n"); 1348 return PTR_ERR(sai->regmap); 1349 } 1350 1351 sai->bus_clk = devm_clk_get(dev, "bus"); 1352 /* Compatible with old DTB cases */ 1353 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1354 sai->bus_clk = devm_clk_get(dev, "sai"); 1355 if (IS_ERR(sai->bus_clk)) { 1356 dev_err(dev, "failed to get bus clock: %ld\n", 1357 PTR_ERR(sai->bus_clk)); 1358 /* -EPROBE_DEFER */ 1359 return PTR_ERR(sai->bus_clk); 1360 } 1361 1362 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1363 sprintf(tmp, "mclk%d", i); 1364 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1365 if (IS_ERR(sai->mclk_clk[i])) { 1366 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1367 i, PTR_ERR(sai->mclk_clk[i])); 1368 sai->mclk_clk[i] = NULL; 1369 } 1370 } 1371 1372 if (sai->soc_data->mclk0_is_mclk1) 1373 sai->mclk_clk[0] = sai->mclk_clk[1]; 1374 else 1375 sai->mclk_clk[0] = sai->bus_clk; 1376 1377 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1378 &sai->pll11k_clk); 1379 1380 /* Use Multi FIFO mode depending on the support from SDMA script */ 1381 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1382 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1383 sai->is_multi_fifo_dma = true; 1384 1385 /* read dataline mask for rx and tx*/ 1386 ret = fsl_sai_read_dlcfg(sai); 1387 if (ret < 0) { 1388 dev_err(dev, "failed to read dlcfg %d\n", ret); 1389 return ret; 1390 } 1391 1392 irq = platform_get_irq(pdev, 0); 1393 if (irq < 0) 1394 return irq; 1395 1396 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1397 np->name, sai); 1398 if (ret) { 1399 dev_err(dev, "failed to claim irq %u\n", irq); 1400 return ret; 1401 } 1402 1403 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1404 sizeof(fsl_sai_dai_template)); 1405 1406 /* Sync Tx with Rx as default by following old DT binding */ 1407 sai->synchronous[RX] = true; 1408 sai->synchronous[TX] = false; 1409 sai->cpu_dai_drv.symmetric_rate = 1; 1410 sai->cpu_dai_drv.symmetric_channels = 1; 1411 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1412 1413 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1414 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1415 /* error out if both synchronous and asynchronous are present */ 1416 dev_err(dev, "invalid binding for synchronous mode\n"); 1417 return -EINVAL; 1418 } 1419 1420 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1421 /* Sync Rx with Tx */ 1422 sai->synchronous[RX] = false; 1423 sai->synchronous[TX] = true; 1424 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1425 /* Discard all settings for asynchronous mode */ 1426 sai->synchronous[RX] = false; 1427 sai->synchronous[TX] = false; 1428 sai->cpu_dai_drv.symmetric_rate = 0; 1429 sai->cpu_dai_drv.symmetric_channels = 0; 1430 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1431 } 1432 1433 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1434 1435 if (sai->mclk_direction_output && 1436 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1437 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1438 if (IS_ERR(gpr)) { 1439 dev_err(dev, "cannot find iomuxc registers\n"); 1440 return PTR_ERR(gpr); 1441 } 1442 1443 index = of_alias_get_id(np, "sai"); 1444 if (index < 0) 1445 return index; 1446 1447 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1448 MCLK_DIR(index)); 1449 } 1450 1451 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1452 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1453 sai->dma_params_rx.maxburst = 1454 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1455 sai->dma_params_tx.maxburst = 1456 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1457 1458 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1459 1460 platform_set_drvdata(pdev, sai); 1461 pm_runtime_enable(dev); 1462 if (!pm_runtime_enabled(dev)) { 1463 ret = fsl_sai_runtime_resume(dev); 1464 if (ret) 1465 goto err_pm_disable; 1466 } 1467 1468 ret = pm_runtime_resume_and_get(dev); 1469 if (ret < 0) 1470 goto err_pm_get_sync; 1471 1472 /* Get sai version */ 1473 ret = fsl_sai_check_version(dev); 1474 if (ret < 0) 1475 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1476 1477 /* Select MCLK direction */ 1478 if (sai->mclk_direction_output && 1479 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1480 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1481 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1482 } 1483 1484 ret = pm_runtime_put_sync(dev); 1485 if (ret < 0 && ret != -ENOSYS) 1486 goto err_pm_get_sync; 1487 1488 /* 1489 * Register platform component before registering cpu dai for there 1490 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1491 */ 1492 if (sai->soc_data->use_imx_pcm) { 1493 ret = imx_pcm_dma_init(pdev); 1494 if (ret) { 1495 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1496 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1497 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1498 goto err_pm_get_sync; 1499 } 1500 } else { 1501 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1502 if (ret) { 1503 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1504 goto err_pm_get_sync; 1505 } 1506 } 1507 1508 ret = devm_snd_soc_register_component(dev, &fsl_component, 1509 &sai->cpu_dai_drv, 1); 1510 if (ret) 1511 goto err_pm_get_sync; 1512 1513 return ret; 1514 1515err_pm_get_sync: 1516 if (!pm_runtime_status_suspended(dev)) 1517 fsl_sai_runtime_suspend(dev); 1518err_pm_disable: 1519 pm_runtime_disable(dev); 1520 1521 return ret; 1522} 1523 1524static void fsl_sai_remove(struct platform_device *pdev) 1525{ 1526 pm_runtime_disable(&pdev->dev); 1527 if (!pm_runtime_status_suspended(&pdev->dev)) 1528 fsl_sai_runtime_suspend(&pdev->dev); 1529} 1530 1531static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1532 .use_imx_pcm = false, 1533 .use_edma = false, 1534 .fifo_depth = 32, 1535 .pins = 1, 1536 .reg_offset = 0, 1537 .mclk0_is_mclk1 = false, 1538 .flags = 0, 1539 .max_register = FSL_SAI_RMR, 1540}; 1541 1542static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1543 .use_imx_pcm = true, 1544 .use_edma = false, 1545 .fifo_depth = 32, 1546 .pins = 1, 1547 .reg_offset = 0, 1548 .mclk0_is_mclk1 = true, 1549 .flags = 0, 1550 .max_register = FSL_SAI_RMR, 1551}; 1552 1553static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1554 .use_imx_pcm = true, 1555 .use_edma = false, 1556 .fifo_depth = 16, 1557 .pins = 2, 1558 .reg_offset = 8, 1559 .mclk0_is_mclk1 = false, 1560 .flags = PMQOS_CPU_LATENCY, 1561 .max_register = FSL_SAI_RMR, 1562}; 1563 1564static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1565 .use_imx_pcm = true, 1566 .use_edma = false, 1567 .fifo_depth = 128, 1568 .pins = 8, 1569 .reg_offset = 8, 1570 .mclk0_is_mclk1 = false, 1571 .flags = 0, 1572 .max_register = FSL_SAI_RMR, 1573}; 1574 1575static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1576 .use_imx_pcm = true, 1577 .use_edma = true, 1578 .fifo_depth = 64, 1579 .pins = 4, 1580 .reg_offset = 0, 1581 .mclk0_is_mclk1 = false, 1582 .flags = 0, 1583 .max_register = FSL_SAI_RMR, 1584}; 1585 1586static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1587 .use_imx_pcm = true, 1588 .use_edma = false, 1589 .fifo_depth = 128, 1590 .reg_offset = 8, 1591 .mclk0_is_mclk1 = false, 1592 .pins = 8, 1593 .flags = 0, 1594 .max_register = FSL_SAI_MCTL, 1595}; 1596 1597static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1598 .use_imx_pcm = true, 1599 .use_edma = false, 1600 .fifo_depth = 128, 1601 .reg_offset = 8, 1602 .mclk0_is_mclk1 = false, 1603 .pins = 8, 1604 .flags = 0, 1605 .max_register = FSL_SAI_MDIV, 1606}; 1607 1608static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1609 .use_imx_pcm = true, 1610 .use_edma = false, 1611 .fifo_depth = 128, 1612 .reg_offset = 8, 1613 .mclk0_is_mclk1 = false, 1614 .pins = 8, 1615 .flags = 0, 1616 .max_register = FSL_SAI_MDIV, 1617 .mclk_with_tere = true, 1618}; 1619 1620static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1621 .use_imx_pcm = true, 1622 .use_edma = true, 1623 .fifo_depth = 16, 1624 .reg_offset = 8, 1625 .mclk0_is_mclk1 = false, 1626 .pins = 4, 1627 .flags = PMQOS_CPU_LATENCY, 1628 .max_register = FSL_SAI_RTCAP, 1629}; 1630 1631static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1632 .use_imx_pcm = true, 1633 .use_edma = true, 1634 .fifo_depth = 128, 1635 .reg_offset = 8, 1636 .mclk0_is_mclk1 = false, 1637 .pins = 4, 1638 .flags = 0, 1639 .max_register = FSL_SAI_MCTL, 1640 .max_burst = {8, 8}, 1641}; 1642 1643static const struct of_device_id fsl_sai_ids[] = { 1644 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1645 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1646 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1647 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1648 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1649 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1650 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1651 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1652 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1653 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1654 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1655 { /* sentinel */ } 1656}; 1657MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1658 1659static int fsl_sai_runtime_suspend(struct device *dev) 1660{ 1661 struct fsl_sai *sai = dev_get_drvdata(dev); 1662 1663 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1664 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1665 1666 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1667 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1668 1669 clk_disable_unprepare(sai->bus_clk); 1670 1671 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1672 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1673 1674 regcache_cache_only(sai->regmap, true); 1675 1676 return 0; 1677} 1678 1679static int fsl_sai_runtime_resume(struct device *dev) 1680{ 1681 struct fsl_sai *sai = dev_get_drvdata(dev); 1682 unsigned int ofs = sai->soc_data->reg_offset; 1683 int ret; 1684 1685 ret = clk_prepare_enable(sai->bus_clk); 1686 if (ret) { 1687 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1688 return ret; 1689 } 1690 1691 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1692 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1693 if (ret) 1694 goto disable_bus_clk; 1695 } 1696 1697 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1698 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1699 if (ret) 1700 goto disable_tx_clk; 1701 } 1702 1703 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1704 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1705 1706 regcache_cache_only(sai->regmap, false); 1707 regcache_mark_dirty(sai->regmap); 1708 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1709 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1710 usleep_range(1000, 2000); 1711 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1712 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1713 1714 ret = regcache_sync(sai->regmap); 1715 if (ret) 1716 goto disable_rx_clk; 1717 1718 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1719 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1720 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1721 1722 return 0; 1723 1724disable_rx_clk: 1725 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1726 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1727disable_tx_clk: 1728 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1729 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1730disable_bus_clk: 1731 clk_disable_unprepare(sai->bus_clk); 1732 1733 return ret; 1734} 1735 1736static const struct dev_pm_ops fsl_sai_pm_ops = { 1737 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1738 fsl_sai_runtime_resume, NULL) 1739 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1740 pm_runtime_force_resume) 1741}; 1742 1743static struct platform_driver fsl_sai_driver = { 1744 .probe = fsl_sai_probe, 1745 .remove_new = fsl_sai_remove, 1746 .driver = { 1747 .name = "fsl-sai", 1748 .pm = &fsl_sai_pm_ops, 1749 .of_match_table = fsl_sai_ids, 1750 }, 1751}; 1752module_platform_driver(fsl_sai_driver); 1753 1754MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1755MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1756MODULE_ALIAS("platform:fsl-sai"); 1757MODULE_LICENSE("GPL"); 1758