1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2// Copyright 2018 NXP
3
4#include <linux/bitfield.h>
5#include <linux/clk.h>
6#include <linux/device.h>
7#include <linux/interrupt.h>
8#include <linux/kobject.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/sysfs.h>
18#include <linux/types.h>
19#include <linux/dma/imx-dma.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm.h>
22#include <sound/soc.h>
23#include <sound/tlv.h>
24#include <sound/core.h>
25
26#include "fsl_micfil.h"
27#include "fsl_utils.h"
28
29#define MICFIL_OSR_DEFAULT	16
30
31enum quality {
32	QUALITY_HIGH,
33	QUALITY_MEDIUM,
34	QUALITY_LOW,
35	QUALITY_VLOW0,
36	QUALITY_VLOW1,
37	QUALITY_VLOW2,
38};
39
40struct fsl_micfil {
41	struct platform_device *pdev;
42	struct regmap *regmap;
43	const struct fsl_micfil_soc_data *soc;
44	struct clk *busclk;
45	struct clk *mclk;
46	struct clk *pll8k_clk;
47	struct clk *pll11k_clk;
48	struct snd_dmaengine_dai_dma_data dma_params_rx;
49	struct sdma_peripheral_config sdmacfg;
50	struct snd_soc_card *card;
51	unsigned int dataline;
52	char name[32];
53	int irq[MICFIL_IRQ_LINES];
54	enum quality quality;
55	int dc_remover;
56	int vad_init_mode;
57	int vad_enabled;
58	int vad_detected;
59	struct fsl_micfil_verid verid;
60	struct fsl_micfil_param param;
61};
62
63struct fsl_micfil_soc_data {
64	unsigned int fifos;
65	unsigned int fifo_depth;
66	unsigned int dataline;
67	bool imx;
68	bool use_edma;
69	bool use_verid;
70	u64  formats;
71};
72
73static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
74	.imx = true,
75	.fifos = 8,
76	.fifo_depth = 8,
77	.dataline =  0xf,
78	.formats = SNDRV_PCM_FMTBIT_S16_LE,
79};
80
81static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
82	.imx = true,
83	.fifos = 8,
84	.fifo_depth = 32,
85	.dataline =  0xf,
86	.formats = SNDRV_PCM_FMTBIT_S32_LE,
87};
88
89static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
90	.imx = true,
91	.fifos = 8,
92	.fifo_depth = 32,
93	.dataline =  0xf,
94	.formats = SNDRV_PCM_FMTBIT_S32_LE,
95	.use_edma = true,
96	.use_verid = true,
97};
98
99static const struct of_device_id fsl_micfil_dt_ids[] = {
100	{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
101	{ .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
102	{ .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
103	{}
104};
105MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
106
107static const char * const micfil_quality_select_texts[] = {
108	[QUALITY_HIGH] = "High",
109	[QUALITY_MEDIUM] = "Medium",
110	[QUALITY_LOW] = "Low",
111	[QUALITY_VLOW0] = "VLow0",
112	[QUALITY_VLOW1] = "Vlow1",
113	[QUALITY_VLOW2] = "Vlow2",
114};
115
116static const struct soc_enum fsl_micfil_quality_enum =
117	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
118			    micfil_quality_select_texts);
119
120static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
121
122static int micfil_set_quality(struct fsl_micfil *micfil)
123{
124	u32 qsel;
125
126	switch (micfil->quality) {
127	case QUALITY_HIGH:
128		qsel = MICFIL_QSEL_HIGH_QUALITY;
129		break;
130	case QUALITY_MEDIUM:
131		qsel = MICFIL_QSEL_MEDIUM_QUALITY;
132		break;
133	case QUALITY_LOW:
134		qsel = MICFIL_QSEL_LOW_QUALITY;
135		break;
136	case QUALITY_VLOW0:
137		qsel = MICFIL_QSEL_VLOW0_QUALITY;
138		break;
139	case QUALITY_VLOW1:
140		qsel = MICFIL_QSEL_VLOW1_QUALITY;
141		break;
142	case QUALITY_VLOW2:
143		qsel = MICFIL_QSEL_VLOW2_QUALITY;
144		break;
145	}
146
147	return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
148				  MICFIL_CTRL2_QSEL,
149				  FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
150}
151
152static int micfil_quality_get(struct snd_kcontrol *kcontrol,
153			      struct snd_ctl_elem_value *ucontrol)
154{
155	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
156	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
157
158	ucontrol->value.integer.value[0] = micfil->quality;
159
160	return 0;
161}
162
163static int micfil_quality_set(struct snd_kcontrol *kcontrol,
164			      struct snd_ctl_elem_value *ucontrol)
165{
166	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
167	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
168
169	micfil->quality = ucontrol->value.integer.value[0];
170
171	return micfil_set_quality(micfil);
172}
173
174static const char * const micfil_hwvad_enable[] = {
175	"Disable (Record only)",
176	"Enable (Record with Vad)",
177};
178
179static const char * const micfil_hwvad_init_mode[] = {
180	"Envelope mode", "Energy mode",
181};
182
183static const char * const micfil_hwvad_hpf_texts[] = {
184	"Filter bypass",
185	"Cut-off @1750Hz",
186	"Cut-off @215Hz",
187	"Cut-off @102Hz",
188};
189
190/*
191 * DC Remover Control
192 * Filter Bypassed	1 1
193 * Cut-off @21Hz	0 0
194 * Cut-off @83Hz	0 1
195 * Cut-off @152HZ	1 0
196 */
197static const char * const micfil_dc_remover_texts[] = {
198	"Cut-off @21Hz", "Cut-off @83Hz",
199	"Cut-off @152Hz", "Bypass",
200};
201
202static const struct soc_enum hwvad_enable_enum =
203	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
204			    micfil_hwvad_enable);
205static const struct soc_enum hwvad_init_mode_enum =
206	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
207			    micfil_hwvad_init_mode);
208static const struct soc_enum hwvad_hpf_enum =
209	SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
210			ARRAY_SIZE(micfil_hwvad_hpf_texts),
211			micfil_hwvad_hpf_texts);
212static const struct soc_enum fsl_micfil_dc_remover_enum =
213	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
214			    micfil_dc_remover_texts);
215
216static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
217				       struct snd_ctl_elem_value *ucontrol)
218{
219	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
220	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
221	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
222	unsigned int *item = ucontrol->value.enumerated.item;
223	int val = snd_soc_enum_item_to_val(e, item[0]);
224	int i = 0, ret = 0;
225	u32 reg_val = 0;
226
227	if (val < 0 || val > 3)
228		return -EINVAL;
229
230	micfil->dc_remover = val;
231
232	/* Calculate total value for all channels */
233	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
234		reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
235
236	/* Update DC Remover mode for all channels */
237	ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
238					    MICFIL_DC_CTRL_CONFIG, reg_val);
239	if (ret < 0)
240		return ret;
241
242	return 0;
243}
244
245static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
246				       struct snd_ctl_elem_value *ucontrol)
247{
248	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
249	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
250
251	ucontrol->value.enumerated.item[0] = micfil->dc_remover;
252
253	return 0;
254}
255
256static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
257			    struct snd_ctl_elem_value *ucontrol)
258{
259	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
260	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
261	unsigned int *item = ucontrol->value.enumerated.item;
262	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
263	int val = snd_soc_enum_item_to_val(e, item[0]);
264
265	micfil->vad_enabled = val;
266
267	return 0;
268}
269
270static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
271			    struct snd_ctl_elem_value *ucontrol)
272{
273	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
274	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
275
276	ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
277
278	return 0;
279}
280
281static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
282			       struct snd_ctl_elem_value *ucontrol)
283{
284	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
285	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
286	unsigned int *item = ucontrol->value.enumerated.item;
287	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
288	int val = snd_soc_enum_item_to_val(e, item[0]);
289
290	/* 0 - Envelope-based Mode
291	 * 1 - Energy-based Mode
292	 */
293	micfil->vad_init_mode = val;
294
295	return 0;
296}
297
298static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
299			       struct snd_ctl_elem_value *ucontrol)
300{
301	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
302	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
303
304	ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
305
306	return 0;
307}
308
309static int hwvad_detected(struct snd_kcontrol *kcontrol,
310			  struct snd_ctl_elem_value *ucontrol)
311{
312	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
313	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
314
315	ucontrol->value.enumerated.item[0] = micfil->vad_detected;
316
317	return 0;
318}
319
320static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
321	SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
322			  MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
323	SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
324			  MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
325	SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
326			  MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
327	SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
328			  MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
329	SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
330			  MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
331	SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
332			  MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
333	SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
334			  MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
335	SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
336			  MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
337	SOC_ENUM_EXT("MICFIL Quality Select",
338		     fsl_micfil_quality_enum,
339		     micfil_quality_get, micfil_quality_set),
340	SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
341		     hwvad_get_enable, hwvad_put_enable),
342	SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
343		     hwvad_get_init_mode, hwvad_put_init_mode),
344	SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
345	SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
346	SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
347		   REG_MICFIL_VAD0_ZCD, 2, 1, 0),
348	SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
349		     micfil_get_dc_remover_state, micfil_put_dc_remover_state),
350	SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
351	SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
352	SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
353	SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
354	SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
355	SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
356	SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
357	SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
358	SOC_SINGLE("HWVAD ZCD And Behavior Switch",
359		   REG_MICFIL_VAD0_ZCD, 4, 1, 0),
360	SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
361};
362
363static int fsl_micfil_use_verid(struct device *dev)
364{
365	struct fsl_micfil *micfil = dev_get_drvdata(dev);
366	unsigned int val;
367	int ret;
368
369	if (!micfil->soc->use_verid)
370		return 0;
371
372	ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
373	if (ret < 0)
374		return ret;
375
376	dev_dbg(dev, "VERID: 0x%016X\n", val);
377
378	micfil->verid.version = val &
379		(MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
380	micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
381	micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
382
383	ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
384	if (ret < 0)
385		return ret;
386
387	dev_dbg(dev, "PARAM: 0x%016X\n", val);
388
389	micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
390		MICFIL_PARAM_NUM_HWVAD_SHIFT;
391	micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
392	micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
393	micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
394	micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
395	micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
396	micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
397	micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
398	micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
399		MICFIL_PARAM_FIFO_PTRWID_SHIFT;
400	micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
401		MICFIL_PARAM_NPAIR_SHIFT;
402
403	return 0;
404}
405
406/* The SRES is a self-negated bit which provides the CPU with the
407 * capability to initialize the PDM Interface module through the
408 * slave-bus interface. This bit always reads as zero, and this
409 * bit is only effective when MDIS is cleared
410 */
411static int fsl_micfil_reset(struct device *dev)
412{
413	struct fsl_micfil *micfil = dev_get_drvdata(dev);
414	int ret;
415
416	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
417				MICFIL_CTRL1_MDIS);
418	if (ret)
419		return ret;
420
421	ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
422			      MICFIL_CTRL1_SRES);
423	if (ret)
424		return ret;
425
426	/*
427	 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
428	 * as non-volatile register, so SRES still remain in regmap
429	 * cache after set, that every update of REG_MICFIL_CTRL1,
430	 * software reset happens. so clear it explicitly.
431	 */
432	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
433				MICFIL_CTRL1_SRES);
434	if (ret)
435		return ret;
436
437	/*
438	 * Set SRES should clear CHnF flags, But even add delay here
439	 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
440	 */
441	ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
442	if (ret)
443		return ret;
444
445	return 0;
446}
447
448static int fsl_micfil_startup(struct snd_pcm_substream *substream,
449			      struct snd_soc_dai *dai)
450{
451	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
452
453	if (!micfil) {
454		dev_err(dai->dev, "micfil dai priv_data not set\n");
455		return -EINVAL;
456	}
457
458	return 0;
459}
460
461/* Enable/disable hwvad interrupts */
462static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
463{
464	u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
465	u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
466
467	/* Voice Activity Detector Error Interruption */
468	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
469			   MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
470
471	/* Voice Activity Detector Interruption */
472	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
473			   MICFIL_VAD0_CTRL1_IE, vadie_reg);
474
475	return 0;
476}
477
478/* Configuration done only in energy-based initialization mode */
479static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
480{
481	/* Keep the VADFRENDIS bitfield cleared. */
482	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
483			  MICFIL_VAD0_CTRL2_FRENDIS);
484
485	/* Keep the VADPREFEN bitfield cleared. */
486	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
487			  MICFIL_VAD0_CTRL2_PREFEN);
488
489	/* Keep the VADSFILEN bitfield cleared. */
490	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
491			  MICFIL_VAD0_SCONFIG_SFILEN);
492
493	/* Keep the VADSMAXEN bitfield cleared. */
494	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
495			  MICFIL_VAD0_SCONFIG_SMAXEN);
496
497	/* Keep the VADNFILAUTO bitfield asserted. */
498	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
499			MICFIL_VAD0_NCONFIG_NFILAUT);
500
501	/* Keep the VADNMINEN bitfield cleared. */
502	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
503			  MICFIL_VAD0_NCONFIG_NMINEN);
504
505	/* Keep the VADNDECEN bitfield cleared. */
506	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
507			  MICFIL_VAD0_NCONFIG_NDECEN);
508
509	/* Keep the VADNOREN bitfield cleared. */
510	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
511			  MICFIL_VAD0_NCONFIG_NOREN);
512
513	return 0;
514}
515
516/* Configuration done only in envelope-based initialization mode */
517static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
518{
519	/* Assert the VADFRENDIS bitfield */
520	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
521			MICFIL_VAD0_CTRL2_FRENDIS);
522
523	/* Assert the VADPREFEN bitfield. */
524	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
525			MICFIL_VAD0_CTRL2_PREFEN);
526
527	/* Assert the VADSFILEN bitfield. */
528	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
529			MICFIL_VAD0_SCONFIG_SFILEN);
530
531	/* Assert the VADSMAXEN bitfield. */
532	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
533			MICFIL_VAD0_SCONFIG_SMAXEN);
534
535	/* Clear the VADNFILAUTO bitfield */
536	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
537			  MICFIL_VAD0_NCONFIG_NFILAUT);
538
539	/* Assert the VADNMINEN bitfield. */
540	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
541			MICFIL_VAD0_NCONFIG_NMINEN);
542
543	/* Assert the VADNDECEN bitfield. */
544	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
545			MICFIL_VAD0_NCONFIG_NDECEN);
546
547	/* Assert VADNOREN bitfield. */
548	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
549			MICFIL_VAD0_NCONFIG_NOREN);
550
551	return 0;
552}
553
554/*
555 * Hardware Voice Active Detection: The HWVAD takes data from the input
556 * of a selected PDM microphone to detect if there is any
557 * voice activity. When a voice activity is detected, an interrupt could
558 * be delivered to the system. Initialization in section 8.4:
559 * Can work in two modes:
560 *  -> Eneveope-based mode (section 8.4.1)
561 *  -> Energy-based mode (section 8.4.2)
562 *
563 * It is important to remark that the HWVAD detector could be enabled
564 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
565 * bit in STAT register is cleared
566 */
567static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
568{
569	int ret;
570
571	micfil->vad_detected = 0;
572
573	/* envelope-based specific initialization */
574	if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
575		ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
576	else
577		ret = fsl_micfil_init_hwvad_energy_mode(micfil);
578	if (ret)
579		return ret;
580
581	/* Voice Activity Detector Internal Filters Initialization*/
582	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
583			MICFIL_VAD0_CTRL1_ST10);
584
585	/* Voice Activity Detector Internal Filter */
586	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
587			  MICFIL_VAD0_CTRL1_ST10);
588
589	/* Enable Interrupts */
590	ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
591	if (ret)
592		return ret;
593
594	/* Voice Activity Detector Reset */
595	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
596			MICFIL_VAD0_CTRL1_RST);
597
598	/* Voice Activity Detector Enabled */
599	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
600			MICFIL_VAD0_CTRL1_EN);
601
602	return 0;
603}
604
605static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
606{
607	struct device *dev = &micfil->pdev->dev;
608	int ret = 0;
609
610	/* Disable HWVAD */
611	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
612			  MICFIL_VAD0_CTRL1_EN);
613
614	/* Disable hwvad interrupts */
615	ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
616	if (ret)
617		dev_err(dev, "Failed to disable interrupts\n");
618
619	return ret;
620}
621
622static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
623			      struct snd_soc_dai *dai)
624{
625	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
626	struct device *dev = &micfil->pdev->dev;
627	int ret;
628
629	switch (cmd) {
630	case SNDRV_PCM_TRIGGER_START:
631	case SNDRV_PCM_TRIGGER_RESUME:
632	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
633		ret = fsl_micfil_reset(dev);
634		if (ret) {
635			dev_err(dev, "failed to soft reset\n");
636			return ret;
637		}
638
639		/* DMA Interrupt Selection - DISEL bits
640		 * 00 - DMA and IRQ disabled
641		 * 01 - DMA req enabled
642		 * 10 - IRQ enabled
643		 * 11 - reserved
644		 */
645		ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
646				MICFIL_CTRL1_DISEL,
647				FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
648		if (ret)
649			return ret;
650
651		/* Enable the module */
652		ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
653				      MICFIL_CTRL1_PDMIEN);
654		if (ret)
655			return ret;
656
657		if (micfil->vad_enabled)
658			fsl_micfil_hwvad_enable(micfil);
659
660		break;
661	case SNDRV_PCM_TRIGGER_STOP:
662	case SNDRV_PCM_TRIGGER_SUSPEND:
663	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
664		if (micfil->vad_enabled)
665			fsl_micfil_hwvad_disable(micfil);
666
667		/* Disable the module */
668		ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
669					MICFIL_CTRL1_PDMIEN);
670		if (ret)
671			return ret;
672
673		ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
674				MICFIL_CTRL1_DISEL,
675				FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
676		if (ret)
677			return ret;
678		break;
679	default:
680		return -EINVAL;
681	}
682	return 0;
683}
684
685static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
686{
687	struct device *dev = &micfil->pdev->dev;
688	u64 ratio = sample_rate;
689	struct clk *clk;
690	int ret;
691
692	/* Get root clock */
693	clk = micfil->mclk;
694
695	/* Disable clock first, for it was enabled by pm_runtime */
696	clk_disable_unprepare(clk);
697	fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
698				     micfil->pll11k_clk, ratio);
699	ret = clk_prepare_enable(clk);
700	if (ret)
701		return ret;
702
703	return 0;
704}
705
706static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
707				struct snd_pcm_hw_params *params,
708				struct snd_soc_dai *dai)
709{
710	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
711	unsigned int channels = params_channels(params);
712	unsigned int rate = params_rate(params);
713	int clk_div = 8;
714	int osr = MICFIL_OSR_DEFAULT;
715	int ret;
716
717	/* 1. Disable the module */
718	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
719				MICFIL_CTRL1_PDMIEN);
720	if (ret)
721		return ret;
722
723	/* enable channels */
724	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
725				 0xFF, ((1 << channels) - 1));
726	if (ret)
727		return ret;
728
729	ret = fsl_micfil_reparent_rootclk(micfil, rate);
730	if (ret)
731		return ret;
732
733	ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
734	if (ret)
735		return ret;
736
737	ret = micfil_set_quality(micfil);
738	if (ret)
739		return ret;
740
741	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
742				 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
743				 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
744				 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
745
746	/* Configure CIC OSR in VADCICOSR */
747	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
748			   MICFIL_VAD0_CTRL1_CICOSR,
749			   FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
750
751	/* Configure source channel in VADCHSEL */
752	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
753			   MICFIL_VAD0_CTRL1_CHSEL,
754			   FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
755
756	micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
757	micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
758	micfil->sdmacfg.n_fifos_src = channels;
759	micfil->sdmacfg.sw_done = true;
760	micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
761	if (micfil->soc->use_edma)
762		micfil->dma_params_rx.maxburst = channels;
763
764	return 0;
765}
766
767static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
768{
769	struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
770	struct device *dev = cpu_dai->dev;
771	unsigned int val = 0;
772	int ret, i;
773
774	micfil->quality = QUALITY_VLOW0;
775	micfil->card = cpu_dai->component->card;
776
777	/* set default gain to 2 */
778	regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
779
780	/* set DC Remover in bypass mode*/
781	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
782		val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
783	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
784				 MICFIL_DC_CTRL_CONFIG, val);
785	if (ret) {
786		dev_err(dev, "failed to set DC Remover mode bits\n");
787		return ret;
788	}
789	micfil->dc_remover = MICFIL_DC_BYPASS;
790
791	snd_soc_dai_init_dma_data(cpu_dai, NULL,
792				  &micfil->dma_params_rx);
793
794	/* FIFO Watermark Control - FIFOWMK*/
795	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
796			MICFIL_FIFO_CTRL_FIFOWMK,
797			FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
798	if (ret)
799		return ret;
800
801	return 0;
802}
803
804static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
805	.probe		= fsl_micfil_dai_probe,
806	.startup	= fsl_micfil_startup,
807	.trigger	= fsl_micfil_trigger,
808	.hw_params	= fsl_micfil_hw_params,
809};
810
811static struct snd_soc_dai_driver fsl_micfil_dai = {
812	.capture = {
813		.stream_name = "CPU-Capture",
814		.channels_min = 1,
815		.channels_max = 8,
816		.rates = SNDRV_PCM_RATE_8000_48000,
817		.formats = SNDRV_PCM_FMTBIT_S16_LE,
818	},
819	.ops = &fsl_micfil_dai_ops,
820};
821
822static const struct snd_soc_component_driver fsl_micfil_component = {
823	.name		= "fsl-micfil-dai",
824	.controls       = fsl_micfil_snd_controls,
825	.num_controls   = ARRAY_SIZE(fsl_micfil_snd_controls),
826	.legacy_dai_naming      = 1,
827};
828
829/* REGMAP */
830static const struct reg_default fsl_micfil_reg_defaults[] = {
831	{REG_MICFIL_CTRL1,		0x00000000},
832	{REG_MICFIL_CTRL2,		0x00000000},
833	{REG_MICFIL_STAT,		0x00000000},
834	{REG_MICFIL_FIFO_CTRL,		0x00000007},
835	{REG_MICFIL_FIFO_STAT,		0x00000000},
836	{REG_MICFIL_DATACH0,		0x00000000},
837	{REG_MICFIL_DATACH1,		0x00000000},
838	{REG_MICFIL_DATACH2,		0x00000000},
839	{REG_MICFIL_DATACH3,		0x00000000},
840	{REG_MICFIL_DATACH4,		0x00000000},
841	{REG_MICFIL_DATACH5,		0x00000000},
842	{REG_MICFIL_DATACH6,		0x00000000},
843	{REG_MICFIL_DATACH7,		0x00000000},
844	{REG_MICFIL_DC_CTRL,		0x00000000},
845	{REG_MICFIL_OUT_CTRL,		0x00000000},
846	{REG_MICFIL_OUT_STAT,		0x00000000},
847	{REG_MICFIL_VAD0_CTRL1,		0x00000000},
848	{REG_MICFIL_VAD0_CTRL2,		0x000A0000},
849	{REG_MICFIL_VAD0_STAT,		0x00000000},
850	{REG_MICFIL_VAD0_SCONFIG,	0x00000000},
851	{REG_MICFIL_VAD0_NCONFIG,	0x80000000},
852	{REG_MICFIL_VAD0_NDATA,		0x00000000},
853	{REG_MICFIL_VAD0_ZCD,		0x00000004},
854};
855
856static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
857{
858	switch (reg) {
859	case REG_MICFIL_CTRL1:
860	case REG_MICFIL_CTRL2:
861	case REG_MICFIL_STAT:
862	case REG_MICFIL_FIFO_CTRL:
863	case REG_MICFIL_FIFO_STAT:
864	case REG_MICFIL_DATACH0:
865	case REG_MICFIL_DATACH1:
866	case REG_MICFIL_DATACH2:
867	case REG_MICFIL_DATACH3:
868	case REG_MICFIL_DATACH4:
869	case REG_MICFIL_DATACH5:
870	case REG_MICFIL_DATACH6:
871	case REG_MICFIL_DATACH7:
872	case REG_MICFIL_DC_CTRL:
873	case REG_MICFIL_OUT_CTRL:
874	case REG_MICFIL_OUT_STAT:
875	case REG_MICFIL_FSYNC_CTRL:
876	case REG_MICFIL_VERID:
877	case REG_MICFIL_PARAM:
878	case REG_MICFIL_VAD0_CTRL1:
879	case REG_MICFIL_VAD0_CTRL2:
880	case REG_MICFIL_VAD0_STAT:
881	case REG_MICFIL_VAD0_SCONFIG:
882	case REG_MICFIL_VAD0_NCONFIG:
883	case REG_MICFIL_VAD0_NDATA:
884	case REG_MICFIL_VAD0_ZCD:
885		return true;
886	default:
887		return false;
888	}
889}
890
891static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
892{
893	switch (reg) {
894	case REG_MICFIL_CTRL1:
895	case REG_MICFIL_CTRL2:
896	case REG_MICFIL_STAT:		/* Write 1 to Clear */
897	case REG_MICFIL_FIFO_CTRL:
898	case REG_MICFIL_FIFO_STAT:	/* Write 1 to Clear */
899	case REG_MICFIL_DC_CTRL:
900	case REG_MICFIL_OUT_CTRL:
901	case REG_MICFIL_OUT_STAT:	/* Write 1 to Clear */
902	case REG_MICFIL_FSYNC_CTRL:
903	case REG_MICFIL_VAD0_CTRL1:
904	case REG_MICFIL_VAD0_CTRL2:
905	case REG_MICFIL_VAD0_STAT:	/* Write 1 to Clear */
906	case REG_MICFIL_VAD0_SCONFIG:
907	case REG_MICFIL_VAD0_NCONFIG:
908	case REG_MICFIL_VAD0_ZCD:
909		return true;
910	default:
911		return false;
912	}
913}
914
915static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
916{
917	switch (reg) {
918	case REG_MICFIL_STAT:
919	case REG_MICFIL_DATACH0:
920	case REG_MICFIL_DATACH1:
921	case REG_MICFIL_DATACH2:
922	case REG_MICFIL_DATACH3:
923	case REG_MICFIL_DATACH4:
924	case REG_MICFIL_DATACH5:
925	case REG_MICFIL_DATACH6:
926	case REG_MICFIL_DATACH7:
927	case REG_MICFIL_VERID:
928	case REG_MICFIL_PARAM:
929	case REG_MICFIL_VAD0_STAT:
930	case REG_MICFIL_VAD0_NDATA:
931		return true;
932	default:
933		return false;
934	}
935}
936
937static const struct regmap_config fsl_micfil_regmap_config = {
938	.reg_bits = 32,
939	.reg_stride = 4,
940	.val_bits = 32,
941
942	.max_register = REG_MICFIL_VAD0_ZCD,
943	.reg_defaults = fsl_micfil_reg_defaults,
944	.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
945	.readable_reg = fsl_micfil_readable_reg,
946	.volatile_reg = fsl_micfil_volatile_reg,
947	.writeable_reg = fsl_micfil_writeable_reg,
948	.cache_type = REGCACHE_RBTREE,
949};
950
951/* END OF REGMAP */
952
953static irqreturn_t micfil_isr(int irq, void *devid)
954{
955	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
956	struct platform_device *pdev = micfil->pdev;
957	u32 stat_reg;
958	u32 fifo_stat_reg;
959	u32 ctrl1_reg;
960	bool dma_enabled;
961	int i;
962
963	regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
964	regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
965	regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
966
967	dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
968
969	/* Channel 0-7 Output Data Flags */
970	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
971		if (stat_reg & MICFIL_STAT_CHXF(i))
972			dev_dbg(&pdev->dev,
973				"Data available in Data Channel %d\n", i);
974		/* if DMA is not enabled, field must be written with 1
975		 * to clear
976		 */
977		if (!dma_enabled)
978			regmap_write_bits(micfil->regmap,
979					  REG_MICFIL_STAT,
980					  MICFIL_STAT_CHXF(i),
981					  1);
982	}
983
984	for (i = 0; i < MICFIL_FIFO_NUM; i++) {
985		if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
986			dev_dbg(&pdev->dev,
987				"FIFO Overflow Exception flag for channel %d\n",
988				i);
989
990		if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
991			dev_dbg(&pdev->dev,
992				"FIFO Underflow Exception flag for channel %d\n",
993				i);
994	}
995
996	return IRQ_HANDLED;
997}
998
999static irqreturn_t micfil_err_isr(int irq, void *devid)
1000{
1001	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1002	struct platform_device *pdev = micfil->pdev;
1003	u32 stat_reg;
1004
1005	regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1006
1007	if (stat_reg & MICFIL_STAT_BSY_FIL)
1008		dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1009
1010	if (stat_reg & MICFIL_STAT_FIR_RDY)
1011		dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1012
1013	if (stat_reg & MICFIL_STAT_LOWFREQF) {
1014		dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1015		regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1016				  MICFIL_STAT_LOWFREQF, 1);
1017	}
1018
1019	return IRQ_HANDLED;
1020}
1021
1022static irqreturn_t voice_detected_fn(int irq, void *devid)
1023{
1024	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1025	struct snd_kcontrol *kctl;
1026
1027	if (!micfil->card)
1028		return IRQ_HANDLED;
1029
1030	kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1031	if (!kctl)
1032		return IRQ_HANDLED;
1033
1034	if (micfil->vad_detected)
1035		snd_ctl_notify(micfil->card->snd_card,
1036			       SNDRV_CTL_EVENT_MASK_VALUE,
1037			       &kctl->id);
1038
1039	return IRQ_HANDLED;
1040}
1041
1042static irqreturn_t hwvad_isr(int irq, void *devid)
1043{
1044	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1045	struct device *dev = &micfil->pdev->dev;
1046	u32 vad0_reg;
1047	int ret;
1048
1049	regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1050
1051	/*
1052	 * The only difference between MICFIL_VAD0_STAT_EF and
1053	 * MICFIL_VAD0_STAT_IF is that the former requires Write
1054	 * 1 to Clear. Since both flags are set, it is enough
1055	 * to only read one of them
1056	 */
1057	if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1058		/* Write 1 to clear */
1059		regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1060				  MICFIL_VAD0_STAT_IF,
1061				  MICFIL_VAD0_STAT_IF);
1062
1063		micfil->vad_detected = 1;
1064	}
1065
1066	ret = fsl_micfil_hwvad_disable(micfil);
1067	if (ret)
1068		dev_err(dev, "Failed to disable hwvad\n");
1069
1070	return IRQ_WAKE_THREAD;
1071}
1072
1073static irqreturn_t hwvad_err_isr(int irq, void *devid)
1074{
1075	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1076	struct device *dev = &micfil->pdev->dev;
1077	u32 vad0_reg;
1078
1079	regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1080
1081	if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1082		dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1083
1084	return IRQ_HANDLED;
1085}
1086
1087static int fsl_micfil_runtime_suspend(struct device *dev);
1088static int fsl_micfil_runtime_resume(struct device *dev);
1089
1090static int fsl_micfil_probe(struct platform_device *pdev)
1091{
1092	struct device_node *np = pdev->dev.of_node;
1093	struct fsl_micfil *micfil;
1094	struct resource *res;
1095	void __iomem *regs;
1096	int ret, i;
1097
1098	micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1099	if (!micfil)
1100		return -ENOMEM;
1101
1102	micfil->pdev = pdev;
1103	strscpy(micfil->name, np->name, sizeof(micfil->name));
1104
1105	micfil->soc = of_device_get_match_data(&pdev->dev);
1106
1107	/* ipg_clk is used to control the registers
1108	 * ipg_clk_app is used to operate the filter
1109	 */
1110	micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1111	if (IS_ERR(micfil->mclk)) {
1112		dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1113			PTR_ERR(micfil->mclk));
1114		return PTR_ERR(micfil->mclk);
1115	}
1116
1117	micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1118	if (IS_ERR(micfil->busclk)) {
1119		dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1120			PTR_ERR(micfil->busclk));
1121		return PTR_ERR(micfil->busclk);
1122	}
1123
1124	fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1125				&micfil->pll11k_clk);
1126
1127	/* init regmap */
1128	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1129	if (IS_ERR(regs))
1130		return PTR_ERR(regs);
1131
1132	micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1133					       regs,
1134					       &fsl_micfil_regmap_config);
1135	if (IS_ERR(micfil->regmap)) {
1136		dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1137			PTR_ERR(micfil->regmap));
1138		return PTR_ERR(micfil->regmap);
1139	}
1140
1141	/* dataline mask for RX */
1142	ret = of_property_read_u32_index(np,
1143					 "fsl,dataline",
1144					 0,
1145					 &micfil->dataline);
1146	if (ret)
1147		micfil->dataline = 1;
1148
1149	if (micfil->dataline & ~micfil->soc->dataline) {
1150		dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1151			micfil->soc->dataline);
1152		return -EINVAL;
1153	}
1154
1155	/* get IRQs */
1156	for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1157		micfil->irq[i] = platform_get_irq(pdev, i);
1158		if (micfil->irq[i] < 0)
1159			return micfil->irq[i];
1160	}
1161
1162	/* Digital Microphone interface interrupt */
1163	ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1164			       micfil_isr, IRQF_SHARED,
1165			       micfil->name, micfil);
1166	if (ret) {
1167		dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1168			micfil->irq[0]);
1169		return ret;
1170	}
1171
1172	/* Digital Microphone interface error interrupt */
1173	ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1174			       micfil_err_isr, IRQF_SHARED,
1175			       micfil->name, micfil);
1176	if (ret) {
1177		dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1178			micfil->irq[1]);
1179		return ret;
1180	}
1181
1182	/* Digital Microphone interface voice activity detector event */
1183	ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1184					hwvad_isr, voice_detected_fn,
1185					IRQF_SHARED, micfil->name, micfil);
1186	if (ret) {
1187		dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1188			micfil->irq[0]);
1189		return ret;
1190	}
1191
1192	/* Digital Microphone interface voice activity detector error */
1193	ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1194			       hwvad_err_isr, IRQF_SHARED,
1195			       micfil->name, micfil);
1196	if (ret) {
1197		dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1198			micfil->irq[1]);
1199		return ret;
1200	}
1201
1202	micfil->dma_params_rx.chan_name = "rx";
1203	micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
1204	micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1205
1206	platform_set_drvdata(pdev, micfil);
1207
1208	pm_runtime_enable(&pdev->dev);
1209	if (!pm_runtime_enabled(&pdev->dev)) {
1210		ret = fsl_micfil_runtime_resume(&pdev->dev);
1211		if (ret)
1212			goto err_pm_disable;
1213	}
1214
1215	ret = pm_runtime_resume_and_get(&pdev->dev);
1216	if (ret < 0)
1217		goto err_pm_get_sync;
1218
1219	/* Get micfil version */
1220	ret = fsl_micfil_use_verid(&pdev->dev);
1221	if (ret < 0)
1222		dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1223
1224	ret = pm_runtime_put_sync(&pdev->dev);
1225	if (ret < 0 && ret != -ENOSYS)
1226		goto err_pm_get_sync;
1227
1228	regcache_cache_only(micfil->regmap, true);
1229
1230	/*
1231	 * Register platform component before registering cpu dai for there
1232	 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1233	 */
1234	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1235	if (ret) {
1236		dev_err(&pdev->dev, "failed to pcm register\n");
1237		goto err_pm_disable;
1238	}
1239
1240	fsl_micfil_dai.capture.formats = micfil->soc->formats;
1241
1242	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1243					      &fsl_micfil_dai, 1);
1244	if (ret) {
1245		dev_err(&pdev->dev, "failed to register component %s\n",
1246			fsl_micfil_component.name);
1247		goto err_pm_disable;
1248	}
1249
1250	return ret;
1251
1252err_pm_get_sync:
1253	if (!pm_runtime_status_suspended(&pdev->dev))
1254		fsl_micfil_runtime_suspend(&pdev->dev);
1255err_pm_disable:
1256	pm_runtime_disable(&pdev->dev);
1257
1258	return ret;
1259}
1260
1261static void fsl_micfil_remove(struct platform_device *pdev)
1262{
1263	pm_runtime_disable(&pdev->dev);
1264}
1265
1266static int fsl_micfil_runtime_suspend(struct device *dev)
1267{
1268	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1269
1270	regcache_cache_only(micfil->regmap, true);
1271
1272	clk_disable_unprepare(micfil->mclk);
1273	clk_disable_unprepare(micfil->busclk);
1274
1275	return 0;
1276}
1277
1278static int fsl_micfil_runtime_resume(struct device *dev)
1279{
1280	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1281	int ret;
1282
1283	ret = clk_prepare_enable(micfil->busclk);
1284	if (ret < 0)
1285		return ret;
1286
1287	ret = clk_prepare_enable(micfil->mclk);
1288	if (ret < 0) {
1289		clk_disable_unprepare(micfil->busclk);
1290		return ret;
1291	}
1292
1293	regcache_cache_only(micfil->regmap, false);
1294	regcache_mark_dirty(micfil->regmap);
1295	regcache_sync(micfil->regmap);
1296
1297	return 0;
1298}
1299
1300static const struct dev_pm_ops fsl_micfil_pm_ops = {
1301	SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
1302			   fsl_micfil_runtime_resume,
1303			   NULL)
1304	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1305				pm_runtime_force_resume)
1306};
1307
1308static struct platform_driver fsl_micfil_driver = {
1309	.probe = fsl_micfil_probe,
1310	.remove_new = fsl_micfil_remove,
1311	.driver = {
1312		.name = "fsl-micfil-dai",
1313		.pm = &fsl_micfil_pm_ops,
1314		.of_match_table = fsl_micfil_dt_ids,
1315	},
1316};
1317module_platform_driver(fsl_micfil_driver);
1318
1319MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1320MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1321MODULE_LICENSE("Dual BSD/GPL");
1322