1// SPDX-License-Identifier: GPL-2.0-only 2// 3// rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver 4// 5// Copyright(c) 2023 Realtek Semiconductor Corp. 6// 7// 8 9#include <linux/bitops.h> 10#include <sound/core.h> 11#include <linux/delay.h> 12#include <linux/init.h> 13#include <sound/initval.h> 14#include <sound/jack.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/moduleparam.h> 18#include <sound/pcm.h> 19#include <linux/pm_runtime.h> 20#include <sound/pcm_params.h> 21#include <linux/soundwire/sdw_registers.h> 22#include <linux/slab.h> 23#include <sound/soc-dapm.h> 24#include <sound/tlv.h> 25 26#include "rt722-sdca.h" 27 28int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, 29 unsigned int nid, unsigned int reg, unsigned int value) 30{ 31 struct regmap *regmap = rt722->mbq_regmap; 32 unsigned int addr = (nid << 20) | reg; 33 int ret; 34 35 ret = regmap_write(regmap, addr, value); 36 if (ret < 0) 37 dev_err(&rt722->slave->dev, 38 "Failed to set private value: %06x <= %04x ret=%d\n", 39 addr, value, ret); 40 41 return ret; 42} 43 44int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, 45 unsigned int nid, unsigned int reg, unsigned int *value) 46{ 47 int ret; 48 struct regmap *regmap = rt722->mbq_regmap; 49 unsigned int addr = (nid << 20) | reg; 50 51 ret = regmap_read(regmap, addr, value); 52 if (ret < 0) 53 dev_err(&rt722->slave->dev, 54 "Failed to get private value: %06x => %04x ret=%d\n", 55 addr, *value, ret); 56 57 return ret; 58} 59 60static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722, 61 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val) 62{ 63 unsigned int tmp; 64 int ret; 65 66 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp); 67 if (ret < 0) 68 return ret; 69 70 set_mask_bits(&tmp, mask, val); 71 return rt722_sdca_index_write(rt722, nid, reg, tmp); 72} 73 74static int rt722_sdca_btn_type(unsigned char *buffer) 75{ 76 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || 77 (*(buffer + 1) == 0x10)) 78 return SND_JACK_BTN_2; 79 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) || 80 (*(buffer + 1) == 0x20)) 81 return SND_JACK_BTN_3; 82 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) || 83 (*(buffer + 1) == 0x40)) 84 return SND_JACK_BTN_0; 85 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) || 86 (*(buffer + 1) == 0x80)) 87 return SND_JACK_BTN_1; 88 89 return 0; 90} 91 92static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722) 93{ 94 unsigned int btn_type = 0, offset, idx, val, owner; 95 int ret; 96 unsigned char buf[3]; 97 98 /* get current UMP message owner */ 99 ret = regmap_read(rt722->regmap, 100 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 101 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 102 if (ret < 0) 103 return 0; 104 105 /* if owner is device then there is no button event from device */ 106 if (owner == 1) 107 return 0; 108 109 /* read UMP message offset */ 110 ret = regmap_read(rt722->regmap, 111 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 112 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 113 if (ret < 0) 114 goto _end_btn_det_; 115 116 for (idx = 0; idx < sizeof(buf); idx++) { 117 ret = regmap_read(rt722->regmap, 118 RT722_BUF_ADDR_HID1 + offset + idx, &val); 119 if (ret < 0) 120 goto _end_btn_det_; 121 buf[idx] = val & 0xff; 122 } 123 124 if (buf[0] == 0x11) 125 btn_type = rt722_sdca_btn_type(&buf[1]); 126 127_end_btn_det_: 128 /* Host is owner, so set back to device */ 129 if (owner == 0) 130 /* set owner to device */ 131 regmap_write(rt722->regmap, 132 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 133 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 134 135 return btn_type; 136} 137 138static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722) 139{ 140 unsigned int det_mode; 141 int ret; 142 143 /* get detected_mode */ 144 ret = regmap_read(rt722->regmap, 145 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 146 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 147 if (ret < 0) 148 goto io_error; 149 150 switch (det_mode) { 151 case 0x00: 152 rt722->jack_type = 0; 153 break; 154 case 0x03: 155 rt722->jack_type = SND_JACK_HEADPHONE; 156 break; 157 case 0x05: 158 rt722->jack_type = SND_JACK_HEADSET; 159 break; 160 } 161 162 /* write selected_mode */ 163 if (det_mode) { 164 ret = regmap_write(rt722->regmap, 165 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 166 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode); 167 if (ret < 0) 168 goto io_error; 169 } 170 171 dev_dbg(&rt722->slave->dev, 172 "%s, detected_mode=0x%x\n", __func__, det_mode); 173 174 return 0; 175 176io_error: 177 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 178 return ret; 179} 180 181static void rt722_sdca_jack_detect_handler(struct work_struct *work) 182{ 183 struct rt722_sdca_priv *rt722 = 184 container_of(work, struct rt722_sdca_priv, jack_detect_work.work); 185 int btn_type = 0, ret; 186 187 if (!rt722->hs_jack) 188 return; 189 190 if (!rt722->component->card || !rt722->component->card->instantiated) 191 return; 192 193 /* SDW_SCP_SDCA_INT_SDCA_6 is used for jack detection */ 194 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_6) { 195 ret = rt722_sdca_headset_detect(rt722); 196 if (ret < 0) 197 return; 198 } 199 200 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 201 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 202 btn_type = rt722_sdca_button_detect(rt722); 203 204 if (rt722->jack_type == 0) 205 btn_type = 0; 206 207 dev_dbg(&rt722->slave->dev, 208 "in %s, jack_type=%d\n", __func__, rt722->jack_type); 209 dev_dbg(&rt722->slave->dev, 210 "in %s, btn_type=0x%x\n", __func__, btn_type); 211 dev_dbg(&rt722->slave->dev, 212 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 213 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 214 215 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 216 SND_JACK_HEADSET | 217 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 218 SND_JACK_BTN_2 | SND_JACK_BTN_3); 219 220 if (btn_type) { 221 /* button released */ 222 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 223 SND_JACK_HEADSET | 224 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 225 SND_JACK_BTN_2 | SND_JACK_BTN_3); 226 227 mod_delayed_work(system_power_efficient_wq, 228 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 229 } 230} 231 232static void rt722_sdca_btn_check_handler(struct work_struct *work) 233{ 234 struct rt722_sdca_priv *rt722 = 235 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work); 236 int btn_type = 0, ret, idx; 237 unsigned int det_mode, offset, val; 238 unsigned char buf[3]; 239 240 ret = regmap_read(rt722->regmap, 241 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 242 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 243 if (ret < 0) 244 goto io_error; 245 246 /* pin attached */ 247 if (det_mode) { 248 /* read UMP message offset */ 249 ret = regmap_read(rt722->regmap, 250 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 251 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 252 if (ret < 0) 253 goto io_error; 254 255 for (idx = 0; idx < sizeof(buf); idx++) { 256 ret = regmap_read(rt722->regmap, 257 RT722_BUF_ADDR_HID1 + offset + idx, &val); 258 if (ret < 0) 259 goto io_error; 260 buf[idx] = val & 0xff; 261 } 262 263 if (buf[0] == 0x11) 264 btn_type = rt722_sdca_btn_type(&buf[1]); 265 } else 266 rt722->jack_type = 0; 267 268 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 269 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 270 SND_JACK_HEADSET | 271 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 272 SND_JACK_BTN_2 | SND_JACK_BTN_3); 273 274 if (btn_type) { 275 /* button released */ 276 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 277 SND_JACK_HEADSET | 278 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 279 SND_JACK_BTN_2 | SND_JACK_BTN_3); 280 281 mod_delayed_work(system_power_efficient_wq, 282 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 283 } 284 285 return; 286 287io_error: 288 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 289} 290 291static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722) 292{ 293 mutex_lock(&rt722->calibrate_mutex); 294 if (rt722->hs_jack) { 295 /* set SCP_SDCA_IntMask1[0]=1 */ 296 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 297 SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6); 298 /* set SCP_SDCA_IntMask2[0]=1 */ 299 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 300 SDW_SCP_SDCA_INTMASK_SDCA_8); 301 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__); 302 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 303 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E); 304 /* set XU(et03h) & XU(et0Dh) to Not bypassed */ 305 regmap_write(rt722->regmap, 306 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, 307 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 308 regmap_write(rt722->regmap, 309 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 310 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 311 /* trigger GE interrupt */ 312 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 313 RT722_GE_RELATED_CTL2, 0x4000, 0x4000); 314 } 315 mutex_unlock(&rt722->calibrate_mutex); 316} 317 318static int rt722_sdca_set_jack_detect(struct snd_soc_component *component, 319 struct snd_soc_jack *hs_jack, void *data) 320{ 321 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 322 int ret; 323 324 rt722->hs_jack = hs_jack; 325 326 ret = pm_runtime_resume_and_get(component->dev); 327 if (ret < 0) { 328 if (ret != -EACCES) { 329 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 330 return ret; 331 } 332 /* pm_runtime not enabled yet */ 333 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 334 return 0; 335 } 336 337 rt722_sdca_jack_init(rt722); 338 339 pm_runtime_mark_last_busy(component->dev); 340 pm_runtime_put_autosuspend(component->dev); 341 342 return 0; 343} 344 345/* For SDCA control DAC/ADC Gain */ 346static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 347 struct snd_ctl_elem_value *ucontrol) 348{ 349 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 350 struct soc_mixer_control *mc = 351 (struct soc_mixer_control *)kcontrol->private_value; 352 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 353 unsigned int read_l, read_r, gain_l_val, gain_r_val; 354 unsigned int adc_vol_flag = 0, changed = 0; 355 unsigned int lvalue, rvalue; 356 const unsigned int interval_offset = 0xc0; 357 const unsigned int tendB = 0xa00; 358 359 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 360 strstr(ucontrol->id.name, "FU0F Capture Volume")) 361 adc_vol_flag = 1; 362 363 regmap_read(rt722->mbq_regmap, mc->reg, &lvalue); 364 regmap_read(rt722->mbq_regmap, mc->rreg, &rvalue); 365 366 /* L Channel */ 367 gain_l_val = ucontrol->value.integer.value[0]; 368 if (gain_l_val > mc->max) 369 gain_l_val = mc->max; 370 371 if (mc->shift == 8) /* boost gain */ 372 gain_l_val = gain_l_val * tendB; 373 else { 374 /* ADC/DAC gain */ 375 if (adc_vol_flag) 376 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 377 else 378 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 379 gain_l_val &= 0xffff; 380 } 381 382 /* R Channel */ 383 gain_r_val = ucontrol->value.integer.value[1]; 384 if (gain_r_val > mc->max) 385 gain_r_val = mc->max; 386 387 if (mc->shift == 8) /* boost gain */ 388 gain_r_val = gain_r_val * tendB; 389 else { 390 /* ADC/DAC gain */ 391 if (adc_vol_flag) 392 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 393 else 394 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 395 gain_r_val &= 0xffff; 396 } 397 398 if (lvalue != gain_l_val || rvalue != gain_r_val) 399 changed = 1; 400 else 401 return 0; 402 403 /* Lch*/ 404 regmap_write(rt722->mbq_regmap, mc->reg, gain_l_val); 405 406 /* Rch */ 407 regmap_write(rt722->mbq_regmap, mc->rreg, gain_r_val); 408 409 regmap_read(rt722->mbq_regmap, mc->reg, &read_l); 410 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r); 411 if (read_r == gain_r_val && read_l == gain_l_val) 412 return changed; 413 414 return -EIO; 415} 416 417static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 418 struct snd_ctl_elem_value *ucontrol) 419{ 420 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 421 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 422 struct soc_mixer_control *mc = 423 (struct soc_mixer_control *)kcontrol->private_value; 424 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 425 unsigned int adc_vol_flag = 0; 426 const unsigned int interval_offset = 0xc0; 427 const unsigned int tendB = 0xa00; 428 429 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 430 strstr(ucontrol->id.name, "FU0F Capture Volume")) 431 adc_vol_flag = 1; 432 433 regmap_read(rt722->mbq_regmap, mc->reg, &read_l); 434 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r); 435 436 if (mc->shift == 8) /* boost gain */ 437 ctl_l = read_l / tendB; 438 else { 439 if (adc_vol_flag) 440 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 441 else 442 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 443 } 444 445 if (read_l != read_r) { 446 if (mc->shift == 8) /* boost gain */ 447 ctl_r = read_r / tendB; 448 else { /* ADC/DAC gain */ 449 if (adc_vol_flag) 450 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 451 else 452 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 453 } 454 } else { 455 ctl_r = ctl_l; 456 } 457 458 ucontrol->value.integer.value[0] = ctl_l; 459 ucontrol->value.integer.value[1] = ctl_r; 460 461 return 0; 462} 463 464static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722) 465{ 466 int err, i; 467 unsigned int ch_mute; 468 469 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) { 470 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i]; 471 err = regmap_write(rt722->regmap, 472 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 473 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 474 if (err < 0) 475 return err; 476 } 477 478 return 0; 479} 480 481static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 482 struct snd_ctl_elem_value *ucontrol) 483{ 484 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 485 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 486 struct rt722_sdca_dmic_kctrl_priv *p = 487 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 488 unsigned int i; 489 490 for (i = 0; i < p->count; i++) 491 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i]; 492 493 return 0; 494} 495 496static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 497 struct snd_ctl_elem_value *ucontrol) 498{ 499 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 500 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 501 struct rt722_sdca_dmic_kctrl_priv *p = 502 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 503 int err, changed = 0, i; 504 505 for (i = 0; i < p->count; i++) { 506 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 507 changed = 1; 508 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 509 } 510 511 err = rt722_sdca_set_fu1e_capture_ctl(rt722); 512 if (err < 0) 513 return err; 514 515 return changed; 516} 517 518static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722) 519{ 520 int err; 521 unsigned int ch_l, ch_r; 522 523 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00; 524 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00; 525 526 err = regmap_write(rt722->regmap, 527 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 528 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 529 if (err < 0) 530 return err; 531 532 err = regmap_write(rt722->regmap, 533 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 534 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 535 if (err < 0) 536 return err; 537 538 return 0; 539} 540 541static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 542 struct snd_ctl_elem_value *ucontrol) 543{ 544 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 545 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 546 547 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute; 548 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute; 549 return 0; 550} 551 552static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 553 struct snd_ctl_elem_value *ucontrol) 554{ 555 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 556 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 557 int err, changed = 0; 558 559 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 560 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 561 changed = 1; 562 563 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 564 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 565 err = rt722_sdca_set_fu0f_capture_ctl(rt722); 566 if (err < 0) 567 return err; 568 569 return changed; 570} 571 572static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol, 573 struct snd_ctl_elem_info *uinfo) 574{ 575 struct rt722_sdca_dmic_kctrl_priv *p = 576 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 577 578 if (p->max == 1) 579 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 580 else 581 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 582 uinfo->count = p->count; 583 uinfo->value.integer.min = 0; 584 uinfo->value.integer.max = p->max; 585 return 0; 586} 587 588static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 589 struct snd_ctl_elem_value *ucontrol) 590{ 591 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 592 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 593 struct rt722_sdca_dmic_kctrl_priv *p = 594 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 595 unsigned int boost_step = 0x0a00; 596 unsigned int vol_max = 0x1e00; 597 unsigned int regvalue, ctl, i; 598 unsigned int adc_vol_flag = 0; 599 const unsigned int interval_offset = 0xc0; 600 601 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 602 adc_vol_flag = 1; 603 604 /* check all channels */ 605 for (i = 0; i < p->count; i++) { 606 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value); 607 608 if (!adc_vol_flag) /* boost gain */ 609 ctl = regvalue / boost_step; 610 else { /* ADC gain */ 611 if (adc_vol_flag) 612 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 613 else 614 ctl = p->max - (((0 - regvalue) & 0xffff) / interval_offset); 615 } 616 617 ucontrol->value.integer.value[i] = ctl; 618 } 619 620 return 0; 621} 622 623static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 624 struct snd_ctl_elem_value *ucontrol) 625{ 626 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 627 struct rt722_sdca_dmic_kctrl_priv *p = 628 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 629 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 630 unsigned int boost_step = 0x0a00; 631 unsigned int vol_max = 0x1e00; 632 unsigned int gain_val[4]; 633 unsigned int i, adc_vol_flag = 0, changed = 0; 634 unsigned int regvalue[4]; 635 const unsigned int interval_offset = 0xc0; 636 int err; 637 638 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 639 adc_vol_flag = 1; 640 641 /* check all channels */ 642 for (i = 0; i < p->count; i++) { 643 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value[i]); 644 645 gain_val[i] = ucontrol->value.integer.value[i]; 646 if (gain_val[i] > p->max) 647 gain_val[i] = p->max; 648 649 if (!adc_vol_flag) /* boost gain */ 650 gain_val[i] = gain_val[i] * boost_step; 651 else { /* ADC gain */ 652 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 653 gain_val[i] &= 0xffff; 654 } 655 656 if (regvalue[i] != gain_val[i]) 657 changed = 1; 658 } 659 660 if (!changed) 661 return 0; 662 663 for (i = 0; i < p->count; i++) { 664 err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]); 665 if (err < 0) 666 dev_err(&rt722->slave->dev, "%#08x can't be set\n", p->reg_base + i); 667 } 668 669 return changed; 670} 671 672#define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \ 673 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \ 674 {.reg_base = xreg_base, .count = xcount, .max = xmax, \ 675 .invert = xinvert}) 676 677#define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ 678{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 679 .info = rt722_sdca_fu_info, \ 680 .get = rt722_sdca_fu1e_capture_get, \ 681 .put = rt722_sdca_fu1e_capture_put, \ 682 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)} 683 684#define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ 685 xhandler_put, xcount, xmax, tlv_array) \ 686{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 687 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 688 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 689 .tlv.p = (tlv_array), \ 690 .info = rt722_sdca_fu_info, \ 691 .get = xhandler_get, .put = xhandler_put, \ 692 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) } 693 694static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 695static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 696static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 697 698static const struct snd_kcontrol_new rt722_sdca_controls[] = { 699 /* Headphone playback settings */ 700 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 701 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 702 RT722_SDCA_CTL_FU_VOLUME, CH_L), 703 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 704 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 705 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 706 /* Headset mic capture settings */ 707 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 708 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put), 709 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 710 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 711 RT722_SDCA_CTL_FU_VOLUME, CH_L), 712 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 713 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 714 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv), 715 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 716 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 717 RT722_SDCA_CTL_FU_CH_GAIN, CH_L), 718 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 719 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0, 720 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv), 721 /* AMP playback settings */ 722 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 723 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 724 RT722_SDCA_CTL_FU_VOLUME, CH_L), 725 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 726 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 727 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 728 /* DMIC capture settings */ 729 RT722_SDCA_FU_CTRL("FU1E Capture Switch", 730 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 731 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4), 732 RT722_SDCA_EXT_TLV("FU1E Capture Volume", 733 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 734 RT722_SDCA_CTL_FU_VOLUME, CH_01), 735 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 736 4, 0x3f, mic_vol_tlv), 737 RT722_SDCA_EXT_TLV("FU15 Boost Volume", 738 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, 739 RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 740 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 741 4, 3, boost_vol_tlv), 742}; 743 744static int rt722_sdca_adc_mux_get(struct snd_kcontrol *kcontrol, 745 struct snd_ctl_elem_value *ucontrol) 746{ 747 struct snd_soc_component *component = 748 snd_soc_dapm_kcontrol_component(kcontrol); 749 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 750 unsigned int val = 0, mask_sft; 751 752 if (strstr(ucontrol->id.name, "ADC 22 Mux")) 753 mask_sft = 12; 754 else if (strstr(ucontrol->id.name, "ADC 24 Mux")) 755 mask_sft = 4; 756 else if (strstr(ucontrol->id.name, "ADC 25 Mux")) 757 mask_sft = 0; 758 else 759 return -EINVAL; 760 761 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL, 762 RT722_HDA_LEGACY_MUX_CTL0, &val); 763 764 ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7; 765 766 return 0; 767} 768 769static int rt722_sdca_adc_mux_put(struct snd_kcontrol *kcontrol, 770 struct snd_ctl_elem_value *ucontrol) 771{ 772 struct snd_soc_component *component = 773 snd_soc_dapm_kcontrol_component(kcontrol); 774 struct snd_soc_dapm_context *dapm = 775 snd_soc_dapm_kcontrol_dapm(kcontrol); 776 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 777 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 778 unsigned int *item = ucontrol->value.enumerated.item; 779 unsigned int val, val2 = 0, change, mask_sft; 780 781 if (item[0] >= e->items) 782 return -EINVAL; 783 784 if (strstr(ucontrol->id.name, "ADC 22 Mux")) 785 mask_sft = 12; 786 else if (strstr(ucontrol->id.name, "ADC 24 Mux")) 787 mask_sft = 4; 788 else if (strstr(ucontrol->id.name, "ADC 25 Mux")) 789 mask_sft = 0; 790 else 791 return -EINVAL; 792 793 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 794 795 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL, 796 RT722_HDA_LEGACY_MUX_CTL0, &val2); 797 val2 = (0x7 << mask_sft) & val2; 798 799 if (val == val2) 800 change = 0; 801 else 802 change = 1; 803 804 if (change) 805 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 806 RT722_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft, 807 val << mask_sft); 808 809 snd_soc_dapm_mux_update_power(dapm, kcontrol, 810 item[0], e, NULL); 811 812 return change; 813} 814 815static const char * const adc22_mux_text[] = { 816 "MIC2", 817 "LINE1", 818 "LINE2", 819}; 820 821static const char * const adc07_10_mux_text[] = { 822 "DMIC1", 823 "DMIC2", 824}; 825 826static SOC_ENUM_SINGLE_DECL( 827 rt722_adc22_enum, SND_SOC_NOPM, 0, adc22_mux_text); 828 829static SOC_ENUM_SINGLE_DECL( 830 rt722_adc24_enum, SND_SOC_NOPM, 0, adc07_10_mux_text); 831 832static SOC_ENUM_SINGLE_DECL( 833 rt722_adc25_enum, SND_SOC_NOPM, 0, adc07_10_mux_text); 834 835static const struct snd_kcontrol_new rt722_sdca_adc22_mux = 836 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt722_adc22_enum, 837 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 838 839static const struct snd_kcontrol_new rt722_sdca_adc24_mux = 840 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt722_adc24_enum, 841 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 842 843static const struct snd_kcontrol_new rt722_sdca_adc25_mux = 844 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt722_adc25_enum, 845 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 846 847static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w, 848 struct snd_kcontrol *kcontrol, int event) 849{ 850 struct snd_soc_component *component = 851 snd_soc_dapm_to_component(w->dapm); 852 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 853 unsigned char unmute = 0x0, mute = 0x1; 854 855 switch (event) { 856 case SND_SOC_DAPM_POST_PMU: 857 regmap_write(rt722->regmap, 858 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 859 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 860 regmap_write(rt722->regmap, 861 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 862 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 863 break; 864 case SND_SOC_DAPM_PRE_PMD: 865 regmap_write(rt722->regmap, 866 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 867 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 868 regmap_write(rt722->regmap, 869 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 870 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 871 break; 872 } 873 return 0; 874} 875 876static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w, 877 struct snd_kcontrol *kcontrol, int event) 878{ 879 struct snd_soc_component *component = 880 snd_soc_dapm_to_component(w->dapm); 881 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 882 unsigned char unmute = 0x0, mute = 0x1; 883 884 switch (event) { 885 case SND_SOC_DAPM_POST_PMU: 886 regmap_write(rt722->regmap, 887 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 888 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 889 regmap_write(rt722->regmap, 890 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 891 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 892 break; 893 case SND_SOC_DAPM_PRE_PMD: 894 regmap_write(rt722->regmap, 895 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 896 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 897 regmap_write(rt722->regmap, 898 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 899 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 900 break; 901 } 902 return 0; 903} 904 905static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w, 906 struct snd_kcontrol *kcontrol, int event) 907{ 908 struct snd_soc_component *component = 909 snd_soc_dapm_to_component(w->dapm); 910 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 911 912 switch (event) { 913 case SND_SOC_DAPM_POST_PMU: 914 rt722->fu1e_dapm_mute = false; 915 rt722_sdca_set_fu1e_capture_ctl(rt722); 916 break; 917 case SND_SOC_DAPM_PRE_PMD: 918 rt722->fu1e_dapm_mute = true; 919 rt722_sdca_set_fu1e_capture_ctl(rt722); 920 break; 921 } 922 return 0; 923} 924 925static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w, 926 struct snd_kcontrol *kcontrol, int event) 927{ 928 struct snd_soc_component *component = 929 snd_soc_dapm_to_component(w->dapm); 930 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 931 932 switch (event) { 933 case SND_SOC_DAPM_POST_PMU: 934 rt722->fu0f_dapm_mute = false; 935 rt722_sdca_set_fu0f_capture_ctl(rt722); 936 break; 937 case SND_SOC_DAPM_PRE_PMD: 938 rt722->fu0f_dapm_mute = true; 939 rt722_sdca_set_fu0f_capture_ctl(rt722); 940 break; 941 } 942 return 0; 943} 944 945static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 946 struct snd_kcontrol *kcontrol, int event) 947{ 948 struct snd_soc_component *component = 949 snd_soc_dapm_to_component(w->dapm); 950 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 951 unsigned char ps0 = 0x0, ps3 = 0x3; 952 953 switch (event) { 954 case SND_SOC_DAPM_POST_PMU: 955 regmap_write(rt722->regmap, 956 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 957 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 958 break; 959 case SND_SOC_DAPM_PRE_PMD: 960 regmap_write(rt722->regmap, 961 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 962 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 963 break; 964 } 965 return 0; 966} 967 968static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w, 969 struct snd_kcontrol *kcontrol, int event) 970{ 971 struct snd_soc_component *component = 972 snd_soc_dapm_to_component(w->dapm); 973 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 974 unsigned char ps0 = 0x0, ps3 = 0x3; 975 976 switch (event) { 977 case SND_SOC_DAPM_POST_PMU: 978 regmap_write(rt722->regmap, 979 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 980 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 981 break; 982 case SND_SOC_DAPM_PRE_PMD: 983 regmap_write(rt722->regmap, 984 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 985 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 986 break; 987 } 988 return 0; 989} 990 991static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w, 992 struct snd_kcontrol *kcontrol, int event) 993{ 994 struct snd_soc_component *component = 995 snd_soc_dapm_to_component(w->dapm); 996 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 997 unsigned char ps0 = 0x0, ps3 = 0x3; 998 999 switch (event) { 1000 case SND_SOC_DAPM_POST_PMU: 1001 regmap_write(rt722->regmap, 1002 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1003 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1004 break; 1005 case SND_SOC_DAPM_PRE_PMD: 1006 regmap_write(rt722->regmap, 1007 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1008 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1009 break; 1010 } 1011 return 0; 1012} 1013 1014static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w, 1015 struct snd_kcontrol *kcontrol, int event) 1016{ 1017 struct snd_soc_component *component = 1018 snd_soc_dapm_to_component(w->dapm); 1019 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1020 unsigned char ps0 = 0x0, ps3 = 0x3; 1021 1022 switch (event) { 1023 case SND_SOC_DAPM_POST_PMU: 1024 regmap_write(rt722->regmap, 1025 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1026 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1027 break; 1028 case SND_SOC_DAPM_PRE_PMD: 1029 regmap_write(rt722->regmap, 1030 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1031 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1032 break; 1033 } 1034 return 0; 1035} 1036 1037static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = { 1038 SND_SOC_DAPM_OUTPUT("HP"), 1039 SND_SOC_DAPM_OUTPUT("SPK"), 1040 SND_SOC_DAPM_INPUT("MIC2"), 1041 SND_SOC_DAPM_INPUT("LINE1"), 1042 SND_SOC_DAPM_INPUT("LINE2"), 1043 SND_SOC_DAPM_INPUT("DMIC1_2"), 1044 SND_SOC_DAPM_INPUT("DMIC3_4"), 1045 1046 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1047 rt722_sdca_pde23_event, 1048 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1049 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 1050 rt722_sdca_pde47_event, 1051 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1052 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1053 rt722_sdca_pde11_event, 1054 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1055 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0, 1056 rt722_sdca_pde12_event, 1057 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1058 1059 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 1060 rt722_sdca_fu21_event, 1061 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1062 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 1063 rt722_sdca_fu42_event, 1064 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1065 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 1066 rt722_sdca_fu36_event, 1067 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1068 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 1069 rt722_sdca_fu113_event, 1070 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1071 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 1072 &rt722_sdca_adc22_mux), 1073 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 1074 &rt722_sdca_adc24_mux), 1075 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 1076 &rt722_sdca_adc25_mux), 1077 1078 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1079 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1080 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1081 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1082}; 1083 1084static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = { 1085 {"FU 42", NULL, "DP1RX"}, 1086 {"FU 21", NULL, "DP3RX"}, 1087 1088 {"ADC 22 Mux", "MIC2", "MIC2"}, 1089 {"ADC 22 Mux", "LINE1", "LINE1"}, 1090 {"ADC 22 Mux", "LINE2", "LINE2"}, 1091 {"ADC 24 Mux", "DMIC1", "DMIC1_2"}, 1092 {"ADC 24 Mux", "DMIC2", "DMIC3_4"}, 1093 {"ADC 25 Mux", "DMIC1", "DMIC1_2"}, 1094 {"ADC 25 Mux", "DMIC2", "DMIC3_4"}, 1095 {"FU 36", NULL, "PDE 12"}, 1096 {"FU 36", NULL, "ADC 22 Mux"}, 1097 {"FU 113", NULL, "PDE 11"}, 1098 {"FU 113", NULL, "ADC 24 Mux"}, 1099 {"FU 113", NULL, "ADC 25 Mux"}, 1100 {"DP2TX", NULL, "FU 36"}, 1101 {"DP6TX", NULL, "FU 113"}, 1102 1103 {"HP", NULL, "PDE 47"}, 1104 {"HP", NULL, "FU 42"}, 1105 {"SPK", NULL, "PDE 23"}, 1106 {"SPK", NULL, "FU 21"}, 1107}; 1108 1109static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev) 1110{ 1111 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src); 1112 1113 return 0; 1114} 1115 1116static int rt722_sdca_probe(struct snd_soc_component *component) 1117{ 1118 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1119 int ret; 1120 1121 rt722_sdca_parse_dt(rt722, &rt722->slave->dev); 1122 rt722->component = component; 1123 1124 ret = pm_runtime_resume(component->dev); 1125 if (ret < 0 && ret != -EACCES) 1126 return ret; 1127 1128 return 0; 1129} 1130 1131static const struct snd_soc_component_driver soc_sdca_dev_rt722 = { 1132 .probe = rt722_sdca_probe, 1133 .controls = rt722_sdca_controls, 1134 .num_controls = ARRAY_SIZE(rt722_sdca_controls), 1135 .dapm_widgets = rt722_sdca_dapm_widgets, 1136 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets), 1137 .dapm_routes = rt722_sdca_audio_map, 1138 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map), 1139 .set_jack = rt722_sdca_set_jack_detect, 1140 .endianness = 1, 1141}; 1142 1143static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1144 int direction) 1145{ 1146 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1147 1148 return 0; 1149} 1150 1151static void rt722_sdca_shutdown(struct snd_pcm_substream *substream, 1152 struct snd_soc_dai *dai) 1153{ 1154 snd_soc_dai_set_dma_data(dai, substream, NULL); 1155} 1156 1157static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1158 struct snd_pcm_hw_params *params, 1159 struct snd_soc_dai *dai) 1160{ 1161 struct snd_soc_component *component = dai->component; 1162 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1163 struct sdw_stream_config stream_config; 1164 struct sdw_port_config port_config; 1165 enum sdw_data_direction direction; 1166 struct sdw_stream_runtime *sdw_stream; 1167 int retval, port, num_channels; 1168 unsigned int sampling_rate; 1169 1170 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1171 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1172 1173 if (!sdw_stream) 1174 return -EINVAL; 1175 1176 if (!rt722->slave) 1177 return -EINVAL; 1178 1179 /* 1180 * RT722_AIF1 with port = 1 for headphone playback 1181 * RT722_AIF1 with port = 2 for headset-mic capture 1182 * RT722_AIF2 with port = 3 for speaker playback 1183 * RT722_AIF3 with port = 6 for digital-mic capture 1184 */ 1185 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1186 direction = SDW_DATA_DIR_RX; 1187 if (dai->id == RT722_AIF1) 1188 port = 1; 1189 else if (dai->id == RT722_AIF2) 1190 port = 3; 1191 else 1192 return -EINVAL; 1193 } else { 1194 direction = SDW_DATA_DIR_TX; 1195 if (dai->id == RT722_AIF1) 1196 port = 2; 1197 else if (dai->id == RT722_AIF3) 1198 port = 6; 1199 else 1200 return -EINVAL; 1201 } 1202 stream_config.frame_rate = params_rate(params); 1203 stream_config.ch_count = params_channels(params); 1204 stream_config.bps = snd_pcm_format_width(params_format(params)); 1205 stream_config.direction = direction; 1206 1207 num_channels = params_channels(params); 1208 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1209 port_config.num = port; 1210 1211 retval = sdw_stream_add_slave(rt722->slave, &stream_config, 1212 &port_config, 1, sdw_stream); 1213 if (retval) { 1214 dev_err(dai->dev, "Unable to configure port\n"); 1215 return retval; 1216 } 1217 1218 if (params_channels(params) > 16) { 1219 dev_err(component->dev, "Unsupported channels %d\n", 1220 params_channels(params)); 1221 return -EINVAL; 1222 } 1223 1224 /* sampling rate configuration */ 1225 switch (params_rate(params)) { 1226 case 44100: 1227 sampling_rate = RT722_SDCA_RATE_44100HZ; 1228 break; 1229 case 48000: 1230 sampling_rate = RT722_SDCA_RATE_48000HZ; 1231 break; 1232 case 96000: 1233 sampling_rate = RT722_SDCA_RATE_96000HZ; 1234 break; 1235 case 192000: 1236 sampling_rate = RT722_SDCA_RATE_192000HZ; 1237 break; 1238 default: 1239 dev_err(component->dev, "Rate %d is not supported\n", 1240 params_rate(params)); 1241 return -EINVAL; 1242 } 1243 1244 /* set sampling frequency */ 1245 if (dai->id == RT722_AIF1) { 1246 regmap_write(rt722->regmap, 1247 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 1248 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1249 regmap_write(rt722->regmap, 1250 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 1251 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1252 } 1253 1254 if (dai->id == RT722_AIF2) 1255 regmap_write(rt722->regmap, 1256 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 1257 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1258 1259 if (dai->id == RT722_AIF3) 1260 regmap_write(rt722->regmap, 1261 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 1262 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1263 1264 return 0; 1265} 1266 1267static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1268 struct snd_soc_dai *dai) 1269{ 1270 struct snd_soc_component *component = dai->component; 1271 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1272 struct sdw_stream_runtime *sdw_stream = 1273 snd_soc_dai_get_dma_data(dai, substream); 1274 1275 if (!rt722->slave) 1276 return -EINVAL; 1277 1278 sdw_stream_remove_slave(rt722->slave, sdw_stream); 1279 return 0; 1280} 1281 1282#define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1283 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1284#define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1285 SNDRV_PCM_FMTBIT_S24_LE) 1286 1287static const struct snd_soc_dai_ops rt722_sdca_ops = { 1288 .hw_params = rt722_sdca_pcm_hw_params, 1289 .hw_free = rt722_sdca_pcm_hw_free, 1290 .set_stream = rt722_sdca_set_sdw_stream, 1291 .shutdown = rt722_sdca_shutdown, 1292}; 1293 1294static struct snd_soc_dai_driver rt722_sdca_dai[] = { 1295 { 1296 .name = "rt722-sdca-aif1", 1297 .id = RT722_AIF1, 1298 .playback = { 1299 .stream_name = "DP1 Headphone Playback", 1300 .channels_min = 1, 1301 .channels_max = 2, 1302 .rates = RT722_STEREO_RATES, 1303 .formats = RT722_FORMATS, 1304 }, 1305 .capture = { 1306 .stream_name = "DP2 Headset Capture", 1307 .channels_min = 1, 1308 .channels_max = 2, 1309 .rates = RT722_STEREO_RATES, 1310 .formats = RT722_FORMATS, 1311 }, 1312 .ops = &rt722_sdca_ops, 1313 }, 1314 { 1315 .name = "rt722-sdca-aif2", 1316 .id = RT722_AIF2, 1317 .playback = { 1318 .stream_name = "DP3 Speaker Playback", 1319 .channels_min = 1, 1320 .channels_max = 2, 1321 .rates = RT722_STEREO_RATES, 1322 .formats = RT722_FORMATS, 1323 }, 1324 .ops = &rt722_sdca_ops, 1325 }, 1326 { 1327 .name = "rt722-sdca-aif3", 1328 .id = RT722_AIF3, 1329 .capture = { 1330 .stream_name = "DP6 DMic Capture", 1331 .channels_min = 1, 1332 .channels_max = 2, 1333 .rates = RT722_STEREO_RATES, 1334 .formats = RT722_FORMATS, 1335 }, 1336 .ops = &rt722_sdca_ops, 1337 } 1338}; 1339 1340int rt722_sdca_init(struct device *dev, struct regmap *regmap, 1341 struct regmap *mbq_regmap, struct sdw_slave *slave) 1342{ 1343 struct rt722_sdca_priv *rt722; 1344 1345 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL); 1346 if (!rt722) 1347 return -ENOMEM; 1348 1349 dev_set_drvdata(dev, rt722); 1350 rt722->slave = slave; 1351 rt722->regmap = regmap; 1352 rt722->mbq_regmap = mbq_regmap; 1353 1354 mutex_init(&rt722->calibrate_mutex); 1355 mutex_init(&rt722->disable_irq_lock); 1356 1357 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler); 1358 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler); 1359 1360 /* 1361 * Mark hw_init to false 1362 * HW init will be performed when device reports present 1363 */ 1364 rt722->hw_init = false; 1365 rt722->first_hw_init = false; 1366 rt722->fu1e_dapm_mute = true; 1367 rt722->fu0f_dapm_mute = true; 1368 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true; 1369 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] = 1370 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true; 1371 1372 return devm_snd_soc_register_component(dev, 1373 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai)); 1374} 1375 1376static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1377{ 1378 /* Set AD07 power entity floating control */ 1379 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1380 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1381 /* Set AD10 power entity floating control */ 1382 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1383 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1384 /* Set DMIC1/DMIC2 power entity floating control */ 1385 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1386 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1387 /* Set DMIC2 IT entity floating control */ 1388 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1389 RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1390 /* Set AD10 FU entity floating control */ 1391 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1392 RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1393 /* Set DMIC2 FU entity floating control */ 1394 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1395 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1396 /* Set AD10 FU channel floating control */ 1397 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1398 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1399 /* Set DMIC2 FU channel floating control */ 1400 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1401 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1402 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1403 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1404 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1405 /* Enable vf707_r12_05/vf707_r13_05 */ 1406 regmap_write(rt722->regmap, 1407 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1408 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1409 /* Fine tune PDE2A latency */ 1410 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1411} 1412 1413static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1414{ 1415 /* Set DVQ=01 */ 1416 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1417 0xc215); 1418 /* Reset dc_cal_top */ 1419 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1420 0x702c); 1421 /* W1C Trigger Calibration */ 1422 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1423 0xf02d); 1424 /* Set DAC02/ClassD power entity floating control */ 1425 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1426 0x2323); 1427 /* Set EAPD high */ 1428 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1429 0x0002); 1430 /* Enable vf707_r14 */ 1431 regmap_write(rt722->regmap, 1432 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1433 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1434} 1435 1436static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1437{ 1438 int loop_check, chk_cnt = 100, ret; 1439 unsigned int calib_status = 0; 1440 1441 /* Read eFuse */ 1442 rt722_sdca_index_write(rt722, RT722_VENDOR_SPK_EFUSE, RT722_DC_CALIB_CTRL, 1443 0x4808); 1444 /* Button A, B, C, D bypass mode */ 1445 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1446 0xcf00); 1447 /* HID1 slot enable */ 1448 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1449 0x000f); 1450 /* Report ID for HID1 */ 1451 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1452 0x1100); 1453 /* OSC/OOC for slot 2, 3 */ 1454 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1455 0x0c12); 1456 /* Set JD de-bounce clock control */ 1457 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1458 0x7002); 1459 /* Set DVQ=01 */ 1460 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1461 0xc215); 1462 /* FSM switch to calibration manual mode */ 1463 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1464 0x4100); 1465 /* W1C Trigger DC calibration (HP) */ 1466 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1467 0x008d); 1468 /* check HP calibration FSM status */ 1469 for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1470 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1471 RT722_DAC_DC_CALI_CTL3, &calib_status); 1472 if (ret < 0 || loop_check == chk_cnt) 1473 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1474 if ((calib_status & 0x0040) == 0x0) 1475 break; 1476 } 1477 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1478 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1479 0x0010); 1480 /* Set ADC09 power entity floating control */ 1481 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1482 0x2a12); 1483 /* Set MIC2 and LINE1 power entity floating control */ 1484 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1485 0x3429); 1486 /* Set ET41h and LINE2 power entity floating control */ 1487 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1488 0x4112); 1489 /* Set DAC03 and HP power entity floating control */ 1490 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1491 0x4040); 1492 /* Fine tune PDE40 latency */ 1493 regmap_write(rt722->regmap, 0x2f58, 0x07); 1494} 1495 1496int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1497{ 1498 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 1499 1500 rt722->disable_irq = false; 1501 1502 if (rt722->hw_init) 1503 return 0; 1504 1505 if (rt722->first_hw_init) { 1506 regcache_cache_only(rt722->regmap, false); 1507 regcache_cache_bypass(rt722->regmap, true); 1508 regcache_cache_only(rt722->mbq_regmap, false); 1509 regcache_cache_bypass(rt722->mbq_regmap, true); 1510 } else { 1511 /* 1512 * PM runtime is only enabled when a Slave reports as Attached 1513 */ 1514 1515 /* set autosuspend parameters */ 1516 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1517 pm_runtime_use_autosuspend(&slave->dev); 1518 1519 /* update count of parent 'active' children */ 1520 pm_runtime_set_active(&slave->dev); 1521 1522 /* make sure the device does not suspend immediately */ 1523 pm_runtime_mark_last_busy(&slave->dev); 1524 1525 pm_runtime_enable(&slave->dev); 1526 } 1527 1528 pm_runtime_get_noresume(&slave->dev); 1529 1530 rt722_sdca_dmic_preset(rt722); 1531 rt722_sdca_amp_preset(rt722); 1532 rt722_sdca_jack_preset(rt722); 1533 1534 if (rt722->first_hw_init) { 1535 regcache_cache_bypass(rt722->regmap, false); 1536 regcache_mark_dirty(rt722->regmap); 1537 regcache_cache_bypass(rt722->mbq_regmap, false); 1538 regcache_mark_dirty(rt722->mbq_regmap); 1539 } else 1540 rt722->first_hw_init = true; 1541 1542 /* Mark Slave initialization complete */ 1543 rt722->hw_init = true; 1544 1545 pm_runtime_mark_last_busy(&slave->dev); 1546 pm_runtime_put_autosuspend(&slave->dev); 1547 1548 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1549 return 0; 1550} 1551 1552MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 1553MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1554MODULE_LICENSE("GPL"); 1555