1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * max98927.c -- MAX98927 ALSA Soc Audio driver 4 * 5 * Copyright (C) 2016-2017 Maxim Integrated Products 6 * Author: Ryan Lee <ryans.lee@maximintegrated.com> 7 */ 8 9#include <linux/acpi.h> 10#include <linux/i2c.h> 11#include <linux/module.h> 12#include <linux/regmap.h> 13#include <linux/slab.h> 14#include <linux/cdev.h> 15#include <sound/pcm.h> 16#include <sound/pcm_params.h> 17#include <sound/soc.h> 18#include <linux/gpio.h> 19#include <linux/gpio/consumer.h> 20#include <linux/of_gpio.h> 21#include <sound/tlv.h> 22#include "max98927.h" 23 24static struct reg_default max98927_reg[] = { 25 {MAX98927_R0001_INT_RAW1, 0x00}, 26 {MAX98927_R0002_INT_RAW2, 0x00}, 27 {MAX98927_R0003_INT_RAW3, 0x00}, 28 {MAX98927_R0004_INT_STATE1, 0x00}, 29 {MAX98927_R0005_INT_STATE2, 0x00}, 30 {MAX98927_R0006_INT_STATE3, 0x00}, 31 {MAX98927_R0007_INT_FLAG1, 0x00}, 32 {MAX98927_R0008_INT_FLAG2, 0x00}, 33 {MAX98927_R0009_INT_FLAG3, 0x00}, 34 {MAX98927_R000A_INT_EN1, 0x00}, 35 {MAX98927_R000B_INT_EN2, 0x00}, 36 {MAX98927_R000C_INT_EN3, 0x00}, 37 {MAX98927_R000D_INT_FLAG_CLR1, 0x00}, 38 {MAX98927_R000E_INT_FLAG_CLR2, 0x00}, 39 {MAX98927_R000F_INT_FLAG_CLR3, 0x00}, 40 {MAX98927_R0010_IRQ_CTRL, 0x00}, 41 {MAX98927_R0011_CLK_MON, 0x00}, 42 {MAX98927_R0012_WDOG_CTRL, 0x00}, 43 {MAX98927_R0013_WDOG_RST, 0x00}, 44 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75}, 45 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c}, 46 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08}, 47 {MAX98927_R0017_PIN_CFG, 0x55}, 48 {MAX98927_R0018_PCM_RX_EN_A, 0x00}, 49 {MAX98927_R0019_PCM_RX_EN_B, 0x00}, 50 {MAX98927_R001A_PCM_TX_EN_A, 0x00}, 51 {MAX98927_R001B_PCM_TX_EN_B, 0x00}, 52 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00}, 53 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00}, 54 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00}, 55 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00}, 56 {MAX98927_R0020_PCM_MODE_CFG, 0x40}, 57 {MAX98927_R0021_PCM_MASTER_MODE, 0x00}, 58 {MAX98927_R0022_PCM_CLK_SETUP, 0x22}, 59 {MAX98927_R0023_PCM_SR_SETUP1, 0x00}, 60 {MAX98927_R0024_PCM_SR_SETUP2, 0x00}, 61 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00}, 62 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00}, 63 {MAX98927_R0027_ICC_RX_EN_A, 0x00}, 64 {MAX98927_R0028_ICC_RX_EN_B, 0x00}, 65 {MAX98927_R002B_ICC_TX_EN_A, 0x00}, 66 {MAX98927_R002C_ICC_TX_EN_B, 0x00}, 67 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00}, 68 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00}, 69 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00}, 70 {MAX98927_R0031_ICC_LNK_EN, 0x00}, 71 {MAX98927_R0032_PDM_TX_EN, 0x00}, 72 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00}, 73 {MAX98927_R0034_PDM_TX_CTRL, 0x00}, 74 {MAX98927_R0035_PDM_RX_CTRL, 0x00}, 75 {MAX98927_R0036_AMP_VOL_CTRL, 0x00}, 76 {MAX98927_R0037_AMP_DSP_CFG, 0x02}, 77 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00}, 78 {MAX98927_R0039_DRE_CTRL, 0x01}, 79 {MAX98927_R003A_AMP_EN, 0x00}, 80 {MAX98927_R003B_SPK_SRC_SEL, 0x00}, 81 {MAX98927_R003C_SPK_GAIN, 0x00}, 82 {MAX98927_R003D_SSM_CFG, 0x04}, 83 {MAX98927_R003E_MEAS_EN, 0x00}, 84 {MAX98927_R003F_MEAS_DSP_CFG, 0x04}, 85 {MAX98927_R0040_BOOST_CTRL0, 0x00}, 86 {MAX98927_R0041_BOOST_CTRL3, 0x00}, 87 {MAX98927_R0042_BOOST_CTRL1, 0x00}, 88 {MAX98927_R0043_MEAS_ADC_CFG, 0x00}, 89 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01}, 90 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00}, 91 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00}, 92 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00}, 93 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00}, 94 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00}, 95 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00}, 96 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00}, 97 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00}, 98 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00}, 99 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00}, 100 {MAX98927_R0051_BROWNOUT_STATUS, 0x00}, 101 {MAX98927_R0052_BROWNOUT_EN, 0x00}, 102 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00}, 103 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00}, 104 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00}, 105 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00}, 106 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00}, 107 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00}, 108 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00}, 109 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00}, 110 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00}, 111 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00}, 112 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00}, 113 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00}, 114 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00}, 115 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00}, 116 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00}, 117 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00}, 118 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00}, 119 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00}, 120 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00}, 121 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00}, 122 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00}, 123 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00}, 124 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00}, 125 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00}, 126 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00}, 127 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00}, 128 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00}, 129 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00}, 130 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00}, 131 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00}, 132 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00}, 133 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00}, 134 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00}, 135 {MAX98927_R00FF_GLOBAL_SHDN, 0x00}, 136 {MAX98927_R0100_SOFT_RESET, 0x00}, 137 {MAX98927_R01FF_REV_ID, 0x40}, 138}; 139 140static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 141{ 142 struct snd_soc_component *component = codec_dai->component; 143 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 144 unsigned int mode = 0; 145 unsigned int format = 0; 146 bool use_pdm = false; 147 unsigned int invert = 0; 148 149 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 150 151 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 152 case SND_SOC_DAIFMT_CBC_CFC: 153 max98927->provider = false; 154 mode = MAX98927_PCM_MASTER_MODE_SLAVE; 155 break; 156 case SND_SOC_DAIFMT_CBP_CFP: 157 max98927->provider = true; 158 mode = MAX98927_PCM_MASTER_MODE_MASTER; 159 break; 160 default: 161 dev_err(component->dev, "DAI clock mode unsupported\n"); 162 return -EINVAL; 163 } 164 165 regmap_update_bits(max98927->regmap, MAX98927_R0021_PCM_MASTER_MODE, 166 MAX98927_PCM_MASTER_MODE_MASK, mode); 167 168 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 169 case SND_SOC_DAIFMT_NB_NF: 170 break; 171 case SND_SOC_DAIFMT_IB_NF: 172 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE; 173 break; 174 default: 175 dev_err(component->dev, "DAI invert mode unsupported\n"); 176 return -EINVAL; 177 } 178 179 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG, 180 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE, invert); 181 182 /* interface format */ 183 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 184 case SND_SOC_DAIFMT_I2S: 185 format = MAX98927_PCM_FORMAT_I2S; 186 break; 187 case SND_SOC_DAIFMT_LEFT_J: 188 format = MAX98927_PCM_FORMAT_LJ; 189 break; 190 case SND_SOC_DAIFMT_DSP_A: 191 format = MAX98927_PCM_FORMAT_TDM_MODE1; 192 break; 193 case SND_SOC_DAIFMT_DSP_B: 194 format = MAX98927_PCM_FORMAT_TDM_MODE0; 195 break; 196 case SND_SOC_DAIFMT_PDM: 197 use_pdm = true; 198 break; 199 default: 200 return -EINVAL; 201 } 202 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 203 204 if (!use_pdm) { 205 /* pcm channel configuration */ 206 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A, 207 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 208 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN); 209 210 regmap_update_bits(max98927->regmap, 211 MAX98927_R0020_PCM_MODE_CFG, 212 MAX98927_PCM_MODE_CFG_FORMAT_MASK, 213 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT); 214 215 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL, 216 MAX98927_SPK_SRC_MASK, 0); 217 218 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL, 219 MAX98927_PDM_RX_EN_MASK, 0); 220 } else { 221 /* pdm channel configuration */ 222 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL, 223 MAX98927_PDM_RX_EN_MASK, 1); 224 225 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL, 226 MAX98927_SPK_SRC_MASK, 3); 227 228 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A, 229 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 230 0); 231 } 232 return 0; 233} 234 235/* codec MCLK rate in master mode */ 236static const int rate_table[] = { 237 5644800, 6000000, 6144000, 6500000, 238 9600000, 11289600, 12000000, 12288000, 239 13000000, 19200000, 240}; 241 242/* BCLKs per LRCLK */ 243static const int bclk_sel_table[] = { 244 32, 48, 64, 96, 128, 192, 256, 384, 512, 245}; 246 247static int max98927_get_bclk_sel(int bclk) 248{ 249 int i; 250 /* match BCLKs per LRCLK */ 251 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 252 if (bclk_sel_table[i] == bclk) 253 return i + 2; 254 } 255 return 0; 256} 257static int max98927_set_clock(struct max98927_priv *max98927, 258 struct snd_pcm_hw_params *params) 259{ 260 struct snd_soc_component *component = max98927->component; 261 /* BCLK/LRCLK ratio calculation */ 262 int blr_clk_ratio = params_channels(params) * max98927->ch_size; 263 int value; 264 265 if (max98927->provider) { 266 int i; 267 /* match rate to closest value */ 268 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 269 if (rate_table[i] >= max98927->sysclk) 270 break; 271 } 272 if (i == ARRAY_SIZE(rate_table)) { 273 dev_err(component->dev, "failed to find proper clock rate.\n"); 274 return -EINVAL; 275 } 276 regmap_update_bits(max98927->regmap, 277 MAX98927_R0021_PCM_MASTER_MODE, 278 MAX98927_PCM_MASTER_MODE_MCLK_MASK, 279 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT); 280 } 281 282 if (!max98927->tdm_mode) { 283 /* BCLK configuration */ 284 value = max98927_get_bclk_sel(blr_clk_ratio); 285 if (!value) { 286 dev_err(component->dev, "format unsupported %d\n", 287 params_format(params)); 288 return -EINVAL; 289 } 290 291 regmap_update_bits(max98927->regmap, 292 MAX98927_R0022_PCM_CLK_SETUP, 293 MAX98927_PCM_CLK_SETUP_BSEL_MASK, value); 294 } 295 return 0; 296} 297 298static int max98927_dai_hw_params(struct snd_pcm_substream *substream, 299 struct snd_pcm_hw_params *params, 300 struct snd_soc_dai *dai) 301{ 302 struct snd_soc_component *component = dai->component; 303 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 304 unsigned int sampling_rate = 0; 305 unsigned int chan_sz = 0; 306 307 /* pcm mode configuration */ 308 switch (snd_pcm_format_width(params_format(params))) { 309 case 16: 310 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16; 311 break; 312 case 24: 313 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24; 314 break; 315 case 32: 316 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32; 317 break; 318 default: 319 dev_err(component->dev, "format unsupported %d\n", 320 params_format(params)); 321 goto err; 322 } 323 324 max98927->ch_size = snd_pcm_format_width(params_format(params)); 325 326 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG, 327 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 328 329 dev_dbg(component->dev, "format supported %d", 330 params_format(params)); 331 332 /* sampling rate configuration */ 333 switch (params_rate(params)) { 334 case 8000: 335 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000; 336 break; 337 case 11025: 338 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025; 339 break; 340 case 12000: 341 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000; 342 break; 343 case 16000: 344 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000; 345 break; 346 case 22050: 347 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050; 348 break; 349 case 24000: 350 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000; 351 break; 352 case 32000: 353 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000; 354 break; 355 case 44100: 356 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100; 357 break; 358 case 48000: 359 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000; 360 break; 361 default: 362 dev_err(component->dev, "rate %d not supported\n", 363 params_rate(params)); 364 goto err; 365 } 366 /* set DAI_SR to correct LRCLK frequency */ 367 regmap_update_bits(max98927->regmap, MAX98927_R0023_PCM_SR_SETUP1, 368 MAX98927_PCM_SR_SET1_SR_MASK, sampling_rate); 369 regmap_update_bits(max98927->regmap, MAX98927_R0024_PCM_SR_SETUP2, 370 MAX98927_PCM_SR_SET2_SR_MASK, 371 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT); 372 373 /* set sampling rate of IV */ 374 if (max98927->interleave_mode && 375 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000) 376 regmap_update_bits(max98927->regmap, 377 MAX98927_R0024_PCM_SR_SETUP2, 378 MAX98927_PCM_SR_SET2_IVADC_SR_MASK, 379 sampling_rate - 3); 380 else 381 regmap_update_bits(max98927->regmap, 382 MAX98927_R0024_PCM_SR_SETUP2, 383 MAX98927_PCM_SR_SET2_IVADC_SR_MASK, 384 sampling_rate); 385 return max98927_set_clock(max98927, params); 386err: 387 return -EINVAL; 388} 389 390static int max98927_dai_tdm_slot(struct snd_soc_dai *dai, 391 unsigned int tx_mask, unsigned int rx_mask, 392 int slots, int slot_width) 393{ 394 struct snd_soc_component *component = dai->component; 395 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 396 int bsel = 0; 397 unsigned int chan_sz = 0; 398 399 max98927->tdm_mode = true; 400 401 /* BCLK configuration */ 402 bsel = max98927_get_bclk_sel(slots * slot_width); 403 if (bsel == 0) { 404 dev_err(component->dev, "BCLK %d not supported\n", 405 slots * slot_width); 406 return -EINVAL; 407 } 408 409 regmap_update_bits(max98927->regmap, MAX98927_R0022_PCM_CLK_SETUP, 410 MAX98927_PCM_CLK_SETUP_BSEL_MASK, bsel); 411 412 /* Channel size configuration */ 413 switch (slot_width) { 414 case 16: 415 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16; 416 break; 417 case 24: 418 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24; 419 break; 420 case 32: 421 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32; 422 break; 423 default: 424 dev_err(component->dev, "format unsupported %d\n", 425 slot_width); 426 return -EINVAL; 427 } 428 429 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG, 430 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 431 432 /* Rx slot configuration */ 433 regmap_write(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A, 434 rx_mask & 0xFF); 435 regmap_write(max98927->regmap, MAX98927_R0019_PCM_RX_EN_B, 436 (rx_mask & 0xFF00) >> 8); 437 438 /* Tx slot configuration */ 439 regmap_write(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A, 440 tx_mask & 0xFF); 441 regmap_write(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B, 442 (tx_mask & 0xFF00) >> 8); 443 444 /* Tx slot Hi-Z configuration */ 445 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 446 ~tx_mask & 0xFF); 447 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 448 (~tx_mask & 0xFF00) >> 8); 449 450 return 0; 451} 452 453#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000 454 455#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 456 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 457 458static int max98927_dai_set_sysclk(struct snd_soc_dai *dai, 459 int clk_id, unsigned int freq, int dir) 460{ 461 struct snd_soc_component *component = dai->component; 462 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 463 464 max98927->sysclk = freq; 465 return 0; 466} 467 468static const struct snd_soc_dai_ops max98927_dai_ops = { 469 .set_sysclk = max98927_dai_set_sysclk, 470 .set_fmt = max98927_dai_set_fmt, 471 .hw_params = max98927_dai_hw_params, 472 .set_tdm_slot = max98927_dai_tdm_slot, 473}; 474 475static int max98927_dac_event(struct snd_soc_dapm_widget *w, 476 struct snd_kcontrol *kcontrol, int event) 477{ 478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 479 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 480 481 switch (event) { 482 case SND_SOC_DAPM_PRE_PMU: 483 max98927->tdm_mode = false; 484 break; 485 case SND_SOC_DAPM_POST_PMU: 486 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN, 487 MAX98927_AMP_EN_MASK, 1); 488 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN, 489 MAX98927_GLOBAL_EN_MASK, 1); 490 break; 491 case SND_SOC_DAPM_POST_PMD: 492 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN, 493 MAX98927_GLOBAL_EN_MASK, 0); 494 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN, 495 MAX98927_AMP_EN_MASK, 0); 496 break; 497 default: 498 return 0; 499 } 500 return 0; 501} 502 503static const char * const max98927_switch_text[] = { 504 "Left", "Right", "LeftRight"}; 505 506static const struct soc_enum dai_sel_enum = 507 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 508 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 3, 509 max98927_switch_text); 510 511static const struct snd_kcontrol_new max98927_dai_controls = 512 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 513 514static const struct snd_kcontrol_new max98927_vi_control = 515 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0); 516 517static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = { 518 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN, 519 0, 0, max98927_dac_event, 520 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 521 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 522 &max98927_dai_controls), 523 SND_SOC_DAPM_OUTPUT("BE_OUT"), 524 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 525 MAX98927_R003E_MEAS_EN, 0, 0), 526 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 527 MAX98927_R003E_MEAS_EN, 1, 0), 528 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 529 &max98927_vi_control), 530 SND_SOC_DAPM_SIGGEN("VMON"), 531 SND_SOC_DAPM_SIGGEN("IMON"), 532}; 533 534static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0); 535static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0); 536 537static bool max98927_readable_register(struct device *dev, unsigned int reg) 538{ 539 switch (reg) { 540 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B: 541 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B: 542 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE 543 ... MAX98927_R004E_MEAS_ADC_CH2_READ: 544 case MAX98927_R0051_BROWNOUT_STATUS 545 ... MAX98927_R0055_BROWNOUT_LVL_HOLD: 546 case MAX98927_R005A_BROWNOUT_LVL1_THRESH 547 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE: 548 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 549 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ: 550 case MAX98927_R00FF_GLOBAL_SHDN: 551 case MAX98927_R0100_SOFT_RESET: 552 case MAX98927_R01FF_REV_ID: 553 return true; 554 default: 555 return false; 556 } 557}; 558 559static bool max98927_volatile_reg(struct device *dev, unsigned int reg) 560{ 561 switch (reg) { 562 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3: 563 case MAX98927_R004C_MEAS_ADC_CH0_READ: 564 case MAX98927_R004D_MEAS_ADC_CH1_READ: 565 case MAX98927_R004E_MEAS_ADC_CH2_READ: 566 case MAX98927_R0051_BROWNOUT_STATUS: 567 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ: 568 case MAX98927_R01FF_REV_ID: 569 case MAX98927_R0100_SOFT_RESET: 570 return true; 571 default: 572 return false; 573 } 574} 575 576static const char * const max98927_boost_voltage_text[] = { 577 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V", 578 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V", 579 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V", 580 "9.5V", "9.625V", "9.75V", "9.875V", "10V" 581}; 582 583static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage, 584 MAX98927_R0040_BOOST_CTRL0, 0, 585 max98927_boost_voltage_text); 586 587static const char * const max98927_current_limit_text[] = { 588 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A", 589 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A", 590 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A", 591 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A" 592}; 593 594static SOC_ENUM_SINGLE_DECL(max98927_current_limit, 595 MAX98927_R0042_BOOST_CTRL1, 1, 596 max98927_current_limit_text); 597 598static const struct snd_kcontrol_new max98927_snd_controls[] = { 599 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN, 0, 6, 0, 600 max98927_spk_tlv), 601 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL, 602 0, (1 << MAX98927_AMP_VOL_WIDTH) - 1, 0, 603 max98927_digital_tlv), 604 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN, 605 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0), 606 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG, 607 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0), 608 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL, MAX98927_DRE_EN_SHIFT, 609 1, 0), 610 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL, 611 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0), 612 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage), 613 SOC_ENUM("Current Limit", max98927_current_limit), 614}; 615 616static const struct snd_soc_dapm_route max98927_audio_map[] = { 617 /* Plabyack */ 618 {"DAI Sel Mux", "Left", "Amp Enable"}, 619 {"DAI Sel Mux", "Right", "Amp Enable"}, 620 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 621 {"BE_OUT", NULL, "DAI Sel Mux"}, 622 /* Capture */ 623 { "VI Sense", "Switch", "VMON" }, 624 { "VI Sense", "Switch", "IMON" }, 625 { "Voltage Sense", NULL, "VI Sense" }, 626 { "Current Sense", NULL, "VI Sense" }, 627}; 628 629static struct snd_soc_dai_driver max98927_dai[] = { 630 { 631 .name = "max98927-aif1", 632 .playback = { 633 .stream_name = "HiFi Playback", 634 .channels_min = 1, 635 .channels_max = 2, 636 .rates = MAX98927_RATES, 637 .formats = MAX98927_FORMATS, 638 }, 639 .capture = { 640 .stream_name = "HiFi Capture", 641 .channels_min = 1, 642 .channels_max = 2, 643 .rates = MAX98927_RATES, 644 .formats = MAX98927_FORMATS, 645 }, 646 .ops = &max98927_dai_ops, 647 } 648}; 649 650static int max98927_probe(struct snd_soc_component *component) 651{ 652 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component); 653 654 max98927->component = component; 655 656 /* Software Reset */ 657 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET, 658 MAX98927_SOFT_RESET); 659 660 /* IV default slot configuration */ 661 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0xFF); 662 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0xFF); 663 regmap_write(max98927->regmap, MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 664 0x80); 665 regmap_write(max98927->regmap, MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 666 0x1); 667 /* Set inital volume (+13dB) */ 668 regmap_write(max98927->regmap, MAX98927_R0036_AMP_VOL_CTRL, 0x38); 669 regmap_write(max98927->regmap, MAX98927_R003C_SPK_GAIN, 0x05); 670 /* Enable DC blocker */ 671 regmap_write(max98927->regmap, MAX98927_R0037_AMP_DSP_CFG, 0x03); 672 /* Enable IMON VMON DC blocker */ 673 regmap_write(max98927->regmap, MAX98927_R003F_MEAS_DSP_CFG, 0xF7); 674 /* Boost Output Voltage & Current limit */ 675 regmap_write(max98927->regmap, MAX98927_R0040_BOOST_CTRL0, 0x1C); 676 regmap_write(max98927->regmap, MAX98927_R0042_BOOST_CTRL1, 0x3E); 677 /* Measurement ADC config */ 678 regmap_write(max98927->regmap, MAX98927_R0043_MEAS_ADC_CFG, 0x04); 679 regmap_write(max98927->regmap, MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00); 680 regmap_write(max98927->regmap, MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x24); 681 /* Brownout Level */ 682 regmap_write(max98927->regmap, MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 683 0x06); 684 /* Envelope Tracking configuration */ 685 regmap_write(max98927->regmap, MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 686 0x08); 687 regmap_write(max98927->regmap, MAX98927_R0086_ENV_TRACK_CTRL, 0x01); 688 regmap_write(max98927->regmap, MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 689 0x10); 690 691 /* voltage, current slot configuration */ 692 regmap_write(max98927->regmap, MAX98927_R001E_PCM_TX_CH_SRC_A, 693 (max98927->i_l_slot << MAX98927_PCM_TX_CH_SRC_A_I_SHIFT | max98927->v_l_slot) & 0xFF); 694 695 if (max98927->v_l_slot < 8) { 696 regmap_update_bits(max98927->regmap, 697 MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 698 1 << max98927->v_l_slot, 0); 699 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A, 700 1 << max98927->v_l_slot, 701 1 << max98927->v_l_slot); 702 } else { 703 regmap_update_bits(max98927->regmap, 704 MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 705 1 << (max98927->v_l_slot - 8), 0); 706 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B, 707 1 << (max98927->v_l_slot - 8), 708 1 << (max98927->v_l_slot - 8)); 709 } 710 711 if (max98927->i_l_slot < 8) { 712 regmap_update_bits(max98927->regmap, 713 MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 714 1 << max98927->i_l_slot, 0); 715 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A, 716 1 << max98927->i_l_slot, 717 1 << max98927->i_l_slot); 718 } else { 719 regmap_update_bits(max98927->regmap, 720 MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 721 1 << (max98927->i_l_slot - 8), 0); 722 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B, 723 1 << (max98927->i_l_slot - 8), 724 1 << (max98927->i_l_slot - 8)); 725 } 726 727 /* Set interleave mode */ 728 if (max98927->interleave_mode) 729 regmap_update_bits(max98927->regmap, 730 MAX98927_R001F_PCM_TX_CH_SRC_B, 731 MAX98927_PCM_TX_CH_INTERLEAVE_MASK, 732 MAX98927_PCM_TX_CH_INTERLEAVE_MASK); 733 return 0; 734} 735 736#ifdef CONFIG_PM_SLEEP 737static int max98927_suspend(struct device *dev) 738{ 739 struct max98927_priv *max98927 = dev_get_drvdata(dev); 740 741 regcache_cache_only(max98927->regmap, true); 742 regcache_mark_dirty(max98927->regmap); 743 return 0; 744} 745static int max98927_resume(struct device *dev) 746{ 747 struct max98927_priv *max98927 = dev_get_drvdata(dev); 748 749 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET, 750 MAX98927_SOFT_RESET); 751 regcache_cache_only(max98927->regmap, false); 752 regcache_sync(max98927->regmap); 753 return 0; 754} 755#endif 756 757static const struct dev_pm_ops max98927_pm = { 758 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume) 759}; 760 761static const struct snd_soc_component_driver soc_component_dev_max98927 = { 762 .probe = max98927_probe, 763 .controls = max98927_snd_controls, 764 .num_controls = ARRAY_SIZE(max98927_snd_controls), 765 .dapm_widgets = max98927_dapm_widgets, 766 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets), 767 .dapm_routes = max98927_audio_map, 768 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map), 769 .idle_bias_on = 1, 770 .use_pmdown_time = 1, 771 .endianness = 1, 772}; 773 774static const struct regmap_config max98927_regmap = { 775 .reg_bits = 16, 776 .val_bits = 8, 777 .max_register = MAX98927_R01FF_REV_ID, 778 .reg_defaults = max98927_reg, 779 .num_reg_defaults = ARRAY_SIZE(max98927_reg), 780 .readable_reg = max98927_readable_register, 781 .volatile_reg = max98927_volatile_reg, 782 .cache_type = REGCACHE_RBTREE, 783}; 784 785static void max98927_slot_config(struct i2c_client *i2c, 786 struct max98927_priv *max98927) 787{ 788 int value; 789 struct device *dev = &i2c->dev; 790 791 if (!device_property_read_u32(dev, "vmon-slot-no", &value)) 792 max98927->v_l_slot = value & 0xF; 793 else 794 max98927->v_l_slot = 0; 795 796 if (!device_property_read_u32(dev, "imon-slot-no", &value)) 797 max98927->i_l_slot = value & 0xF; 798 else 799 max98927->i_l_slot = 1; 800} 801 802static int max98927_i2c_probe(struct i2c_client *i2c) 803{ 804 805 int ret = 0, value; 806 int reg = 0; 807 struct max98927_priv *max98927 = NULL; 808 809 max98927 = devm_kzalloc(&i2c->dev, sizeof(*max98927), GFP_KERNEL); 810 if (!max98927) { 811 ret = -ENOMEM; 812 return ret; 813 } 814 i2c_set_clientdata(i2c, max98927); 815 816 /* update interleave mode info */ 817 if (of_property_read_bool(i2c->dev.of_node, "maxim,interleave-mode")) { 818 max98927->interleave_mode = true; 819 } else { 820 if (!of_property_read_u32(i2c->dev.of_node, "interleave_mode", 821 &value)) 822 if (value > 0) 823 max98927->interleave_mode = true; 824 } 825 826 /* regmap initialization */ 827 max98927->regmap 828 = devm_regmap_init_i2c(i2c, &max98927_regmap); 829 if (IS_ERR(max98927->regmap)) { 830 ret = PTR_ERR(max98927->regmap); 831 dev_err(&i2c->dev, 832 "Failed to allocate regmap: %d\n", ret); 833 return ret; 834 } 835 836 max98927->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", 837 GPIOD_OUT_HIGH); 838 if (IS_ERR(max98927->reset_gpio)) { 839 ret = PTR_ERR(max98927->reset_gpio); 840 return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin"); 841 } 842 843 if (max98927->reset_gpio) { 844 gpiod_set_value_cansleep(max98927->reset_gpio, 0); 845 /* Wait for i2c port to be ready */ 846 usleep_range(5000, 6000); 847 } 848 849 /* Check Revision ID */ 850 ret = regmap_read(max98927->regmap, MAX98927_R01FF_REV_ID, ®); 851 if (ret < 0) { 852 dev_err(&i2c->dev, 853 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID); 854 return ret; 855 } 856 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg); 857 858 /* voltage/current slot configuration */ 859 max98927_slot_config(i2c, max98927); 860 861 /* codec registeration */ 862 ret = devm_snd_soc_register_component(&i2c->dev, 863 &soc_component_dev_max98927, 864 max98927_dai, ARRAY_SIZE(max98927_dai)); 865 if (ret < 0) 866 dev_err(&i2c->dev, "Failed to register component: %d\n", ret); 867 868 return ret; 869} 870 871static void max98927_i2c_remove(struct i2c_client *i2c) 872{ 873 struct max98927_priv *max98927 = i2c_get_clientdata(i2c); 874 875 if (max98927->reset_gpio) 876 gpiod_set_value_cansleep(max98927->reset_gpio, 1); 877} 878 879static const struct i2c_device_id max98927_i2c_id[] = { 880 { "max98927", 0}, 881 { }, 882}; 883 884MODULE_DEVICE_TABLE(i2c, max98927_i2c_id); 885 886#if defined(CONFIG_OF) 887static const struct of_device_id max98927_of_match[] = { 888 { .compatible = "maxim,max98927", }, 889 { } 890}; 891MODULE_DEVICE_TABLE(of, max98927_of_match); 892#endif 893 894#ifdef CONFIG_ACPI 895static const struct acpi_device_id max98927_acpi_match[] = { 896 { "MX98927", 0 }, 897 {}, 898}; 899MODULE_DEVICE_TABLE(acpi, max98927_acpi_match); 900#endif 901 902static struct i2c_driver max98927_i2c_driver = { 903 .driver = { 904 .name = "max98927", 905 .of_match_table = of_match_ptr(max98927_of_match), 906 .acpi_match_table = ACPI_PTR(max98927_acpi_match), 907 .pm = &max98927_pm, 908 }, 909 .probe = max98927_i2c_probe, 910 .remove = max98927_i2c_remove, 911 .id_table = max98927_i2c_id, 912}; 913 914module_i2c_driver(max98927_i2c_driver) 915 916MODULE_DESCRIPTION("ALSA SoC MAX98927 driver"); 917MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 918MODULE_LICENSE("GPL"); 919