1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12#include <linux/module.h> 13#include <linux/moduleparam.h> 14#include <linux/version.h> 15#include <linux/types.h> 16#include <linux/init.h> 17#include <linux/delay.h> 18#include <linux/gpio.h> 19#include <linux/regmap.h> 20#include <linux/slab.h> 21#include <linux/acpi.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/property.h> 25#include <linux/regulator/consumer.h> 26#include <linux/gpio/consumer.h> 27#include <linux/of_device.h> 28#include <sound/core.h> 29#include <sound/pcm.h> 30#include <sound/pcm_params.h> 31#include <sound/soc.h> 32#include <sound/soc-dapm.h> 33#include <sound/initval.h> 34#include <sound/tlv.h> 35#include <dt-bindings/sound/cs42l42.h> 36 37#include "cs42l42.h" 38#include "cirrus_legacy.h" 39 40static const char * const cs42l42_supply_names[] = { 41 "VA", 42 "VP", 43 "VCP", 44 "VD_FILT", 45 "VL", 46}; 47 48static const struct reg_default cs42l42_reg_defaults[] = { 49 { CS42L42_FRZ_CTL, 0x00 }, 50 { CS42L42_SRC_CTL, 0x10 }, 51 { CS42L42_MCLK_CTL, 0x02 }, 52 { CS42L42_SFTRAMP_RATE, 0xA4 }, 53 { CS42L42_SLOW_START_ENABLE, 0x70 }, 54 { CS42L42_I2C_DEBOUNCE, 0x88 }, 55 { CS42L42_I2C_STRETCH, 0x03 }, 56 { CS42L42_I2C_TIMEOUT, 0xB7 }, 57 { CS42L42_PWR_CTL1, 0xFF }, 58 { CS42L42_PWR_CTL2, 0x84 }, 59 { CS42L42_PWR_CTL3, 0x20 }, 60 { CS42L42_RSENSE_CTL1, 0x40 }, 61 { CS42L42_RSENSE_CTL2, 0x00 }, 62 { CS42L42_OSC_SWITCH, 0x00 }, 63 { CS42L42_RSENSE_CTL3, 0x1B }, 64 { CS42L42_TSENSE_CTL, 0x1B }, 65 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 66 { CS42L42_HSDET_CTL1, 0x77 }, 67 { CS42L42_HSDET_CTL2, 0x00 }, 68 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 69 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 70 { CS42L42_MCLK_SRC_SEL, 0x00 }, 71 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 72 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 73 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 74 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 75 { CS42L42_FSYNC_P_UPPER, 0x00 }, 76 { CS42L42_ASP_CLK_CFG, 0x00 }, 77 { CS42L42_ASP_FRM_CFG, 0x10 }, 78 { CS42L42_FS_RATE_EN, 0x00 }, 79 { CS42L42_IN_ASRC_CLK, 0x00 }, 80 { CS42L42_OUT_ASRC_CLK, 0x00 }, 81 { CS42L42_PLL_DIV_CFG1, 0x00 }, 82 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 83 { CS42L42_MIXER_INT_MASK, 0x0F }, 84 { CS42L42_SRC_INT_MASK, 0x0F }, 85 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 86 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 87 { CS42L42_CODEC_INT_MASK, 0x03 }, 88 { CS42L42_SRCPL_INT_MASK, 0x7F }, 89 { CS42L42_VPMON_INT_MASK, 0x01 }, 90 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 91 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 92 { CS42L42_PLL_CTL1, 0x00 }, 93 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 94 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 95 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 96 { CS42L42_PLL_DIV_INT, 0x40 }, 97 { CS42L42_PLL_CTL3, 0x10 }, 98 { CS42L42_PLL_CAL_RATIO, 0x80 }, 99 { CS42L42_PLL_CTL4, 0x03 }, 100 { CS42L42_LOAD_DET_EN, 0x00 }, 101 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 102 { CS42L42_WAKE_CTL, 0xC0 }, 103 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 104 { CS42L42_TIPSENSE_CTL, 0x02 }, 105 { CS42L42_MISC_DET_CTL, 0x03 }, 106 { CS42L42_MIC_DET_CTL1, 0x1F }, 107 { CS42L42_MIC_DET_CTL2, 0x2F }, 108 { CS42L42_DET_INT1_MASK, 0xE0 }, 109 { CS42L42_DET_INT2_MASK, 0xFF }, 110 { CS42L42_HS_BIAS_CTL, 0xC2 }, 111 { CS42L42_ADC_CTL, 0x00 }, 112 { CS42L42_ADC_VOLUME, 0x00 }, 113 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 114 { CS42L42_DAC_CTL1, 0x00 }, 115 { CS42L42_DAC_CTL2, 0x02 }, 116 { CS42L42_HP_CTL, 0x0D }, 117 { CS42L42_CLASSH_CTL, 0x07 }, 118 { CS42L42_MIXER_CHA_VOL, 0x3F }, 119 { CS42L42_MIXER_ADC_VOL, 0x3F }, 120 { CS42L42_MIXER_CHB_VOL, 0x3F }, 121 { CS42L42_EQ_COEF_IN0, 0x00 }, 122 { CS42L42_EQ_COEF_IN1, 0x00 }, 123 { CS42L42_EQ_COEF_IN2, 0x00 }, 124 { CS42L42_EQ_COEF_IN3, 0x00 }, 125 { CS42L42_EQ_COEF_RW, 0x00 }, 126 { CS42L42_EQ_COEF_OUT0, 0x00 }, 127 { CS42L42_EQ_COEF_OUT1, 0x00 }, 128 { CS42L42_EQ_COEF_OUT2, 0x00 }, 129 { CS42L42_EQ_COEF_OUT3, 0x00 }, 130 { CS42L42_EQ_INIT_STAT, 0x00 }, 131 { CS42L42_EQ_START_FILT, 0x00 }, 132 { CS42L42_EQ_MUTE_CTL, 0x00 }, 133 { CS42L42_SP_RX_CH_SEL, 0x04 }, 134 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 135 { CS42L42_SP_RX_FS, 0x8C }, 136 { CS42l42_SPDIF_CH_SEL, 0x0E }, 137 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 138 { CS42L42_SP_TX_FS, 0xCC }, 139 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 140 { CS42L42_SRC_SDIN_FS, 0x40 }, 141 { CS42L42_SRC_SDOUT_FS, 0x40 }, 142 { CS42L42_SPDIF_CTL1, 0x01 }, 143 { CS42L42_SPDIF_CTL2, 0x00 }, 144 { CS42L42_SPDIF_CTL3, 0x00 }, 145 { CS42L42_SPDIF_CTL4, 0x42 }, 146 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 147 { CS42L42_ASP_TX_CH_EN, 0x00 }, 148 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 149 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 150 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 151 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 152 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 153 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 154 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 155 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 156 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 157 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 158 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 159 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 160 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 161 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 162 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 163 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 164 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 165 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 167 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 168 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 171 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 173}; 174 175bool cs42l42_readable_register(struct device *dev, unsigned int reg) 176{ 177 switch (reg) { 178 case CS42L42_PAGE_REGISTER: 179 case CS42L42_DEVID_AB: 180 case CS42L42_DEVID_CD: 181 case CS42L42_DEVID_E: 182 case CS42L42_FABID: 183 case CS42L42_REVID: 184 case CS42L42_FRZ_CTL: 185 case CS42L42_SRC_CTL: 186 case CS42L42_MCLK_STATUS: 187 case CS42L42_MCLK_CTL: 188 case CS42L42_SFTRAMP_RATE: 189 case CS42L42_SLOW_START_ENABLE: 190 case CS42L42_I2C_DEBOUNCE: 191 case CS42L42_I2C_STRETCH: 192 case CS42L42_I2C_TIMEOUT: 193 case CS42L42_PWR_CTL1: 194 case CS42L42_PWR_CTL2: 195 case CS42L42_PWR_CTL3: 196 case CS42L42_RSENSE_CTL1: 197 case CS42L42_RSENSE_CTL2: 198 case CS42L42_OSC_SWITCH: 199 case CS42L42_OSC_SWITCH_STATUS: 200 case CS42L42_RSENSE_CTL3: 201 case CS42L42_TSENSE_CTL: 202 case CS42L42_TSRS_INT_DISABLE: 203 case CS42L42_TRSENSE_STATUS: 204 case CS42L42_HSDET_CTL1: 205 case CS42L42_HSDET_CTL2: 206 case CS42L42_HS_SWITCH_CTL: 207 case CS42L42_HS_DET_STATUS: 208 case CS42L42_HS_CLAMP_DISABLE: 209 case CS42L42_MCLK_SRC_SEL: 210 case CS42L42_SPDIF_CLK_CFG: 211 case CS42L42_FSYNC_PW_LOWER: 212 case CS42L42_FSYNC_PW_UPPER: 213 case CS42L42_FSYNC_P_LOWER: 214 case CS42L42_FSYNC_P_UPPER: 215 case CS42L42_ASP_CLK_CFG: 216 case CS42L42_ASP_FRM_CFG: 217 case CS42L42_FS_RATE_EN: 218 case CS42L42_IN_ASRC_CLK: 219 case CS42L42_OUT_ASRC_CLK: 220 case CS42L42_PLL_DIV_CFG1: 221 case CS42L42_ADC_OVFL_STATUS: 222 case CS42L42_MIXER_STATUS: 223 case CS42L42_SRC_STATUS: 224 case CS42L42_ASP_RX_STATUS: 225 case CS42L42_ASP_TX_STATUS: 226 case CS42L42_CODEC_STATUS: 227 case CS42L42_DET_INT_STATUS1: 228 case CS42L42_DET_INT_STATUS2: 229 case CS42L42_SRCPL_INT_STATUS: 230 case CS42L42_VPMON_STATUS: 231 case CS42L42_PLL_LOCK_STATUS: 232 case CS42L42_TSRS_PLUG_STATUS: 233 case CS42L42_ADC_OVFL_INT_MASK: 234 case CS42L42_MIXER_INT_MASK: 235 case CS42L42_SRC_INT_MASK: 236 case CS42L42_ASP_RX_INT_MASK: 237 case CS42L42_ASP_TX_INT_MASK: 238 case CS42L42_CODEC_INT_MASK: 239 case CS42L42_SRCPL_INT_MASK: 240 case CS42L42_VPMON_INT_MASK: 241 case CS42L42_PLL_LOCK_INT_MASK: 242 case CS42L42_TSRS_PLUG_INT_MASK: 243 case CS42L42_PLL_CTL1: 244 case CS42L42_PLL_DIV_FRAC0: 245 case CS42L42_PLL_DIV_FRAC1: 246 case CS42L42_PLL_DIV_FRAC2: 247 case CS42L42_PLL_DIV_INT: 248 case CS42L42_PLL_CTL3: 249 case CS42L42_PLL_CAL_RATIO: 250 case CS42L42_PLL_CTL4: 251 case CS42L42_LOAD_DET_RCSTAT: 252 case CS42L42_LOAD_DET_DONE: 253 case CS42L42_LOAD_DET_EN: 254 case CS42L42_HSBIAS_SC_AUTOCTL: 255 case CS42L42_WAKE_CTL: 256 case CS42L42_ADC_DISABLE_MUTE: 257 case CS42L42_TIPSENSE_CTL: 258 case CS42L42_MISC_DET_CTL: 259 case CS42L42_MIC_DET_CTL1: 260 case CS42L42_MIC_DET_CTL2: 261 case CS42L42_DET_STATUS1: 262 case CS42L42_DET_STATUS2: 263 case CS42L42_DET_INT1_MASK: 264 case CS42L42_DET_INT2_MASK: 265 case CS42L42_HS_BIAS_CTL: 266 case CS42L42_ADC_CTL: 267 case CS42L42_ADC_VOLUME: 268 case CS42L42_ADC_WNF_HPF_CTL: 269 case CS42L42_DAC_CTL1: 270 case CS42L42_DAC_CTL2: 271 case CS42L42_HP_CTL: 272 case CS42L42_CLASSH_CTL: 273 case CS42L42_MIXER_CHA_VOL: 274 case CS42L42_MIXER_ADC_VOL: 275 case CS42L42_MIXER_CHB_VOL: 276 case CS42L42_EQ_COEF_IN0: 277 case CS42L42_EQ_COEF_IN1: 278 case CS42L42_EQ_COEF_IN2: 279 case CS42L42_EQ_COEF_IN3: 280 case CS42L42_EQ_COEF_RW: 281 case CS42L42_EQ_COEF_OUT0: 282 case CS42L42_EQ_COEF_OUT1: 283 case CS42L42_EQ_COEF_OUT2: 284 case CS42L42_EQ_COEF_OUT3: 285 case CS42L42_EQ_INIT_STAT: 286 case CS42L42_EQ_START_FILT: 287 case CS42L42_EQ_MUTE_CTL: 288 case CS42L42_SP_RX_CH_SEL: 289 case CS42L42_SP_RX_ISOC_CTL: 290 case CS42L42_SP_RX_FS: 291 case CS42l42_SPDIF_CH_SEL: 292 case CS42L42_SP_TX_ISOC_CTL: 293 case CS42L42_SP_TX_FS: 294 case CS42L42_SPDIF_SW_CTL1: 295 case CS42L42_SRC_SDIN_FS: 296 case CS42L42_SRC_SDOUT_FS: 297 case CS42L42_SOFT_RESET_REBOOT: 298 case CS42L42_SPDIF_CTL1: 299 case CS42L42_SPDIF_CTL2: 300 case CS42L42_SPDIF_CTL3: 301 case CS42L42_SPDIF_CTL4: 302 case CS42L42_ASP_TX_SZ_EN: 303 case CS42L42_ASP_TX_CH_EN: 304 case CS42L42_ASP_TX_CH_AP_RES: 305 case CS42L42_ASP_TX_CH1_BIT_MSB: 306 case CS42L42_ASP_TX_CH1_BIT_LSB: 307 case CS42L42_ASP_TX_HIZ_DLY_CFG: 308 case CS42L42_ASP_TX_CH2_BIT_MSB: 309 case CS42L42_ASP_TX_CH2_BIT_LSB: 310 case CS42L42_ASP_RX_DAI0_EN: 311 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 312 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 313 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 314 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 315 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 316 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 317 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 318 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 319 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 320 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 321 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 322 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 323 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 324 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 325 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 326 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 327 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 328 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 329 case CS42L42_SUB_REVID: 330 return true; 331 default: 332 return false; 333 } 334} 335EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE); 336 337bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 338{ 339 switch (reg) { 340 case CS42L42_DEVID_AB: 341 case CS42L42_DEVID_CD: 342 case CS42L42_DEVID_E: 343 case CS42L42_MCLK_STATUS: 344 case CS42L42_OSC_SWITCH_STATUS: 345 case CS42L42_TRSENSE_STATUS: 346 case CS42L42_HS_DET_STATUS: 347 case CS42L42_ADC_OVFL_STATUS: 348 case CS42L42_MIXER_STATUS: 349 case CS42L42_SRC_STATUS: 350 case CS42L42_ASP_RX_STATUS: 351 case CS42L42_ASP_TX_STATUS: 352 case CS42L42_CODEC_STATUS: 353 case CS42L42_DET_INT_STATUS1: 354 case CS42L42_DET_INT_STATUS2: 355 case CS42L42_SRCPL_INT_STATUS: 356 case CS42L42_VPMON_STATUS: 357 case CS42L42_PLL_LOCK_STATUS: 358 case CS42L42_TSRS_PLUG_STATUS: 359 case CS42L42_LOAD_DET_RCSTAT: 360 case CS42L42_LOAD_DET_DONE: 361 case CS42L42_DET_STATUS1: 362 case CS42L42_DET_STATUS2: 363 case CS42L42_SOFT_RESET_REBOOT: 364 return true; 365 default: 366 return false; 367 } 368} 369EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE); 370 371const struct regmap_range_cfg cs42l42_page_range = { 372 .name = "Pages", 373 .range_min = 0, 374 .range_max = CS42L42_MAX_REGISTER, 375 .selector_reg = CS42L42_PAGE_REGISTER, 376 .selector_mask = 0xff, 377 .selector_shift = 0, 378 .window_start = 0, 379 .window_len = 256, 380}; 381EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE); 382 383const struct regmap_config cs42l42_regmap = { 384 .reg_bits = 8, 385 .val_bits = 8, 386 387 .readable_reg = cs42l42_readable_register, 388 .volatile_reg = cs42l42_volatile_register, 389 390 .ranges = &cs42l42_page_range, 391 .num_ranges = 1, 392 393 .max_register = CS42L42_MAX_REGISTER, 394 .reg_defaults = cs42l42_reg_defaults, 395 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 396 .cache_type = REGCACHE_MAPLE, 397 398 .use_single_read = true, 399 .use_single_write = true, 400}; 401EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE); 402 403static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 404static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 405 406static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408{ 409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 410 u8 val; 411 412 /* all bits of SLOW_START_EN must change together */ 413 switch (ucontrol->value.integer.value[0]) { 414 case 0: 415 val = 0; 416 break; 417 case 1: 418 val = CS42L42_SLOW_START_EN_MASK; 419 break; 420 default: 421 return -EINVAL; 422 } 423 424 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 425 CS42L42_SLOW_START_EN_MASK, val); 426} 427 428static const char * const cs42l42_hpf_freq_text[] = { 429 "1.86Hz", "120Hz", "235Hz", "466Hz" 430}; 431 432static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 433 CS42L42_ADC_HPF_CF_SHIFT, 434 cs42l42_hpf_freq_text); 435 436static const char * const cs42l42_wnf3_freq_text[] = { 437 "160Hz", "180Hz", "200Hz", "220Hz", 438 "240Hz", "260Hz", "280Hz", "300Hz" 439}; 440 441static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 442 CS42L42_ADC_WNF_CF_SHIFT, 443 cs42l42_wnf3_freq_text); 444 445static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 446 /* ADC Volume and Filter Controls */ 447 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 448 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 449 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 450 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 451 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 452 CS42L42_ADC_INV_SHIFT, true, false), 453 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 454 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 455 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 456 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 457 CS42L42_ADC_WNF_EN_SHIFT, true, false), 458 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 459 CS42L42_ADC_HPF_EN_SHIFT, true, false), 460 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 461 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 462 463 /* DAC Volume and Filter Controls */ 464 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 465 CS42L42_DACA_INV_SHIFT, true, false), 466 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 467 CS42L42_DACB_INV_SHIFT, true, false), 468 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 469 CS42L42_DAC_HPF_EN_SHIFT, true, false), 470 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 471 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 472 0x3f, 1, mixer_tlv), 473 474 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 475 CS42L42_SLOW_START_EN_SHIFT, true, false, 476 snd_soc_get_volsw, cs42l42_slow_start_put), 477}; 478 479static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 480 struct snd_kcontrol *kcontrol, int event) 481{ 482 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 483 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 484 485 switch (event) { 486 case SND_SOC_DAPM_PRE_PMU: 487 cs42l42->hp_adc_up_pending = true; 488 break; 489 case SND_SOC_DAPM_POST_PMU: 490 /* Only need one delay if HP and ADC are both powering-up */ 491 if (cs42l42->hp_adc_up_pending) { 492 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 493 CS42L42_HP_ADC_EN_TIME_US + 1000); 494 cs42l42->hp_adc_up_pending = false; 495 } 496 break; 497 default: 498 break; 499 } 500 501 return 0; 502} 503 504static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 505 /* Playback Path */ 506 SND_SOC_DAPM_OUTPUT("HP"), 507 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 508 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 509 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 510 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 511 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 512 513 /* Playback Requirements */ 514 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 515 516 /* Capture Path */ 517 SND_SOC_DAPM_INPUT("HS"), 518 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 519 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 520 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 521 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 522 523 /* Capture Requirements */ 524 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 525 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 526 527 /* Playback/Capture Requirements */ 528 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 529 530 /* Soundwire SRC power control */ 531 SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0), 532 SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0), 533}; 534 535static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 536 /* Playback Path */ 537 {"HP", NULL, "DAC"}, 538 {"DAC", NULL, "MIXER"}, 539 {"MIXER", NULL, "SDIN1"}, 540 {"MIXER", NULL, "SDIN2"}, 541 {"SDIN1", NULL, "Playback"}, 542 {"SDIN2", NULL, "Playback"}, 543 544 /* Playback Requirements */ 545 {"SDIN1", NULL, "ASP DAI0"}, 546 {"SDIN2", NULL, "ASP DAI0"}, 547 {"SDIN1", NULL, "SCLK"}, 548 {"SDIN2", NULL, "SCLK"}, 549 550 /* Capture Path */ 551 {"ADC", NULL, "HS"}, 552 { "SDOUT1", NULL, "ADC" }, 553 { "SDOUT2", NULL, "ADC" }, 554 { "Capture", NULL, "SDOUT1" }, 555 { "Capture", NULL, "SDOUT2" }, 556 557 /* Capture Requirements */ 558 { "SDOUT1", NULL, "ASP DAO0" }, 559 { "SDOUT2", NULL, "ASP DAO0" }, 560 { "SDOUT1", NULL, "SCLK" }, 561 { "SDOUT2", NULL, "SCLK" }, 562 { "SDOUT1", NULL, "ASP TX EN" }, 563 { "SDOUT2", NULL, "ASP TX EN" }, 564}; 565 566static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 567{ 568 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 569 570 /* Prevent race with interrupt handler */ 571 mutex_lock(&cs42l42->irq_lock); 572 cs42l42->jack = jk; 573 574 if (jk) { 575 switch (cs42l42->hs_type) { 576 case CS42L42_PLUG_CTIA: 577 case CS42L42_PLUG_OMTP: 578 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET); 579 break; 580 case CS42L42_PLUG_HEADPHONE: 581 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE); 582 break; 583 default: 584 break; 585 } 586 } 587 mutex_unlock(&cs42l42->irq_lock); 588 589 return 0; 590} 591 592const struct snd_soc_component_driver cs42l42_soc_component = { 593 .set_jack = cs42l42_set_jack, 594 .dapm_widgets = cs42l42_dapm_widgets, 595 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 596 .dapm_routes = cs42l42_audio_map, 597 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 598 .controls = cs42l42_snd_controls, 599 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 600 .endianness = 1, 601}; 602EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE); 603 604/* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 605static const struct reg_sequence cs42l42_to_sclk_seq[] = { 606 { 607 .reg = CS42L42_OSC_SWITCH, 608 .def = CS42L42_SCLK_PRESENT_MASK, 609 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 610 }, 611}; 612 613/* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 614static const struct reg_sequence cs42l42_to_osc_seq[] = { 615 { 616 .reg = CS42L42_OSC_SWITCH, 617 .def = 0, 618 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 619 }, 620}; 621 622struct cs42l42_pll_params { 623 u32 sclk; 624 u8 mclk_src_sel; 625 u8 sclk_prediv; 626 u8 pll_div_int; 627 u32 pll_div_frac; 628 u8 pll_mode; 629 u8 pll_divout; 630 u32 mclk_int; 631 u8 pll_cal_ratio; 632 u8 n; 633}; 634 635/* 636 * Common PLL Settings for given SCLK 637 * Table 4-5 from the Datasheet 638 */ 639static const struct cs42l42_pll_params pll_ratio_table[] = { 640 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 641 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 642 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 643 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 644 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 645 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 646 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 647 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 648 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 649 { 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 650 { 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 651 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 652 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 653 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 654 { 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}, 655 { 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 656 { 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 657 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 658 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 659 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 660 { 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 661 { 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 662 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 663 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 664 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 665}; 666 667int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk, 668 unsigned int sample_rate) 669{ 670 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 671 int i; 672 673 /* Don't reconfigure if there is an audio stream running */ 674 if (cs42l42->stream_use) { 675 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 676 return 0; 677 else 678 return -EBUSY; 679 } 680 681 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 682 /* MCLKint must be a multiple of the sample rate */ 683 if (pll_ratio_table[i].mclk_int % sample_rate) 684 continue; 685 686 if (pll_ratio_table[i].sclk == clk) { 687 cs42l42->pll_config = i; 688 689 /* Configure the internal sample rate */ 690 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 691 CS42L42_INTERNAL_FS_MASK, 692 ((pll_ratio_table[i].mclk_int != 693 12000000) && 694 (pll_ratio_table[i].mclk_int != 695 24000000)) << 696 CS42L42_INTERNAL_FS_SHIFT); 697 if (pll_ratio_table[i].mclk_src_sel == 0) { 698 /* Pass the clock straight through */ 699 snd_soc_component_update_bits(component, 700 CS42L42_PLL_CTL1, 701 CS42L42_PLL_START_MASK, 0); 702 } else { 703 /* Configure PLL per table 4-5 */ 704 snd_soc_component_update_bits(component, 705 CS42L42_PLL_DIV_CFG1, 706 CS42L42_SCLK_PREDIV_MASK, 707 pll_ratio_table[i].sclk_prediv 708 << CS42L42_SCLK_PREDIV_SHIFT); 709 snd_soc_component_update_bits(component, 710 CS42L42_PLL_DIV_INT, 711 CS42L42_PLL_DIV_INT_MASK, 712 pll_ratio_table[i].pll_div_int 713 << CS42L42_PLL_DIV_INT_SHIFT); 714 snd_soc_component_update_bits(component, 715 CS42L42_PLL_DIV_FRAC0, 716 CS42L42_PLL_DIV_FRAC_MASK, 717 CS42L42_FRAC0_VAL( 718 pll_ratio_table[i].pll_div_frac) 719 << CS42L42_PLL_DIV_FRAC_SHIFT); 720 snd_soc_component_update_bits(component, 721 CS42L42_PLL_DIV_FRAC1, 722 CS42L42_PLL_DIV_FRAC_MASK, 723 CS42L42_FRAC1_VAL( 724 pll_ratio_table[i].pll_div_frac) 725 << CS42L42_PLL_DIV_FRAC_SHIFT); 726 snd_soc_component_update_bits(component, 727 CS42L42_PLL_DIV_FRAC2, 728 CS42L42_PLL_DIV_FRAC_MASK, 729 CS42L42_FRAC2_VAL( 730 pll_ratio_table[i].pll_div_frac) 731 << CS42L42_PLL_DIV_FRAC_SHIFT); 732 snd_soc_component_update_bits(component, 733 CS42L42_PLL_CTL4, 734 CS42L42_PLL_MODE_MASK, 735 pll_ratio_table[i].pll_mode 736 << CS42L42_PLL_MODE_SHIFT); 737 snd_soc_component_update_bits(component, 738 CS42L42_PLL_CTL3, 739 CS42L42_PLL_DIVOUT_MASK, 740 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 741 << CS42L42_PLL_DIVOUT_SHIFT); 742 snd_soc_component_update_bits(component, 743 CS42L42_PLL_CAL_RATIO, 744 CS42L42_PLL_CAL_RATIO_MASK, 745 pll_ratio_table[i].pll_cal_ratio 746 << CS42L42_PLL_CAL_RATIO_SHIFT); 747 } 748 return 0; 749 } 750 } 751 752 return -EINVAL; 753} 754EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE); 755 756void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 757{ 758 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 759 unsigned int fs; 760 761 /* Don't reconfigure if there is an audio stream running */ 762 if (cs42l42->stream_use) 763 return; 764 765 /* SRC MCLK must be as close as possible to 125 * sample rate */ 766 if (sample_rate <= 48000) 767 fs = CS42L42_CLK_IASRC_SEL_6; 768 else 769 fs = CS42L42_CLK_IASRC_SEL_12; 770 771 /* Set the sample rates (96k or lower) */ 772 snd_soc_component_update_bits(component, 773 CS42L42_FS_RATE_EN, 774 CS42L42_FS_EN_MASK, 775 (CS42L42_FS_EN_IASRC_96K | 776 CS42L42_FS_EN_OASRC_96K) << 777 CS42L42_FS_EN_SHIFT); 778 779 snd_soc_component_update_bits(component, 780 CS42L42_IN_ASRC_CLK, 781 CS42L42_CLK_IASRC_SEL_MASK, 782 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 783 snd_soc_component_update_bits(component, 784 CS42L42_OUT_ASRC_CLK, 785 CS42L42_CLK_OASRC_SEL_MASK, 786 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 787} 788EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE); 789 790static int cs42l42_asp_config(struct snd_soc_component *component, 791 unsigned int sclk, unsigned int sample_rate) 792{ 793 u32 fsync = sclk / sample_rate; 794 795 /* Set up the LRCLK */ 796 if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) { 797 dev_err(component->dev, 798 "Unsupported sclk %d/sample rate %d\n", 799 sclk, 800 sample_rate); 801 return -EINVAL; 802 } 803 /* Set the LRCLK period */ 804 snd_soc_component_update_bits(component, 805 CS42L42_FSYNC_P_LOWER, 806 CS42L42_FSYNC_PERIOD_MASK, 807 CS42L42_FRAC0_VAL(fsync - 1) << 808 CS42L42_FSYNC_PERIOD_SHIFT); 809 snd_soc_component_update_bits(component, 810 CS42L42_FSYNC_P_UPPER, 811 CS42L42_FSYNC_PERIOD_MASK, 812 CS42L42_FRAC1_VAL(fsync - 1) << 813 CS42L42_FSYNC_PERIOD_SHIFT); 814 /* Set the LRCLK to 50% duty cycle */ 815 fsync = fsync / 2; 816 snd_soc_component_update_bits(component, 817 CS42L42_FSYNC_PW_LOWER, 818 CS42L42_FSYNC_PULSE_WIDTH_MASK, 819 CS42L42_FRAC0_VAL(fsync - 1) << 820 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 821 snd_soc_component_update_bits(component, 822 CS42L42_FSYNC_PW_UPPER, 823 CS42L42_FSYNC_PULSE_WIDTH_MASK, 824 CS42L42_FRAC1_VAL(fsync - 1) << 825 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 826 827 return 0; 828} 829 830static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 831{ 832 struct snd_soc_component *component = codec_dai->component; 833 u32 asp_cfg_val = 0; 834 835 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 836 case SND_SOC_DAIFMT_CBS_CFM: 837 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 838 CS42L42_ASP_MODE_SHIFT; 839 break; 840 case SND_SOC_DAIFMT_CBS_CFS: 841 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 842 CS42L42_ASP_MODE_SHIFT; 843 break; 844 default: 845 return -EINVAL; 846 } 847 848 /* interface format */ 849 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 850 case SND_SOC_DAIFMT_I2S: 851 /* 852 * 5050 mode, frame starts on falling edge of LRCLK, 853 * frame delayed by 1.0 SCLKs 854 */ 855 snd_soc_component_update_bits(component, 856 CS42L42_ASP_FRM_CFG, 857 CS42L42_ASP_STP_MASK | 858 CS42L42_ASP_5050_MASK | 859 CS42L42_ASP_FSD_MASK, 860 CS42L42_ASP_5050_MASK | 861 (CS42L42_ASP_FSD_1_0 << 862 CS42L42_ASP_FSD_SHIFT)); 863 break; 864 default: 865 return -EINVAL; 866 } 867 868 /* Bitclock/frame inversion */ 869 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 870 case SND_SOC_DAIFMT_NB_NF: 871 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 872 break; 873 case SND_SOC_DAIFMT_NB_IF: 874 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 875 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 876 break; 877 case SND_SOC_DAIFMT_IB_NF: 878 break; 879 case SND_SOC_DAIFMT_IB_IF: 880 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 881 break; 882 } 883 884 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 885 CS42L42_ASP_SCPOL_MASK | 886 CS42L42_ASP_LCPOL_MASK, 887 asp_cfg_val); 888 889 return 0; 890} 891 892static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 893{ 894 struct snd_soc_component *component = dai->component; 895 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 896 897 /* 898 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 899 * a standard I2S frame. If the machine driver sets SCLK it must be 900 * legal. 901 */ 902 if (cs42l42->sclk) 903 return 0; 904 905 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 906 return snd_pcm_hw_constraint_minmax(substream->runtime, 907 SNDRV_PCM_HW_PARAM_RATE, 908 44100, 96000); 909} 910 911static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 912 struct snd_pcm_hw_params *params, 913 struct snd_soc_dai *dai) 914{ 915 struct snd_soc_component *component = dai->component; 916 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 917 unsigned int channels = params_channels(params); 918 unsigned int width = (params_width(params) / 8) - 1; 919 unsigned int sample_rate = params_rate(params); 920 unsigned int slot_width = 0; 921 unsigned int val = 0; 922 unsigned int bclk; 923 int ret; 924 925 if (cs42l42->bclk_ratio) { 926 /* machine driver has set the BCLK/samp-rate ratio */ 927 bclk = cs42l42->bclk_ratio * params_rate(params); 928 } else if (cs42l42->sclk) { 929 /* machine driver has set the SCLK */ 930 bclk = cs42l42->sclk; 931 } else { 932 /* 933 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 934 * more than assumed (which would result in overclocking). 935 */ 936 if (params_width(params) == 24) 937 slot_width = 32; 938 939 /* I2S frame always has multiple of 2 channels */ 940 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); 941 } 942 943 switch (substream->stream) { 944 case SNDRV_PCM_STREAM_CAPTURE: 945 /* channel 2 on high LRCLK */ 946 val = CS42L42_ASP_TX_CH2_AP_MASK | 947 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 948 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 949 950 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 951 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 952 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 953 break; 954 case SNDRV_PCM_STREAM_PLAYBACK: 955 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 956 /* channel 1 on low LRCLK */ 957 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 958 CS42L42_ASP_RX_CH_AP_MASK | 959 CS42L42_ASP_RX_CH_RES_MASK, val); 960 /* Channel 2 on high LRCLK */ 961 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 962 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 963 CS42L42_ASP_RX_CH_AP_MASK | 964 CS42L42_ASP_RX_CH_RES_MASK, val); 965 966 /* Channel B comes from the last active channel */ 967 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 968 CS42L42_SP_RX_CHB_SEL_MASK, 969 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 970 971 /* Both LRCLK slots must be enabled */ 972 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 973 CS42L42_ASP_RX0_CH_EN_MASK, 974 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 975 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 976 break; 977 default: 978 break; 979 } 980 981 ret = cs42l42_pll_config(component, bclk, sample_rate); 982 if (ret) 983 return ret; 984 985 ret = cs42l42_asp_config(component, bclk, sample_rate); 986 if (ret) 987 return ret; 988 989 cs42l42_src_config(component, sample_rate); 990 991 return 0; 992} 993 994static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 995 int clk_id, unsigned int freq, int dir) 996{ 997 struct snd_soc_component *component = dai->component; 998 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 999 int i; 1000 1001 if (freq == 0) { 1002 cs42l42->sclk = 0; 1003 return 0; 1004 } 1005 1006 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 1007 if (pll_ratio_table[i].sclk == freq) { 1008 cs42l42->sclk = freq; 1009 return 0; 1010 } 1011 } 1012 1013 dev_err(component->dev, "SCLK %u not supported\n", freq); 1014 1015 return -EINVAL; 1016} 1017 1018static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai, 1019 unsigned int bclk_ratio) 1020{ 1021 struct snd_soc_component *component = dai->component; 1022 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1023 1024 cs42l42->bclk_ratio = bclk_ratio; 1025 1026 return 0; 1027} 1028 1029int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1030{ 1031 struct snd_soc_component *component = dai->component; 1032 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1033 unsigned int regval; 1034 int ret; 1035 1036 if (mute) { 1037 /* Mute the headphone */ 1038 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1039 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1040 CS42L42_HP_ANA_AMUTE_MASK | 1041 CS42L42_HP_ANA_BMUTE_MASK, 1042 CS42L42_HP_ANA_AMUTE_MASK | 1043 CS42L42_HP_ANA_BMUTE_MASK); 1044 1045 cs42l42->stream_use &= ~(1 << stream); 1046 if (!cs42l42->stream_use) { 1047 /* 1048 * Switch to the internal oscillator. 1049 * SCLK must remain running until after this clock switch. 1050 * Without a source of clock the I2C bus doesn't work. 1051 */ 1052 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 1053 ARRAY_SIZE(cs42l42_to_osc_seq)); 1054 1055 /* Must disconnect PLL before stopping it */ 1056 snd_soc_component_update_bits(component, 1057 CS42L42_MCLK_SRC_SEL, 1058 CS42L42_MCLK_SRC_SEL_MASK, 1059 0); 1060 usleep_range(100, 200); 1061 1062 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1063 CS42L42_PLL_START_MASK, 0); 1064 } 1065 } else { 1066 if (!cs42l42->stream_use) { 1067 /* SCLK must be running before codec unmute. 1068 * 1069 * PLL must not be started with ADC and HP both off 1070 * otherwise the FILT+ supply will not charge properly. 1071 * DAPM widgets power-up before stream unmute so at least 1072 * one of the "DAC" or "ADC" widgets will already have 1073 * powered-up. 1074 */ 1075 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1076 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1077 CS42L42_PLL_START_MASK, 1); 1078 1079 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1080 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1081 CS42L42_PLL_DIVOUT_TIME_US * 2); 1082 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1083 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1084 CS42L42_PLL_DIVOUT_MASK, 1085 regval << 1086 CS42L42_PLL_DIVOUT_SHIFT); 1087 } 1088 1089 ret = regmap_read_poll_timeout(cs42l42->regmap, 1090 CS42L42_PLL_LOCK_STATUS, 1091 regval, 1092 (regval & 1), 1093 CS42L42_PLL_LOCK_POLL_US, 1094 CS42L42_PLL_LOCK_TIMEOUT_US); 1095 if (ret < 0) 1096 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1097 1098 /* PLL must be running to drive glitchless switch logic */ 1099 snd_soc_component_update_bits(component, 1100 CS42L42_MCLK_SRC_SEL, 1101 CS42L42_MCLK_SRC_SEL_MASK, 1102 CS42L42_MCLK_SRC_SEL_MASK); 1103 } 1104 1105 /* Mark SCLK as present, turn off internal oscillator */ 1106 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1107 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1108 } 1109 cs42l42->stream_use |= 1 << stream; 1110 1111 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1112 /* Un-mute the headphone */ 1113 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1114 CS42L42_HP_ANA_AMUTE_MASK | 1115 CS42L42_HP_ANA_BMUTE_MASK, 1116 0); 1117 } 1118 } 1119 1120 return 0; 1121} 1122EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE); 1123 1124#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1125 SNDRV_PCM_FMTBIT_S24_LE |\ 1126 SNDRV_PCM_FMTBIT_S32_LE) 1127 1128static const struct snd_soc_dai_ops cs42l42_ops = { 1129 .startup = cs42l42_dai_startup, 1130 .hw_params = cs42l42_pcm_hw_params, 1131 .set_fmt = cs42l42_set_dai_fmt, 1132 .set_sysclk = cs42l42_set_sysclk, 1133 .set_bclk_ratio = cs42l42_set_bclk_ratio, 1134 .mute_stream = cs42l42_mute_stream, 1135}; 1136 1137struct snd_soc_dai_driver cs42l42_dai = { 1138 .name = "cs42l42", 1139 .playback = { 1140 .stream_name = "Playback", 1141 .channels_min = 1, 1142 .channels_max = 2, 1143 .rates = SNDRV_PCM_RATE_8000_96000, 1144 .formats = CS42L42_FORMATS, 1145 }, 1146 .capture = { 1147 .stream_name = "Capture", 1148 .channels_min = 1, 1149 .channels_max = 2, 1150 .rates = SNDRV_PCM_RATE_8000_96000, 1151 .formats = CS42L42_FORMATS, 1152 }, 1153 .symmetric_rate = 1, 1154 .symmetric_sample_bits = 1, 1155 .ops = &cs42l42_ops, 1156}; 1157EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE); 1158 1159static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1160{ 1161 unsigned int hs_det_status; 1162 unsigned int hs_det_comp1; 1163 unsigned int hs_det_comp2; 1164 unsigned int hs_det_sw; 1165 1166 /* Set hs detect to manual, active mode */ 1167 regmap_update_bits(cs42l42->regmap, 1168 CS42L42_HSDET_CTL2, 1169 CS42L42_HSDET_CTRL_MASK | 1170 CS42L42_HSDET_SET_MASK | 1171 CS42L42_HSBIAS_REF_MASK | 1172 CS42L42_HSDET_AUTO_TIME_MASK, 1173 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1174 (0 << CS42L42_HSDET_SET_SHIFT) | 1175 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1176 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1177 1178 /* Configure HS DET comparator reference levels. */ 1179 regmap_update_bits(cs42l42->regmap, 1180 CS42L42_HSDET_CTL1, 1181 CS42L42_HSDET_COMP1_LVL_MASK | 1182 CS42L42_HSDET_COMP2_LVL_MASK, 1183 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1184 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1185 1186 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1187 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1188 1189 msleep(100); 1190 1191 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1192 1193 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1194 CS42L42_HSDET_COMP1_OUT_SHIFT; 1195 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1196 CS42L42_HSDET_COMP2_OUT_SHIFT; 1197 1198 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1199 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1200 1201 msleep(100); 1202 1203 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1204 1205 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1206 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1207 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1208 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1209 1210 /* Use Comparator 1 with 1.25V Threshold. */ 1211 switch (hs_det_comp1) { 1212 case CS42L42_HSDET_COMP_TYPE1: 1213 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1214 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1215 break; 1216 case CS42L42_HSDET_COMP_TYPE2: 1217 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1218 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1219 break; 1220 default: 1221 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1222 switch (hs_det_comp2) { 1223 case CS42L42_HSDET_COMP_TYPE1: 1224 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1225 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1226 break; 1227 case CS42L42_HSDET_COMP_TYPE2: 1228 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1229 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1230 break; 1231 /* Detect Type 3 and Type 4 Headsets as Headphones */ 1232 default: 1233 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1234 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1235 break; 1236 } 1237 } 1238 1239 /* Set Switches */ 1240 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1241 1242 /* Set HSDET mode to Manual—Disabled */ 1243 regmap_update_bits(cs42l42->regmap, 1244 CS42L42_HSDET_CTL2, 1245 CS42L42_HSDET_CTRL_MASK | 1246 CS42L42_HSDET_SET_MASK | 1247 CS42L42_HSBIAS_REF_MASK | 1248 CS42L42_HSDET_AUTO_TIME_MASK, 1249 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1250 (0 << CS42L42_HSDET_SET_SHIFT) | 1251 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1252 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1253 1254 /* Configure HS DET comparator reference levels. */ 1255 regmap_update_bits(cs42l42->regmap, 1256 CS42L42_HSDET_CTL1, 1257 CS42L42_HSDET_COMP1_LVL_MASK | 1258 CS42L42_HSDET_COMP2_LVL_MASK, 1259 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1260 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1261} 1262 1263static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1264{ 1265 unsigned int hs_det_status; 1266 unsigned int int_status; 1267 1268 /* Read and save the hs detection result */ 1269 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1270 1271 /* Mask the auto detect interrupt */ 1272 regmap_update_bits(cs42l42->regmap, 1273 CS42L42_CODEC_INT_MASK, 1274 CS42L42_PDN_DONE_MASK | 1275 CS42L42_HSDET_AUTO_DONE_MASK, 1276 (1 << CS42L42_PDN_DONE_SHIFT) | 1277 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1278 1279 1280 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1281 CS42L42_HSDET_TYPE_SHIFT; 1282 1283 /* Set hs detect to automatic, disabled mode */ 1284 regmap_update_bits(cs42l42->regmap, 1285 CS42L42_HSDET_CTL2, 1286 CS42L42_HSDET_CTRL_MASK | 1287 CS42L42_HSDET_SET_MASK | 1288 CS42L42_HSBIAS_REF_MASK | 1289 CS42L42_HSDET_AUTO_TIME_MASK, 1290 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1291 (2 << CS42L42_HSDET_SET_SHIFT) | 1292 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1293 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1294 1295 /* Run Manual detection if auto detect has not found a headset. 1296 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1297 * to ensure that a headset mic is detected in all cases. 1298 */ 1299 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1300 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1301 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1302 cs42l42_manual_hs_type_detect(cs42l42); 1303 } 1304 1305 /* Set up button detection */ 1306 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1307 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1308 /* Set auto HS bias settings to default */ 1309 regmap_update_bits(cs42l42->regmap, 1310 CS42L42_HSBIAS_SC_AUTOCTL, 1311 CS42L42_HSBIAS_SENSE_EN_MASK | 1312 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1313 CS42L42_TIP_SENSE_EN_MASK | 1314 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1315 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1316 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1317 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1318 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1319 1320 /* Set up hs detect level sensitivity */ 1321 regmap_update_bits(cs42l42->regmap, 1322 CS42L42_MIC_DET_CTL1, 1323 CS42L42_LATCH_TO_VP_MASK | 1324 CS42L42_EVENT_STAT_SEL_MASK | 1325 CS42L42_HS_DET_LEVEL_MASK, 1326 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1327 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1328 (cs42l42->bias_thresholds[0] << 1329 CS42L42_HS_DET_LEVEL_SHIFT)); 1330 1331 /* Set auto HS bias settings to default */ 1332 regmap_update_bits(cs42l42->regmap, 1333 CS42L42_HSBIAS_SC_AUTOCTL, 1334 CS42L42_HSBIAS_SENSE_EN_MASK | 1335 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1336 CS42L42_TIP_SENSE_EN_MASK | 1337 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1338 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1339 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1340 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1341 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1342 1343 /* Turn on level detect circuitry */ 1344 regmap_update_bits(cs42l42->regmap, 1345 CS42L42_MISC_DET_CTL, 1346 CS42L42_HSBIAS_CTL_MASK | 1347 CS42L42_PDN_MIC_LVL_DET_MASK, 1348 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1349 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1350 1351 msleep(cs42l42->btn_det_init_dbnce); 1352 1353 /* Clear any button interrupts before unmasking them */ 1354 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1355 &int_status); 1356 1357 /* Unmask button detect interrupts */ 1358 regmap_update_bits(cs42l42->regmap, 1359 CS42L42_DET_INT2_MASK, 1360 CS42L42_M_DETECT_TF_MASK | 1361 CS42L42_M_DETECT_FT_MASK | 1362 CS42L42_M_HSBIAS_HIZ_MASK | 1363 CS42L42_M_SHORT_RLS_MASK | 1364 CS42L42_M_SHORT_DET_MASK, 1365 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1366 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1367 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1368 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1369 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1370 } else { 1371 /* Make sure button detect and HS bias circuits are off */ 1372 regmap_update_bits(cs42l42->regmap, 1373 CS42L42_MISC_DET_CTL, 1374 CS42L42_HSBIAS_CTL_MASK | 1375 CS42L42_PDN_MIC_LVL_DET_MASK, 1376 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1377 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1378 } 1379 1380 regmap_update_bits(cs42l42->regmap, 1381 CS42L42_DAC_CTL2, 1382 CS42L42_HPOUT_PULLDOWN_MASK | 1383 CS42L42_HPOUT_LOAD_MASK | 1384 CS42L42_HPOUT_CLAMP_MASK | 1385 CS42L42_DAC_HPF_EN_MASK | 1386 CS42L42_DAC_MON_EN_MASK, 1387 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1388 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1389 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1390 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1391 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1392 1393 /* Unmask tip sense interrupts */ 1394 regmap_update_bits(cs42l42->regmap, 1395 CS42L42_TSRS_PLUG_INT_MASK, 1396 CS42L42_TS_PLUG_MASK | 1397 CS42L42_TS_UNPLUG_MASK, 1398 (0 << CS42L42_TS_PLUG_SHIFT) | 1399 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1400} 1401 1402static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1403{ 1404 /* Mask tip sense interrupts */ 1405 regmap_update_bits(cs42l42->regmap, 1406 CS42L42_TSRS_PLUG_INT_MASK, 1407 CS42L42_TS_PLUG_MASK | 1408 CS42L42_TS_UNPLUG_MASK, 1409 (1 << CS42L42_TS_PLUG_SHIFT) | 1410 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1411 1412 /* Make sure button detect and HS bias circuits are off */ 1413 regmap_update_bits(cs42l42->regmap, 1414 CS42L42_MISC_DET_CTL, 1415 CS42L42_HSBIAS_CTL_MASK | 1416 CS42L42_PDN_MIC_LVL_DET_MASK, 1417 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1418 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1419 1420 /* Set auto HS bias settings to default */ 1421 regmap_update_bits(cs42l42->regmap, 1422 CS42L42_HSBIAS_SC_AUTOCTL, 1423 CS42L42_HSBIAS_SENSE_EN_MASK | 1424 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1425 CS42L42_TIP_SENSE_EN_MASK | 1426 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1427 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1428 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1429 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1430 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1431 1432 /* Set hs detect to manual, disabled mode */ 1433 regmap_update_bits(cs42l42->regmap, 1434 CS42L42_HSDET_CTL2, 1435 CS42L42_HSDET_CTRL_MASK | 1436 CS42L42_HSDET_SET_MASK | 1437 CS42L42_HSBIAS_REF_MASK | 1438 CS42L42_HSDET_AUTO_TIME_MASK, 1439 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1440 (2 << CS42L42_HSDET_SET_SHIFT) | 1441 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1442 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1443 1444 regmap_update_bits(cs42l42->regmap, 1445 CS42L42_DAC_CTL2, 1446 CS42L42_HPOUT_PULLDOWN_MASK | 1447 CS42L42_HPOUT_LOAD_MASK | 1448 CS42L42_HPOUT_CLAMP_MASK | 1449 CS42L42_DAC_HPF_EN_MASK | 1450 CS42L42_DAC_MON_EN_MASK, 1451 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1452 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1453 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1454 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1455 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1456 1457 /* Power up HS bias to 2.7V */ 1458 regmap_update_bits(cs42l42->regmap, 1459 CS42L42_MISC_DET_CTL, 1460 CS42L42_HSBIAS_CTL_MASK | 1461 CS42L42_PDN_MIC_LVL_DET_MASK, 1462 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1463 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1464 1465 /* Wait for HS bias to ramp up */ 1466 msleep(cs42l42->hs_bias_ramp_time); 1467 1468 /* Unmask auto detect interrupt */ 1469 regmap_update_bits(cs42l42->regmap, 1470 CS42L42_CODEC_INT_MASK, 1471 CS42L42_PDN_DONE_MASK | 1472 CS42L42_HSDET_AUTO_DONE_MASK, 1473 (1 << CS42L42_PDN_DONE_SHIFT) | 1474 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1475 1476 /* Set hs detect to automatic, enabled mode */ 1477 regmap_update_bits(cs42l42->regmap, 1478 CS42L42_HSDET_CTL2, 1479 CS42L42_HSDET_CTRL_MASK | 1480 CS42L42_HSDET_SET_MASK | 1481 CS42L42_HSBIAS_REF_MASK | 1482 CS42L42_HSDET_AUTO_TIME_MASK, 1483 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1484 (2 << CS42L42_HSDET_SET_SHIFT) | 1485 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1486 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1487} 1488 1489static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1490{ 1491 /* Mask button detect interrupts */ 1492 regmap_update_bits(cs42l42->regmap, 1493 CS42L42_DET_INT2_MASK, 1494 CS42L42_M_DETECT_TF_MASK | 1495 CS42L42_M_DETECT_FT_MASK | 1496 CS42L42_M_HSBIAS_HIZ_MASK | 1497 CS42L42_M_SHORT_RLS_MASK | 1498 CS42L42_M_SHORT_DET_MASK, 1499 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1500 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1501 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1502 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1503 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1504 1505 /* Ground HS bias */ 1506 regmap_update_bits(cs42l42->regmap, 1507 CS42L42_MISC_DET_CTL, 1508 CS42L42_HSBIAS_CTL_MASK | 1509 CS42L42_PDN_MIC_LVL_DET_MASK, 1510 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1511 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1512 1513 /* Set auto HS bias settings to default */ 1514 regmap_update_bits(cs42l42->regmap, 1515 CS42L42_HSBIAS_SC_AUTOCTL, 1516 CS42L42_HSBIAS_SENSE_EN_MASK | 1517 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1518 CS42L42_TIP_SENSE_EN_MASK | 1519 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1520 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1521 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1522 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1523 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1524 1525 /* Set hs detect to manual, disabled mode */ 1526 regmap_update_bits(cs42l42->regmap, 1527 CS42L42_HSDET_CTL2, 1528 CS42L42_HSDET_CTRL_MASK | 1529 CS42L42_HSDET_SET_MASK | 1530 CS42L42_HSBIAS_REF_MASK | 1531 CS42L42_HSDET_AUTO_TIME_MASK, 1532 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1533 (2 << CS42L42_HSDET_SET_SHIFT) | 1534 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1535 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1536} 1537 1538static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1539{ 1540 int bias_level; 1541 unsigned int detect_status; 1542 1543 /* Mask button detect interrupts */ 1544 regmap_update_bits(cs42l42->regmap, 1545 CS42L42_DET_INT2_MASK, 1546 CS42L42_M_DETECT_TF_MASK | 1547 CS42L42_M_DETECT_FT_MASK | 1548 CS42L42_M_HSBIAS_HIZ_MASK | 1549 CS42L42_M_SHORT_RLS_MASK | 1550 CS42L42_M_SHORT_DET_MASK, 1551 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1552 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1553 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1554 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1555 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1556 1557 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1558 cs42l42->btn_det_event_dbnce * 2000); 1559 1560 /* Test all 4 level detect biases */ 1561 bias_level = 1; 1562 do { 1563 /* Adjust button detect level sensitivity */ 1564 regmap_update_bits(cs42l42->regmap, 1565 CS42L42_MIC_DET_CTL1, 1566 CS42L42_LATCH_TO_VP_MASK | 1567 CS42L42_EVENT_STAT_SEL_MASK | 1568 CS42L42_HS_DET_LEVEL_MASK, 1569 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1570 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1571 (cs42l42->bias_thresholds[bias_level] << 1572 CS42L42_HS_DET_LEVEL_SHIFT)); 1573 1574 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1575 &detect_status); 1576 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1577 (++bias_level < CS42L42_NUM_BIASES)); 1578 1579 switch (bias_level) { 1580 case 1: /* Function C button press */ 1581 bias_level = SND_JACK_BTN_2; 1582 dev_dbg(cs42l42->dev, "Function C button press\n"); 1583 break; 1584 case 2: /* Function B button press */ 1585 bias_level = SND_JACK_BTN_1; 1586 dev_dbg(cs42l42->dev, "Function B button press\n"); 1587 break; 1588 case 3: /* Function D button press */ 1589 bias_level = SND_JACK_BTN_3; 1590 dev_dbg(cs42l42->dev, "Function D button press\n"); 1591 break; 1592 case 4: /* Function A button press */ 1593 bias_level = SND_JACK_BTN_0; 1594 dev_dbg(cs42l42->dev, "Function A button press\n"); 1595 break; 1596 default: 1597 bias_level = 0; 1598 break; 1599 } 1600 1601 /* Set button detect level sensitivity back to default */ 1602 regmap_update_bits(cs42l42->regmap, 1603 CS42L42_MIC_DET_CTL1, 1604 CS42L42_LATCH_TO_VP_MASK | 1605 CS42L42_EVENT_STAT_SEL_MASK | 1606 CS42L42_HS_DET_LEVEL_MASK, 1607 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1608 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1609 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1610 1611 /* Clear any button interrupts before unmasking them */ 1612 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1613 &detect_status); 1614 1615 /* Unmask button detect interrupts */ 1616 regmap_update_bits(cs42l42->regmap, 1617 CS42L42_DET_INT2_MASK, 1618 CS42L42_M_DETECT_TF_MASK | 1619 CS42L42_M_DETECT_FT_MASK | 1620 CS42L42_M_HSBIAS_HIZ_MASK | 1621 CS42L42_M_SHORT_RLS_MASK | 1622 CS42L42_M_SHORT_DET_MASK, 1623 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1624 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1625 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1626 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1627 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1628 1629 return bias_level; 1630} 1631 1632struct cs42l42_irq_params { 1633 u16 status_addr; 1634 u16 mask_addr; 1635 u8 mask; 1636}; 1637 1638static const struct cs42l42_irq_params irq_params_table[] = { 1639 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1640 CS42L42_ADC_OVFL_VAL_MASK}, 1641 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1642 CS42L42_MIXER_VAL_MASK}, 1643 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1644 CS42L42_SRC_VAL_MASK}, 1645 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1646 CS42L42_ASP_RX_VAL_MASK}, 1647 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1648 CS42L42_ASP_TX_VAL_MASK}, 1649 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1650 CS42L42_CODEC_VAL_MASK}, 1651 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1652 CS42L42_DET_INT_VAL1_MASK}, 1653 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1654 CS42L42_DET_INT_VAL2_MASK}, 1655 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1656 CS42L42_SRCPL_VAL_MASK}, 1657 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1658 CS42L42_VPMON_VAL_MASK}, 1659 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1660 CS42L42_PLL_LOCK_VAL_MASK}, 1661 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1662 CS42L42_TSRS_PLUG_VAL_MASK} 1663}; 1664 1665irqreturn_t cs42l42_irq_thread(int irq, void *data) 1666{ 1667 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1668 unsigned int stickies[12]; 1669 unsigned int masks[12]; 1670 unsigned int current_plug_status; 1671 unsigned int current_button_status; 1672 unsigned int i; 1673 1674 pm_runtime_get_sync(cs42l42->dev); 1675 mutex_lock(&cs42l42->irq_lock); 1676 if (cs42l42->suspended || !cs42l42->init_done) { 1677 mutex_unlock(&cs42l42->irq_lock); 1678 pm_runtime_put_autosuspend(cs42l42->dev); 1679 return IRQ_NONE; 1680 } 1681 1682 /* Read sticky registers to clear interurpt */ 1683 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1684 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1685 &(stickies[i])); 1686 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1687 &(masks[i])); 1688 stickies[i] = stickies[i] & (~masks[i]) & 1689 irq_params_table[i].mask; 1690 } 1691 1692 /* Read tip sense status before handling type detect */ 1693 current_plug_status = (stickies[11] & 1694 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1695 CS42L42_TS_PLUG_SHIFT; 1696 1697 /* Read button sense status */ 1698 current_button_status = stickies[7] & 1699 (CS42L42_M_DETECT_TF_MASK | 1700 CS42L42_M_DETECT_FT_MASK | 1701 CS42L42_M_HSBIAS_HIZ_MASK); 1702 1703 /* 1704 * Check auto-detect status. Don't assume a previous unplug event has 1705 * cleared the flags. If the jack is unplugged and plugged during 1706 * system suspend there won't have been an unplug event. 1707 */ 1708 if ((~masks[5]) & irq_params_table[5].mask) { 1709 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1710 cs42l42_process_hs_type_detect(cs42l42); 1711 switch (cs42l42->hs_type) { 1712 case CS42L42_PLUG_CTIA: 1713 case CS42L42_PLUG_OMTP: 1714 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1715 SND_JACK_HEADSET | 1716 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1717 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1718 break; 1719 case CS42L42_PLUG_HEADPHONE: 1720 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1721 SND_JACK_HEADSET | 1722 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1723 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1724 break; 1725 default: 1726 break; 1727 } 1728 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1729 } 1730 } 1731 1732 /* Check tip sense status */ 1733 if ((~masks[11]) & irq_params_table[11].mask) { 1734 switch (current_plug_status) { 1735 case CS42L42_TS_PLUG: 1736 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1737 cs42l42->plug_state = CS42L42_TS_PLUG; 1738 cs42l42_init_hs_type_detect(cs42l42); 1739 } 1740 break; 1741 1742 case CS42L42_TS_UNPLUG: 1743 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1744 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1745 cs42l42_cancel_hs_type_detect(cs42l42); 1746 1747 snd_soc_jack_report(cs42l42->jack, 0, 1748 SND_JACK_HEADSET | 1749 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1750 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1751 1752 dev_dbg(cs42l42->dev, "Unplug event\n"); 1753 } 1754 break; 1755 1756 default: 1757 cs42l42->plug_state = CS42L42_TS_TRANS; 1758 } 1759 } 1760 1761 /* Check button detect status */ 1762 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1763 if (!(current_button_status & 1764 CS42L42_M_HSBIAS_HIZ_MASK)) { 1765 1766 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1767 dev_dbg(cs42l42->dev, "Button released\n"); 1768 snd_soc_jack_report(cs42l42->jack, 0, 1769 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1770 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1771 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1772 snd_soc_jack_report(cs42l42->jack, 1773 cs42l42_handle_button_press(cs42l42), 1774 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1775 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1776 } 1777 } 1778 } 1779 1780 mutex_unlock(&cs42l42->irq_lock); 1781 pm_runtime_mark_last_busy(cs42l42->dev); 1782 pm_runtime_put_autosuspend(cs42l42->dev); 1783 1784 return IRQ_HANDLED; 1785} 1786EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE); 1787 1788static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1789{ 1790 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1791 CS42L42_ADC_OVFL_MASK, 1792 (1 << CS42L42_ADC_OVFL_SHIFT)); 1793 1794 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1795 CS42L42_MIX_CHB_OVFL_MASK | 1796 CS42L42_MIX_CHA_OVFL_MASK | 1797 CS42L42_EQ_OVFL_MASK | 1798 CS42L42_EQ_BIQUAD_OVFL_MASK, 1799 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1800 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1801 (1 << CS42L42_EQ_OVFL_SHIFT) | 1802 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1803 1804 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1805 CS42L42_SRC_ILK_MASK | 1806 CS42L42_SRC_OLK_MASK | 1807 CS42L42_SRC_IUNLK_MASK | 1808 CS42L42_SRC_OUNLK_MASK, 1809 (1 << CS42L42_SRC_ILK_SHIFT) | 1810 (1 << CS42L42_SRC_OLK_SHIFT) | 1811 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1812 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1813 1814 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1815 CS42L42_ASPRX_NOLRCK_MASK | 1816 CS42L42_ASPRX_EARLY_MASK | 1817 CS42L42_ASPRX_LATE_MASK | 1818 CS42L42_ASPRX_ERROR_MASK | 1819 CS42L42_ASPRX_OVLD_MASK, 1820 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1821 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1822 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1823 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1824 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1825 1826 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1827 CS42L42_ASPTX_NOLRCK_MASK | 1828 CS42L42_ASPTX_EARLY_MASK | 1829 CS42L42_ASPTX_LATE_MASK | 1830 CS42L42_ASPTX_SMERROR_MASK, 1831 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1832 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1833 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1834 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1835 1836 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1837 CS42L42_PDN_DONE_MASK | 1838 CS42L42_HSDET_AUTO_DONE_MASK, 1839 (1 << CS42L42_PDN_DONE_SHIFT) | 1840 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1841 1842 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1843 CS42L42_SRCPL_ADC_LK_MASK | 1844 CS42L42_SRCPL_DAC_LK_MASK | 1845 CS42L42_SRCPL_ADC_UNLK_MASK | 1846 CS42L42_SRCPL_DAC_UNLK_MASK, 1847 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1848 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1849 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1850 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1851 1852 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1853 CS42L42_TIP_SENSE_UNPLUG_MASK | 1854 CS42L42_TIP_SENSE_PLUG_MASK | 1855 CS42L42_HSBIAS_SENSE_MASK, 1856 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1857 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1858 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1859 1860 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1861 CS42L42_M_DETECT_TF_MASK | 1862 CS42L42_M_DETECT_FT_MASK | 1863 CS42L42_M_HSBIAS_HIZ_MASK | 1864 CS42L42_M_SHORT_RLS_MASK | 1865 CS42L42_M_SHORT_DET_MASK, 1866 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1867 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1868 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1869 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1870 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1871 1872 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1873 CS42L42_VPMON_MASK, 1874 (1 << CS42L42_VPMON_SHIFT)); 1875 1876 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1877 CS42L42_PLL_LOCK_MASK, 1878 (1 << CS42L42_PLL_LOCK_SHIFT)); 1879 1880 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1881 CS42L42_RS_PLUG_MASK | 1882 CS42L42_RS_UNPLUG_MASK | 1883 CS42L42_TS_PLUG_MASK | 1884 CS42L42_TS_UNPLUG_MASK, 1885 (1 << CS42L42_RS_PLUG_SHIFT) | 1886 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1887 (0 << CS42L42_TS_PLUG_SHIFT) | 1888 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1889} 1890 1891static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1892{ 1893 unsigned int reg; 1894 1895 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1896 1897 /* 1898 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the 1899 * FILT+ supply will not charge properly. 1900 */ 1901 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1902 CS42L42_DETECT_MODE_MASK, 0); 1903 1904 /* Latch analog controls to VP power domain */ 1905 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1906 CS42L42_LATCH_TO_VP_MASK | 1907 CS42L42_EVENT_STAT_SEL_MASK | 1908 CS42L42_HS_DET_LEVEL_MASK, 1909 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1910 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1911 (cs42l42->bias_thresholds[0] << 1912 CS42L42_HS_DET_LEVEL_SHIFT)); 1913 1914 /* Remove ground noise-suppression clamps */ 1915 regmap_update_bits(cs42l42->regmap, 1916 CS42L42_HS_CLAMP_DISABLE, 1917 CS42L42_HS_CLAMP_DISABLE_MASK, 1918 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1919 1920 /* Enable the tip sense circuit */ 1921 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1922 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1923 1924 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1925 CS42L42_TIP_SENSE_CTRL_MASK | 1926 CS42L42_TIP_SENSE_INV_MASK | 1927 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1928 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1929 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1930 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1931 1932 /* Save the initial status of the tip sense */ 1933 regmap_read(cs42l42->regmap, 1934 CS42L42_TSRS_PLUG_STATUS, 1935 ®); 1936 cs42l42->plug_state = (((char) reg) & 1937 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1938 CS42L42_TS_PLUG_SHIFT; 1939} 1940 1941static const unsigned int threshold_defaults[] = { 1942 CS42L42_HS_DET_LEVEL_15, 1943 CS42L42_HS_DET_LEVEL_8, 1944 CS42L42_HS_DET_LEVEL_4, 1945 CS42L42_HS_DET_LEVEL_1 1946}; 1947 1948static int cs42l42_handle_device_data(struct device *dev, 1949 struct cs42l42_private *cs42l42) 1950{ 1951 unsigned int val; 1952 u32 thresholds[CS42L42_NUM_BIASES]; 1953 int ret; 1954 int i; 1955 1956 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1957 if (!ret) { 1958 switch (val) { 1959 case CS42L42_TS_INV_EN: 1960 case CS42L42_TS_INV_DIS: 1961 cs42l42->ts_inv = val; 1962 break; 1963 default: 1964 dev_err(dev, 1965 "Wrong cirrus,ts-inv DT value %d\n", 1966 val); 1967 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1968 } 1969 } else { 1970 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1971 } 1972 1973 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1974 if (!ret) { 1975 switch (val) { 1976 case CS42L42_TS_DBNCE_0: 1977 case CS42L42_TS_DBNCE_125: 1978 case CS42L42_TS_DBNCE_250: 1979 case CS42L42_TS_DBNCE_500: 1980 case CS42L42_TS_DBNCE_750: 1981 case CS42L42_TS_DBNCE_1000: 1982 case CS42L42_TS_DBNCE_1250: 1983 case CS42L42_TS_DBNCE_1500: 1984 cs42l42->ts_dbnc_rise = val; 1985 break; 1986 default: 1987 dev_err(dev, 1988 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1989 val); 1990 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1991 } 1992 } else { 1993 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1994 } 1995 1996 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1997 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1998 (cs42l42->ts_dbnc_rise << 1999 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 2000 2001 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 2002 if (!ret) { 2003 switch (val) { 2004 case CS42L42_TS_DBNCE_0: 2005 case CS42L42_TS_DBNCE_125: 2006 case CS42L42_TS_DBNCE_250: 2007 case CS42L42_TS_DBNCE_500: 2008 case CS42L42_TS_DBNCE_750: 2009 case CS42L42_TS_DBNCE_1000: 2010 case CS42L42_TS_DBNCE_1250: 2011 case CS42L42_TS_DBNCE_1500: 2012 cs42l42->ts_dbnc_fall = val; 2013 break; 2014 default: 2015 dev_err(dev, 2016 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 2017 val); 2018 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2019 } 2020 } else { 2021 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2022 } 2023 2024 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 2025 CS42L42_TS_FALL_DBNCE_TIME_MASK, 2026 (cs42l42->ts_dbnc_fall << 2027 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 2028 2029 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 2030 if (!ret) { 2031 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 2032 cs42l42->btn_det_init_dbnce = val; 2033 else { 2034 dev_err(dev, 2035 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 2036 val); 2037 cs42l42->btn_det_init_dbnce = 2038 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2039 } 2040 } else { 2041 cs42l42->btn_det_init_dbnce = 2042 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2043 } 2044 2045 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 2046 if (!ret) { 2047 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 2048 cs42l42->btn_det_event_dbnce = val; 2049 else { 2050 dev_err(dev, 2051 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 2052 cs42l42->btn_det_event_dbnce = 2053 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2054 } 2055 } else { 2056 cs42l42->btn_det_event_dbnce = 2057 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2058 } 2059 2060 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 2061 thresholds, ARRAY_SIZE(thresholds)); 2062 if (!ret) { 2063 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 2064 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 2065 cs42l42->bias_thresholds[i] = thresholds[i]; 2066 else { 2067 dev_err(dev, 2068 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 2069 thresholds[i]); 2070 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2071 } 2072 } 2073 } else { 2074 for (i = 0; i < CS42L42_NUM_BIASES; i++) 2075 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2076 } 2077 2078 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 2079 if (!ret) { 2080 switch (val) { 2081 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 2082 cs42l42->hs_bias_ramp_rate = val; 2083 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 2084 break; 2085 case CS42L42_HSBIAS_RAMP_FAST: 2086 cs42l42->hs_bias_ramp_rate = val; 2087 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 2088 break; 2089 case CS42L42_HSBIAS_RAMP_SLOW: 2090 cs42l42->hs_bias_ramp_rate = val; 2091 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2092 break; 2093 case CS42L42_HSBIAS_RAMP_SLOWEST: 2094 cs42l42->hs_bias_ramp_rate = val; 2095 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 2096 break; 2097 default: 2098 dev_err(dev, 2099 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2100 val); 2101 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2102 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2103 } 2104 } else { 2105 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2106 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2107 } 2108 2109 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2110 CS42L42_HSBIAS_RAMP_MASK, 2111 (cs42l42->hs_bias_ramp_rate << 2112 CS42L42_HSBIAS_RAMP_SHIFT)); 2113 2114 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2115 cs42l42->hs_bias_sense_en = 0; 2116 else 2117 cs42l42->hs_bias_sense_en = 1; 2118 2119 return 0; 2120} 2121 2122/* Datasheet suspend sequence */ 2123static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { 2124 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), 2125 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), 2126 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), 2127 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), 2128 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), 2129 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), 2130 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), 2131 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), 2132 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), 2133 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), 2134 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), 2135 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), 2136 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), 2137 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), 2138 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), 2139 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), 2140 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), 2141 REG_SEQ0(CS42L42_HP_CTL, 0x0F), 2142 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), 2143 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), 2144 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), 2145 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), 2146 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), 2147 REG_SEQ0(CS42L42_DAC_CTL2, 0x02), 2148 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), 2149 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), 2150 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), 2151 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), 2152 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) 2153}; 2154 2155int cs42l42_suspend(struct device *dev) 2156{ 2157 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2158 unsigned int reg; 2159 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; 2160 int i, ret; 2161 2162 if (!cs42l42->init_done) 2163 return 0; 2164 2165 /* 2166 * Wait for threaded irq handler to be idle and stop it processing 2167 * future interrupts. This ensures a safe disable if the interrupt 2168 * is shared. 2169 */ 2170 mutex_lock(&cs42l42->irq_lock); 2171 cs42l42->suspended = true; 2172 2173 /* Save register values that will be overwritten by shutdown sequence */ 2174 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { 2175 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®); 2176 save_regs[i] = (u8)reg; 2177 } 2178 2179 /* Shutdown codec */ 2180 regmap_multi_reg_write(cs42l42->regmap, 2181 cs42l42_shutdown_seq, 2182 ARRAY_SIZE(cs42l42_shutdown_seq)); 2183 2184 /* All interrupt sources are now disabled */ 2185 mutex_unlock(&cs42l42->irq_lock); 2186 2187 /* Wait for power-down complete */ 2188 msleep(CS42L42_PDN_DONE_TIME_MS); 2189 ret = regmap_read_poll_timeout(cs42l42->regmap, 2190 CS42L42_CODEC_STATUS, reg, 2191 (reg & CS42L42_PDN_DONE_MASK), 2192 CS42L42_PDN_DONE_POLL_US, 2193 CS42L42_PDN_DONE_TIMEOUT_US); 2194 if (ret) 2195 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret); 2196 2197 /* Discharge FILT+ */ 2198 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2199 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); 2200 msleep(CS42L42_FILT_DISCHARGE_TIME_MS); 2201 2202 regcache_cache_only(cs42l42->regmap, true); 2203 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2204 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2205 2206 /* Restore register values to the regmap cache */ 2207 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) 2208 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]); 2209 2210 /* The cached address page register value is now stale */ 2211 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); 2212 2213 dev_dbg(dev, "System suspended\n"); 2214 2215 return 0; 2216 2217} 2218EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE); 2219 2220int cs42l42_resume(struct device *dev) 2221{ 2222 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2223 int ret; 2224 2225 if (!cs42l42->init_done) 2226 return 0; 2227 2228 /* 2229 * If jack was unplugged and re-plugged during suspend it could 2230 * have changed type but the tip-sense state hasn't changed. 2231 * Force a plugged state to be re-evaluated. 2232 */ 2233 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) 2234 cs42l42->plug_state = CS42L42_TS_TRANS; 2235 2236 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2237 if (ret != 0) { 2238 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2239 return ret; 2240 } 2241 2242 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2243 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2244 2245 dev_dbg(dev, "System resume powered up\n"); 2246 2247 return 0; 2248} 2249EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE); 2250 2251void cs42l42_resume_restore(struct device *dev) 2252{ 2253 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2254 2255 regcache_cache_only(cs42l42->regmap, false); 2256 regcache_mark_dirty(cs42l42->regmap); 2257 2258 mutex_lock(&cs42l42->irq_lock); 2259 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 2260 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 2261 regcache_sync(cs42l42->regmap); 2262 2263 cs42l42->suspended = false; 2264 mutex_unlock(&cs42l42->irq_lock); 2265 2266 dev_dbg(dev, "System resumed\n"); 2267} 2268EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE); 2269 2270static int __maybe_unused cs42l42_i2c_resume(struct device *dev) 2271{ 2272 int ret; 2273 2274 ret = cs42l42_resume(dev); 2275 if (ret) 2276 return ret; 2277 2278 cs42l42_resume_restore(dev); 2279 2280 return 0; 2281} 2282 2283int cs42l42_common_probe(struct cs42l42_private *cs42l42, 2284 const struct snd_soc_component_driver *component_drv, 2285 struct snd_soc_dai_driver *dai) 2286{ 2287 int ret, i; 2288 2289 dev_set_drvdata(cs42l42->dev, cs42l42); 2290 mutex_init(&cs42l42->irq_lock); 2291 2292 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); 2293 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2294 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2295 2296 ret = devm_regulator_bulk_get(cs42l42->dev, 2297 ARRAY_SIZE(cs42l42->supplies), 2298 cs42l42->supplies); 2299 if (ret != 0) { 2300 dev_err(cs42l42->dev, 2301 "Failed to request supplies: %d\n", ret); 2302 return ret; 2303 } 2304 2305 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2306 cs42l42->supplies); 2307 if (ret != 0) { 2308 dev_err(cs42l42->dev, 2309 "Failed to enable supplies: %d\n", ret); 2310 return ret; 2311 } 2312 2313 /* Reset the Device */ 2314 cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev, 2315 "reset", GPIOD_OUT_LOW); 2316 if (IS_ERR(cs42l42->reset_gpio)) { 2317 ret = PTR_ERR(cs42l42->reset_gpio); 2318 goto err_disable_noreset; 2319 } 2320 2321 if (cs42l42->reset_gpio) { 2322 dev_dbg(cs42l42->dev, "Found reset GPIO\n"); 2323 2324 /* 2325 * ACPI can override the default GPIO state we requested 2326 * so ensure that we start with RESET low. 2327 */ 2328 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2329 2330 /* Ensure minimum reset pulse width */ 2331 usleep_range(10, 500); 2332 2333 /* 2334 * On SoundWire keep the chip in reset until we get an UNATTACH 2335 * notification from the SoundWire core. This acts as a 2336 * synchronization point to reject stale ATTACH notifications 2337 * if the chip was already enumerated before we reset it. 2338 */ 2339 if (cs42l42->sdw_peripheral) 2340 cs42l42->sdw_waiting_first_unattach = true; 2341 else 2342 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2343 } 2344 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2345 2346 /* Request IRQ if one was specified */ 2347 if (cs42l42->irq) { 2348 ret = request_threaded_irq(cs42l42->irq, 2349 NULL, cs42l42_irq_thread, 2350 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2351 "cs42l42", cs42l42); 2352 if (ret) { 2353 dev_err_probe(cs42l42->dev, ret, 2354 "Failed to request IRQ\n"); 2355 goto err_disable_noirq; 2356 } 2357 } 2358 2359 /* Register codec now so it can EPROBE_DEFER */ 2360 ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1); 2361 if (ret < 0) 2362 goto err; 2363 2364 return 0; 2365 2366err: 2367 if (cs42l42->irq) 2368 free_irq(cs42l42->irq, cs42l42); 2369 2370err_disable_noirq: 2371 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2372err_disable_noreset: 2373 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2374 2375 return ret; 2376} 2377EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE); 2378 2379int cs42l42_init(struct cs42l42_private *cs42l42) 2380{ 2381 unsigned int reg; 2382 int devid, ret; 2383 2384 /* initialize codec */ 2385 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2386 if (devid < 0) { 2387 ret = devid; 2388 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret); 2389 goto err_disable; 2390 } 2391 2392 if (devid != cs42l42->devid) { 2393 ret = -ENODEV; 2394 dev_err(cs42l42->dev, 2395 "CS42L%x Device ID (%X). Expected %X\n", 2396 cs42l42->devid & 0xff, devid, cs42l42->devid); 2397 goto err_disable; 2398 } 2399 2400 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2401 if (ret < 0) { 2402 dev_err(cs42l42->dev, "Get Revision ID failed\n"); 2403 goto err_shutdown; 2404 } 2405 2406 dev_info(cs42l42->dev, 2407 "Cirrus Logic CS42L%x, Revision: %02X\n", 2408 cs42l42->devid & 0xff, reg & 0xFF); 2409 2410 /* Power up the codec */ 2411 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2412 CS42L42_ASP_DAO_PDN_MASK | 2413 CS42L42_ASP_DAI_PDN_MASK | 2414 CS42L42_MIXER_PDN_MASK | 2415 CS42L42_EQ_PDN_MASK | 2416 CS42L42_HP_PDN_MASK | 2417 CS42L42_ADC_PDN_MASK | 2418 CS42L42_PDN_ALL_MASK, 2419 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2420 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2421 (1 << CS42L42_MIXER_PDN_SHIFT) | 2422 (1 << CS42L42_EQ_PDN_SHIFT) | 2423 (1 << CS42L42_HP_PDN_SHIFT) | 2424 (1 << CS42L42_ADC_PDN_SHIFT) | 2425 (0 << CS42L42_PDN_ALL_SHIFT)); 2426 2427 ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42); 2428 if (ret != 0) 2429 goto err_shutdown; 2430 2431 /* 2432 * SRC power is linked to ASP power so doesn't work in Soundwire mode. 2433 * Override it and use DAPM to control SRC power for Soundwire. 2434 */ 2435 if (cs42l42->sdw_peripheral) { 2436 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2437 CS42L42_SRC_PDN_OVERRIDE_MASK | 2438 CS42L42_DAC_SRC_PDNB_MASK | 2439 CS42L42_ADC_SRC_PDNB_MASK, 2440 CS42L42_SRC_PDN_OVERRIDE_MASK); 2441 } 2442 2443 /* Setup headset detection */ 2444 cs42l42_setup_hs_type_detect(cs42l42); 2445 2446 /* 2447 * Set init_done before unmasking interrupts so any triggered 2448 * immediately will be handled. 2449 */ 2450 cs42l42->init_done = true; 2451 2452 /* Mask/Unmask Interrupts */ 2453 cs42l42_set_interrupt_masks(cs42l42); 2454 2455 return 0; 2456 2457err_shutdown: 2458 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2459 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2460 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2461 2462err_disable: 2463 if (cs42l42->irq) 2464 free_irq(cs42l42->irq, cs42l42); 2465 2466 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2467 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2468 cs42l42->supplies); 2469 return ret; 2470} 2471EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE); 2472 2473void cs42l42_common_remove(struct cs42l42_private *cs42l42) 2474{ 2475 if (cs42l42->irq) 2476 free_irq(cs42l42->irq, cs42l42); 2477 2478 /* 2479 * The driver might not have control of reset and power supplies, 2480 * so ensure that the chip internals are powered down. 2481 */ 2482 if (cs42l42->init_done) { 2483 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2484 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2485 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2486 } 2487 2488 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2489 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2490} 2491EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE); 2492 2493MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2494MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2495MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2496MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2497MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2498MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2499MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2500MODULE_LICENSE("GPL"); 2501