162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * AMD ALSA SoC PDM Driver
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright 2020 Advanced Micro Devices, Inc.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include "rn_chip_offset_byte.h"
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#define ACP_DEVS		3
1162306a36Sopenharmony_ci#define ACP_PHY_BASE_ADDRESS 0x1240000
1262306a36Sopenharmony_ci#define	ACP_REG_START	0x1240000
1362306a36Sopenharmony_ci#define	ACP_REG_END	0x1250200
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci#define ACP_DEVICE_ID 0x15E2
1662306a36Sopenharmony_ci#define ACP_POWER_ON 0x00
1762306a36Sopenharmony_ci#define ACP_POWER_ON_IN_PROGRESS 0x01
1862306a36Sopenharmony_ci#define ACP_POWER_OFF 0x02
1962306a36Sopenharmony_ci#define ACP_POWER_OFF_IN_PROGRESS 0x03
2062306a36Sopenharmony_ci#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci#define ACP_PGFSM_CNTL_POWER_ON_MASK    0x01
2362306a36Sopenharmony_ci#define ACP_PGFSM_CNTL_POWER_OFF_MASK   0x00
2462306a36Sopenharmony_ci#define ACP_PGFSM_STATUS_MASK           0x03
2562306a36Sopenharmony_ci#define ACP_POWERED_ON                  0x00
2662306a36Sopenharmony_ci#define ACP_POWER_ON_IN_PROGRESS        0x01
2762306a36Sopenharmony_ci#define ACP_POWERED_OFF                 0x02
2862306a36Sopenharmony_ci#define ACP_POWER_OFF_IN_PROGRESS       0x03
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci#define ACP_ERROR_MASK 0x20000000
3162306a36Sopenharmony_ci#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
3262306a36Sopenharmony_ci#define PDM_DMA_STAT 0x10
3362306a36Sopenharmony_ci#define PDM_DMA_INTR_MASK  0x10000
3462306a36Sopenharmony_ci#define ACP_ERROR_STAT 29
3562306a36Sopenharmony_ci#define PDM_DECIMATION_FACTOR 0x2
3662306a36Sopenharmony_ci#define ACP_PDM_CLK_FREQ_MASK 0x07
3762306a36Sopenharmony_ci#define ACP_WOV_GAIN_CONTROL	GENMASK(4, 3)
3862306a36Sopenharmony_ci#define ACP_PDM_ENABLE 0x01
3962306a36Sopenharmony_ci#define ACP_PDM_DISABLE 0x00
4062306a36Sopenharmony_ci#define ACP_PDM_DMA_EN_STATUS 0x02
4162306a36Sopenharmony_ci#define TWO_CH 0x02
4262306a36Sopenharmony_ci#define DELAY_US 5
4362306a36Sopenharmony_ci#define ACP_COUNTER 20000
4462306a36Sopenharmony_ci/* time in ms for runtime suspend delay */
4562306a36Sopenharmony_ci#define ACP_SUSPEND_DELAY_MS	2000
4662306a36Sopenharmony_ci
4762306a36Sopenharmony_ci#define ACP_SRAM_PTE_OFFSET	0x02050000
4862306a36Sopenharmony_ci#define PAGE_SIZE_4K_ENABLE     0x2
4962306a36Sopenharmony_ci#define MEM_WINDOW_START	0x4000000
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci#define CAPTURE_MIN_NUM_PERIODS     4
5262306a36Sopenharmony_ci#define CAPTURE_MAX_NUM_PERIODS     4
5362306a36Sopenharmony_ci#define CAPTURE_MAX_PERIOD_SIZE     8192
5462306a36Sopenharmony_ci#define CAPTURE_MIN_PERIOD_SIZE     4096
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
5762306a36Sopenharmony_ci#define MIN_BUFFER MAX_BUFFER
5862306a36Sopenharmony_ci#define	ACP_DMIC_AUTO   -1
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_cistruct pdm_dev_data {
6162306a36Sopenharmony_ci	u32 pdm_irq;
6262306a36Sopenharmony_ci	void __iomem *acp_base;
6362306a36Sopenharmony_ci	struct snd_pcm_substream *capture_stream;
6462306a36Sopenharmony_ci};
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_cistruct pdm_stream_instance {
6762306a36Sopenharmony_ci	u16 num_pages;
6862306a36Sopenharmony_ci	u16 channels;
6962306a36Sopenharmony_ci	dma_addr_t dma_addr;
7062306a36Sopenharmony_ci	u64 bytescount;
7162306a36Sopenharmony_ci	void __iomem *acp_base;
7262306a36Sopenharmony_ci};
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ciunion acp_pdm_dma_count {
7562306a36Sopenharmony_ci	struct {
7662306a36Sopenharmony_ci	u32 low;
7762306a36Sopenharmony_ci	u32 high;
7862306a36Sopenharmony_ci	} bcount;
7962306a36Sopenharmony_ci	u64 bytescount;
8062306a36Sopenharmony_ci};
8162306a36Sopenharmony_ci
8262306a36Sopenharmony_cistatic inline u32 rn_readl(void __iomem *base_addr)
8362306a36Sopenharmony_ci{
8462306a36Sopenharmony_ci	return readl(base_addr - ACP_PHY_BASE_ADDRESS);
8562306a36Sopenharmony_ci}
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_cistatic inline void rn_writel(u32 val, void __iomem *base_addr)
8862306a36Sopenharmony_ci{
8962306a36Sopenharmony_ci	writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
9062306a36Sopenharmony_ci}
9162306a36Sopenharmony_ci
9262306a36Sopenharmony_ci/* Machine configuration */
9362306a36Sopenharmony_ciint snd_amd_acp_find_config(struct pci_dev *pci);
94