1// SPDX-License-Identifier: GPL-2.0-or-later 2/* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). 3 * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de> 4 * 5 * Framework borrowed from Bart Hartgers's als4000.c. 6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), 7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). 8 * Other versions are: 9 * PCI168 A(W), sub ID 1800 10 * PCI168 A/AP, sub ID 8000 11 * Please give me feedback in case you try my driver with one of these!! 12 * 13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download 14 * (XP/Vista do not support this card at all but every Linux distribution 15 * has very good support out of the box; 16 * just to make sure that the right people hit this and get to know that, 17 * despite the high level of Internet ignorance - as usual :-P - 18 * about very good support for this card - on Linux!) 19 * 20 * NOTES 21 * Since Aztech does not provide any chipset documentation, 22 * even on repeated request to various addresses, 23 * and the answer that was finally given was negative 24 * (and I was stupid enough to manage to get hold of a PCI168 soundcard 25 * in the first place >:-P}), 26 * I was forced to base this driver on reverse engineering 27 * (3 weeks' worth of evenings filled with driver work). 28 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) 29 * 30 * It is quite likely that the AZF3328 chip is the PCI cousin of the 31 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. 32 * 33 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name 34 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, 35 * Fincitec acquired by National Semiconductor in 2002, together with the 36 * Fincitec-related company ARSmikro) has the following features: 37 * 38 * - compatibility & compliance: 39 * - Microsoft PC 97 ("PC 97 Hardware Design Guide", 40 * http://www.microsoft.com/whdc/archive/pcguides.mspx) 41 * - Microsoft PC 98 Baseline Audio 42 * - MPU401 UART 43 * - Sound Blaster Emulation (DOS Box) 44 * - builtin AC97 conformant codec (SNR over 80dB) 45 * Note that "conformant" != "compliant"!! this chip's mixer register layout 46 * *differs* from the standard AC97 layout: 47 * they chose to not implement the headphone register (which is not a 48 * problem since it's merely optional), yet when doing this, they committed 49 * the grave sin of letting other registers follow immediately instead of 50 * keeping a headphone dummy register, thereby shifting the mixer register 51 * addresses illegally. So far unfortunately it looks like the very flexible 52 * ALSA AC97 support is still not enough to easily compensate for such a 53 * grave layout violation despite all tweaks and quirks mechanisms it offers. 54 * Well, not quite: now ac97 layer is much improved (bus-specific ops!), 55 * thus I was able to implement support - it's actually working quite well. 56 * An interesting item might be Aztech AMR 2800-W, since it's an AC97 57 * modem card which might reveal the Aztech-specific codec ID which 58 * we might want to pretend, too. Dito PCI168's brother, PCI368, 59 * where the advertising datasheet says it's AC97-based and has a 60 * Digital Enhanced Game Port. 61 * - builtin genuine OPL3 - verified to work fine, 20080506 62 * - full duplex 16bit playback/record at independent sampling rate 63 * - MPU401 (+ legacy address support, claimed by one official spec sheet) 64 * FIXME: how to enable legacy addr?? 65 * - game port (legacy address support) 66 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven 67 * features supported). - See common term "Digital Enhanced Game Port"... 68 * (probably DirectInput 3.0 spec - confirm) 69 * - builtin 3D enhancement (said to be YAMAHA Ymersion) 70 * - built-in General DirectX timer having a 20 bits counter 71 * with 1us resolution (see below!) 72 * - I2S serial output port for external DAC 73 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] 74 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI 75 * - supports hardware volume control 76 * - single chip low cost solution (128 pin QFP) 77 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] 78 * required for Microsoft's logo compliance (FIXME: where?) 79 * At least the Trident 4D Wave DX has one bit somewhere 80 * to enable writes to PCI subsystem VID registers, that should be it. 81 * This might easily be in extended PCI reg space, since PCI168 also has 82 * some custom data starting at 0x80. What kind of config settings 83 * are located in our extended PCI space anyway?? 84 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms 85 * [TDA1517P chip] 86 * 87 * Note that this driver now is actually *better* than the Windows driver, 88 * since it additionally supports the card's 1MHz DirectX timer - just try 89 * the following snd-seq module parameters etc.: 90 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 91 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 92 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 93 * - "timidity -iAv -B2,8 -Os -EFreverb=0" 94 * - "pmidi -p 128:0 jazz.mid" 95 * 96 * OPL3 hardware playback testing, try something like: 97 * cat /proc/asound/hwdep 98 * and 99 * aconnect -o 100 * Then use 101 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 102 * where x,y is the xx-yy number as given in hwdep. 103 * Then try 104 * pmidi -p a:b jazz.mid 105 * where a:b is the client number plus 0 usually, as given by aconnect above. 106 * Oh, and make sure to unmute the FM mixer control (doh!) 107 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) 108 * despite no CPU activity, possibly due to hindering ACPI idling somehow. 109 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. 110 * Higher PCM / FM mixer levels seem to conflict (causes crackling), 111 * at least sometimes. Maybe even use with hardware sequencer timer above :) 112 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. 113 * 114 * Certain PCI versions of this card are susceptible to DMA traffic underruns 115 * in some systems (resulting in sound crackling/clicking/popping), 116 * probably because they don't have a DMA FIFO buffer or so. 117 * Overview (PCI ID/PCI subID/PCI rev.): 118 * - no DMA crackling on SiS735: 0x50DC/0x1801/16 119 * - unknown performance: 0x50DC/0x1801/10 120 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) 121 * 122 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is 123 * supposed to be very fast and supposed to get rid of crackling much 124 * better than a VIA, yet ironically I still get crackling, like many other 125 * people with the same chipset. 126 * Possible remedies: 127 * - use speaker (amplifier) output instead of headphone output 128 * (in case crackling is due to overloaded output clipping) 129 * - plug card into a different PCI slot, preferably one that isn't shared 130 * too much (this helps a lot, but not completely!) 131 * - get rid of PCI VGA card, use AGP instead 132 * - upgrade or downgrade BIOS 133 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) 134 * Not too helpful. 135 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS 136 * 137 * BUGS 138 * - full-duplex might *still* be problematic, however a recent test was fine 139 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated 140 * if you set PCM output switch to "pre 3D" instead of "post 3D". 141 * If this can't be set, then get a mixer application that Isn't Stupid (tm) 142 * (e.g. kmix, gamix) - unfortunately several are!! 143 * - locking is not entirely clean, especially the audio stream activity 144 * ints --> may be racy 145 * - an _unconnected_ secondary joystick at the gameport will be reported 146 * to be "active" (floating values, not precisely -1) due to the way we need 147 * to read the Digital Enhanced Game Port. Not sure whether it is fixable. 148 * 149 * TODO 150 * - use PCI_VDEVICE 151 * - verify driver status on x86_64 152 * - test multi-card driver operation 153 * - (ab)use 1MHz DirectX timer as kernel clocksource 154 * - test MPU401 MIDI playback etc. 155 * - add more power micro-management (disable various units of the card 156 * as long as they're unused, to improve audio quality and save power). 157 * However this requires more I/O ports which I haven't figured out yet 158 * and which thus might not even exist... 159 * The standard suspend/resume functionality could probably make use of 160 * some improvement, too... 161 * - figure out what all unknown port bits are responsible for 162 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code 163 * fully accept our quite incompatible ""AC97"" mixer and thus save some 164 * code (but I'm not too optimistic that doing this is possible at all) 165 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. 166 */ 167 168#include <linux/io.h> 169#include <linux/init.h> 170#include <linux/bug.h> /* WARN_ONCE */ 171#include <linux/pci.h> 172#include <linux/delay.h> 173#include <linux/slab.h> 174#include <linux/gameport.h> 175#include <linux/module.h> 176#include <linux/dma-mapping.h> 177#include <sound/core.h> 178#include <sound/control.h> 179#include <sound/pcm.h> 180#include <sound/rawmidi.h> 181#include <sound/mpu401.h> 182#include <sound/opl3.h> 183#include <sound/initval.h> 184/* 185 * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap. 186 * If the AC97 compatibility parts we needed to implement locally turn out 187 * to work nicely, then remove the old implementation eventually. 188 */ 189#define AZF_USE_AC97_LAYER 1 190 191#ifdef AZF_USE_AC97_LAYER 192#include <sound/ac97_codec.h> 193#endif 194#include "azt3328.h" 195 196MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); 197MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); 198MODULE_LICENSE("GPL"); 199 200#if IS_REACHABLE(CONFIG_GAMEPORT) 201#define SUPPORT_GAMEPORT 1 202#endif 203 204/* === Debug settings === 205 Further diagnostic functionality than the settings below 206 does not need to be provided, since one can easily write a POSIX shell script 207 to dump the card's I/O ports (those listed in lspci -v -v): 208 dump() 209 { 210 local descr=$1; local addr=$2; local count=$3 211 212 echo "${descr}: ${count} @ ${addr}:" 213 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ 214 2>/dev/null| hexdump -C 215 } 216 and then use something like 217 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", 218 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", 219 possibly within a "while true; do ... sleep 1; done" loop. 220 Tweaking ports could be done using 221 VALSTRING="`printf "%02x" $value`" 222 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ 223 2>/dev/null 224*/ 225 226static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 227module_param_array(index, int, NULL, 0444); 228MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); 229 230static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 231module_param_array(id, charp, NULL, 0444); 232MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); 233 234static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 235module_param_array(enable, bool, NULL, 0444); 236MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); 237 238static int seqtimer_scaling = 128; 239module_param(seqtimer_scaling, int, 0444); 240MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); 241 242enum snd_azf3328_codec_type { 243 /* warning: fixed indices (also used for bitmask checks!) */ 244 AZF_CODEC_PLAYBACK = 0, 245 AZF_CODEC_CAPTURE = 1, 246 AZF_CODEC_I2S_OUT = 2, 247}; 248 249struct snd_azf3328_codec_data { 250 unsigned long io_base; /* keep first! (avoid offset calc) */ 251 unsigned int dma_base; /* helper to avoid an indirection in hotpath */ 252 spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ 253 struct snd_pcm_substream *substream; 254 bool running; 255 enum snd_azf3328_codec_type type; 256 const char *name; 257}; 258 259struct snd_azf3328 { 260 /* often-used fields towards beginning, then grouped */ 261 262 unsigned long ctrl_io; /* usually 0xb000, size 128 */ 263 unsigned long game_io; /* usually 0xb400, size 8 */ 264 unsigned long mpu_io; /* usually 0xb800, size 4 */ 265 unsigned long opl3_io; /* usually 0xbc00, size 8 */ 266 unsigned long mixer_io; /* usually 0xc000, size 64 */ 267 268 spinlock_t reg_lock; 269 270 struct snd_timer *timer; 271 272 struct snd_pcm *pcm[3]; 273 274 /* playback, recording and I2S out codecs */ 275 struct snd_azf3328_codec_data codecs[3]; 276 277#ifdef AZF_USE_AC97_LAYER 278 struct snd_ac97 *ac97; 279#endif 280 281 struct snd_card *card; 282 struct snd_rawmidi *rmidi; 283 284#ifdef SUPPORT_GAMEPORT 285 struct gameport *gameport; 286 u16 axes[4]; 287#endif 288 289 struct pci_dev *pci; 290 int irq; 291 292 /* register 0x6a is write-only, thus need to remember setting. 293 * If we need to add more registers here, then we might try to fold this 294 * into some transparent combined shadow register handling with 295 * CONFIG_PM register storage below, but that's slightly difficult. */ 296 u16 shadow_reg_ctrl_6AH; 297 298#ifdef CONFIG_PM_SLEEP 299 /* register value containers for power management 300 * Note: not always full I/O range preserved (similar to Win driver!) */ 301 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; 302 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; 303 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; 304 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; 305 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; 306#endif 307}; 308 309static const struct pci_device_id snd_azf3328_ids[] = { 310 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ 311 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ 312 { 0, } 313}; 314 315MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); 316 317 318static int 319snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) 320{ 321 /* Well, strictly spoken, the inb/outb sequence isn't atomic 322 and would need locking. However we currently don't care 323 since it potentially complicates matters. */ 324 u8 prev = inb(reg), new; 325 326 new = (do_set) ? (prev|mask) : (prev & ~mask); 327 /* we need to always write the new value no matter whether it differs 328 * or not, since some register bits don't indicate their setting */ 329 outb(new, reg); 330 if (new != prev) 331 return 1; 332 333 return 0; 334} 335 336static inline void 337snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, 338 unsigned reg, 339 u8 value 340) 341{ 342 outb(value, codec->io_base + reg); 343} 344 345static inline u8 346snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) 347{ 348 return inb(codec->io_base + reg); 349} 350 351static inline void 352snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, 353 unsigned reg, 354 u16 value 355) 356{ 357 outw(value, codec->io_base + reg); 358} 359 360static inline u16 361snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) 362{ 363 return inw(codec->io_base + reg); 364} 365 366static inline void 367snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec, 368 unsigned reg, const void *buffer, int count 369) 370{ 371 unsigned long addr = codec->io_base + reg; 372 if (count) { 373 const u32 *buf = buffer; 374 do { 375 outl(*buf++, addr); 376 addr += 4; 377 } while (--count); 378 } 379} 380 381static inline u32 382snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) 383{ 384 return inl(codec->io_base + reg); 385} 386 387static inline void 388snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 389{ 390 outb(value, chip->ctrl_io + reg); 391} 392 393static inline u8 394snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) 395{ 396 return inb(chip->ctrl_io + reg); 397} 398 399static inline u16 400snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) 401{ 402 return inw(chip->ctrl_io + reg); 403} 404 405static inline void 406snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 407{ 408 outw(value, chip->ctrl_io + reg); 409} 410 411static inline void 412snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) 413{ 414 outl(value, chip->ctrl_io + reg); 415} 416 417static inline void 418snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 419{ 420 outb(value, chip->game_io + reg); 421} 422 423static inline void 424snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 425{ 426 outw(value, chip->game_io + reg); 427} 428 429static inline u8 430snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) 431{ 432 return inb(chip->game_io + reg); 433} 434 435static inline u16 436snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) 437{ 438 return inw(chip->game_io + reg); 439} 440 441static inline void 442snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 443{ 444 outw(value, chip->mixer_io + reg); 445} 446 447static inline u16 448snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) 449{ 450 return inw(chip->mixer_io + reg); 451} 452 453#define AZF_MUTE_BIT 0x80 454 455static bool 456snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip, 457 unsigned reg, bool do_mute 458) 459{ 460 unsigned long portbase = chip->mixer_io + reg + 1; 461 bool updated; 462 463 /* the mute bit is on the *second* (i.e. right) register of a 464 * left/right channel setting */ 465 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); 466 467 /* indicate whether it was muted before */ 468 return (do_mute) ? !updated : updated; 469} 470 471static inline bool 472snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip, 473 bool do_mute 474) 475{ 476 return snd_azf3328_mixer_mute_control( 477 chip, 478 IDX_MIXER_PLAY_MASTER, 479 do_mute 480 ); 481} 482 483static inline bool 484snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip, 485 bool do_mute 486) 487{ 488 return snd_azf3328_mixer_mute_control( 489 chip, 490 IDX_MIXER_WAVEOUT, 491 do_mute 492 ); 493} 494 495static inline void 496snd_azf3328_mixer_reset(const struct snd_azf3328 *chip) 497{ 498 /* reset (close) mixer: 499 * first mute master volume, then reset 500 */ 501 snd_azf3328_mixer_mute_control_master(chip, 1); 502 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 503} 504 505#ifdef AZF_USE_AC97_LAYER 506 507static inline void 508snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip, 509 unsigned short reg, const char *mode) 510{ 511 /* need to add some more or less clever emulation? */ 512 dev_warn(chip->card->dev, 513 "missing %s emulation for AC97 register 0x%02x!\n", 514 mode, reg); 515} 516 517/* 518 * Need to have _special_ AC97 mixer hardware register index mapper, 519 * to compensate for the issue of a rather AC97-incompatible hardware layout. 520 */ 521#define AZF_REG_MASK 0x3f 522#define AZF_AC97_REG_UNSUPPORTED 0x8000 523#define AZF_AC97_REG_REAL_IO_READ 0x4000 524#define AZF_AC97_REG_REAL_IO_WRITE 0x2000 525#define AZF_AC97_REG_REAL_IO_RW \ 526 (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE) 527#define AZF_AC97_REG_EMU_IO_READ 0x0400 528#define AZF_AC97_REG_EMU_IO_WRITE 0x0200 529#define AZF_AC97_REG_EMU_IO_RW \ 530 (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE) 531static unsigned short 532snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) 533{ 534 static const struct { 535 unsigned short azf_reg; 536 } azf_reg_mapper[] = { 537 /* Especially when taking into consideration 538 * mono/stereo-based sequence of azf vs. AC97 control series, 539 * it's quite obvious that azf simply got rid 540 * of the AC97_HEADPHONE control at its intended offset, 541 * thus shifted _all_ controls by one, 542 * and _then_ simply added it as an FMSYNTH control at the end, 543 * to make up for the offset. 544 * This means we'll have to translate indices here as 545 * needed and then do some tiny AC97 patch action 546 * (snd_ac97_rename_vol_ctl() etc.) - that's it. 547 */ 548 { /* AC97_RESET */ IDX_MIXER_RESET 549 | AZF_AC97_REG_REAL_IO_WRITE 550 | AZF_AC97_REG_EMU_IO_READ }, 551 { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER }, 552 /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */ 553 { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH }, 554 { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT }, 555 { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE }, 556 { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP }, 557 { /* AC97_PHONE */ IDX_MIXER_MODEMIN }, 558 { /* AC97_MIC */ IDX_MIXER_MIC }, 559 { /* AC97_LINE */ IDX_MIXER_LINEIN }, 560 { /* AC97_CD */ IDX_MIXER_CDAUDIO }, 561 { /* AC97_VIDEO */ IDX_MIXER_VIDEO }, 562 { /* AC97_AUX */ IDX_MIXER_AUX }, 563 { /* AC97_PCM */ IDX_MIXER_WAVEOUT }, 564 { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT }, 565 { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME }, 566 { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW }, 567 { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 }, 568 { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 }, 569 }; 570 571 unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED; 572 573 /* azf3328 supports the low-numbered and low-spec:ed range 574 of AC97 regs only */ 575 if (reg <= AC97_3D_CONTROL) { 576 unsigned short reg_idx = reg / 2; 577 reg_azf = azf_reg_mapper[reg_idx].azf_reg; 578 /* a translation-only entry means it's real read/write: */ 579 if (!(reg_azf & ~AZF_REG_MASK)) 580 reg_azf |= AZF_AC97_REG_REAL_IO_RW; 581 } else { 582 switch (reg) { 583 case AC97_POWERDOWN: 584 reg_azf = AZF_AC97_REG_EMU_IO_RW; 585 break; 586 case AC97_EXTENDED_ID: 587 reg_azf = AZF_AC97_REG_EMU_IO_READ; 588 break; 589 case AC97_EXTENDED_STATUS: 590 /* I don't know what the h*ll AC97 layer 591 * would consult this _extended_ register for 592 * given a base-AC97-advertised card, 593 * but let's just emulate it anyway :-P 594 */ 595 reg_azf = AZF_AC97_REG_EMU_IO_RW; 596 break; 597 case AC97_VENDOR_ID1: 598 case AC97_VENDOR_ID2: 599 reg_azf = AZF_AC97_REG_EMU_IO_READ; 600 break; 601 } 602 } 603 return reg_azf; 604} 605 606static const unsigned short 607azf_emulated_ac97_caps = 608 AC97_BC_DEDICATED_MIC | 609 AC97_BC_BASS_TREBLE | 610 /* Headphone is an FM Synth control here */ 611 AC97_BC_HEADPHONE | 612 /* no AC97_BC_LOUDNESS! */ 613 /* mask 0x7c00 is 614 vendor-specific 3D enhancement 615 vendor indicator. 616 Since there actually _is_ an 617 entry for Aztech Labs 618 (13), make damn sure 619 to indicate it. */ 620 (13 << 10); 621 622static const unsigned short 623azf_emulated_ac97_powerdown = 624 /* pretend everything to be active */ 625 AC97_PD_ADC_STATUS | 626 AC97_PD_DAC_STATUS | 627 AC97_PD_MIXER_STATUS | 628 AC97_PD_VREF_STATUS; 629 630/* 631 * Emulated, _inofficial_ vendor ID 632 * (there might be some devices such as the MR 2800-W 633 * which could reveal the real Aztech AC97 ID). 634 * We choose to use "AZT" prefix, and then use 1 to indicate PCI168 635 * (better don't use 0x68 since there's a PCI368 as well). 636 */ 637static const unsigned int 638azf_emulated_ac97_vendor_id = 0x415a5401; 639 640static unsigned short 641snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97) 642{ 643 const struct snd_azf3328 *chip = ac97->private_data; 644 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 645 unsigned short reg_val = 0; 646 bool unsupported = false; 647 648 dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n", 649 reg_ac97); 650 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 651 unsupported = true; 652 else { 653 if (reg_azf & AZF_AC97_REG_REAL_IO_READ) 654 reg_val = snd_azf3328_mixer_inw(chip, 655 reg_azf & AZF_REG_MASK); 656 else { 657 /* 658 * Proceed with dummy I/O read, 659 * to ensure compatible timing where this may matter. 660 * (ALSA AC97 layer usually doesn't call I/O functions 661 * due to intelligent I/O caching anyway) 662 * Choose a mixer register that's thoroughly unrelated 663 * to common audio (try to minimize distortion). 664 */ 665 snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H); 666 } 667 668 if (reg_azf & AZF_AC97_REG_EMU_IO_READ) { 669 switch (reg_ac97) { 670 case AC97_RESET: 671 reg_val |= azf_emulated_ac97_caps; 672 break; 673 case AC97_POWERDOWN: 674 reg_val |= azf_emulated_ac97_powerdown; 675 break; 676 case AC97_EXTENDED_ID: 677 case AC97_EXTENDED_STATUS: 678 /* AFAICS we simply can't support anything: */ 679 reg_val |= 0; 680 break; 681 case AC97_VENDOR_ID1: 682 reg_val = azf_emulated_ac97_vendor_id >> 16; 683 break; 684 case AC97_VENDOR_ID2: 685 reg_val = azf_emulated_ac97_vendor_id & 0xffff; 686 break; 687 default: 688 unsupported = true; 689 break; 690 } 691 } 692 } 693 if (unsupported) 694 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read"); 695 696 return reg_val; 697} 698 699static void 700snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97, 701 unsigned short reg_ac97, unsigned short val) 702{ 703 const struct snd_azf3328 *chip = ac97->private_data; 704 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 705 bool unsupported = false; 706 707 dev_dbg(chip->card->dev, 708 "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n", 709 reg_ac97, val); 710 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 711 unsupported = true; 712 else { 713 if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE) 714 snd_azf3328_mixer_outw( 715 chip, 716 reg_azf & AZF_REG_MASK, 717 val 718 ); 719 else 720 if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) { 721 switch (reg_ac97) { 722 case AC97_REC_GAIN_MIC: 723 case AC97_POWERDOWN: 724 case AC97_EXTENDED_STATUS: 725 /* 726 * Silently swallow these writes. 727 * Since for most registers our card doesn't 728 * actually support a comparable feature, 729 * this is exactly what we should do here. 730 * The AC97 layer's I/O caching probably 731 * automatically takes care of all the rest... 732 * (remembers written values etc.) 733 */ 734 break; 735 default: 736 unsupported = true; 737 break; 738 } 739 } 740 } 741 if (unsupported) 742 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write"); 743} 744 745static int 746snd_azf3328_mixer_new(struct snd_azf3328 *chip) 747{ 748 struct snd_ac97_bus *bus; 749 struct snd_ac97_template ac97; 750 static const struct snd_ac97_bus_ops ops = { 751 .write = snd_azf3328_mixer_ac97_write, 752 .read = snd_azf3328_mixer_ac97_read, 753 }; 754 int rc; 755 756 memset(&ac97, 0, sizeof(ac97)); 757 ac97.scaps = AC97_SCAP_SKIP_MODEM 758 | AC97_SCAP_AUDIO /* we support audio! */ 759 | AC97_SCAP_NO_SPDIF; 760 ac97.private_data = chip; 761 ac97.pci = chip->pci; 762 763 /* 764 * ALSA's AC97 layer has terrible init crackling issues, 765 * unfortunately, and since it makes use of AC97_RESET, 766 * there's no use trying to mute Master Playback proactively. 767 */ 768 769 rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus); 770 if (!rc) 771 rc = snd_ac97_mixer(bus, &ac97, &chip->ac97); 772 /* 773 * Make sure to complain loudly in case of AC97 init failure, 774 * since failure may happen quite often, 775 * due to this card being a very quirky AC97 "lookalike". 776 */ 777 if (rc) 778 dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc); 779 780 /* If we return an error here, then snd_card_free() should 781 * free up any ac97 codecs that got created, as well as the bus. 782 */ 783 return rc; 784} 785#else /* AZF_USE_AC97_LAYER */ 786static void 787snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, 788 unsigned reg, 789 unsigned char dst_vol_left, 790 unsigned char dst_vol_right, 791 int chan_sel, int delay 792) 793{ 794 unsigned long portbase = chip->mixer_io + reg; 795 unsigned char curr_vol_left = 0, curr_vol_right = 0; 796 int left_change = 0, right_change = 0; 797 798 if (chan_sel & SET_CHAN_LEFT) { 799 curr_vol_left = inb(portbase + 1); 800 801 /* take care of muting flag contained in left channel */ 802 if (curr_vol_left & AZF_MUTE_BIT) 803 dst_vol_left |= AZF_MUTE_BIT; 804 else 805 dst_vol_left &= ~AZF_MUTE_BIT; 806 807 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; 808 } 809 810 if (chan_sel & SET_CHAN_RIGHT) { 811 curr_vol_right = inb(portbase + 0); 812 813 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; 814 } 815 816 do { 817 if (left_change) { 818 if (curr_vol_left != dst_vol_left) { 819 curr_vol_left += left_change; 820 outb(curr_vol_left, portbase + 1); 821 } else 822 left_change = 0; 823 } 824 if (right_change) { 825 if (curr_vol_right != dst_vol_right) { 826 curr_vol_right += right_change; 827 828 /* during volume change, the right channel is crackling 829 * somewhat more than the left channel, unfortunately. 830 * This seems to be a hardware issue. */ 831 outb(curr_vol_right, portbase + 0); 832 } else 833 right_change = 0; 834 } 835 if (delay) 836 mdelay(delay); 837 } while ((left_change) || (right_change)); 838} 839 840/* 841 * general mixer element 842 */ 843struct azf3328_mixer_reg { 844 unsigned reg; 845 unsigned int lchan_shift, rchan_shift; 846 unsigned int mask; 847 unsigned int invert: 1; 848 unsigned int stereo: 1; 849 unsigned int enum_c: 4; 850}; 851 852#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ 853 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ 854 (mask << 16) | \ 855 (invert << 24) | \ 856 (stereo << 25) | \ 857 (enum_c << 26)) 858 859static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) 860{ 861 r->reg = val & 0xff; 862 r->lchan_shift = (val >> 8) & 0x0f; 863 r->rchan_shift = (val >> 12) & 0x0f; 864 r->mask = (val >> 16) & 0xff; 865 r->invert = (val >> 24) & 1; 866 r->stereo = (val >> 25) & 1; 867 r->enum_c = (val >> 26) & 0x0f; 868} 869 870/* 871 * mixer switches/volumes 872 */ 873 874#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ 875{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 876 .info = snd_azf3328_info_mixer, \ 877 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 878 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ 879} 880 881#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ 882{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 883 .info = snd_azf3328_info_mixer, \ 884 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 885 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ 886} 887 888#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ 889{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 890 .info = snd_azf3328_info_mixer, \ 891 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 892 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ 893} 894 895#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ 896{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 897 .info = snd_azf3328_info_mixer, \ 898 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 899 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ 900} 901 902#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ 903{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 904 .info = snd_azf3328_info_mixer_enum, \ 905 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ 906 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ 907} 908 909static int 910snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, 911 struct snd_ctl_elem_info *uinfo) 912{ 913 struct azf3328_mixer_reg reg; 914 915 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 916 uinfo->type = reg.mask == 1 ? 917 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 918 uinfo->count = reg.stereo + 1; 919 uinfo->value.integer.min = 0; 920 uinfo->value.integer.max = reg.mask; 921 return 0; 922} 923 924static int 925snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, 926 struct snd_ctl_elem_value *ucontrol) 927{ 928 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 929 struct azf3328_mixer_reg reg; 930 u16 oreg, val; 931 932 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 933 934 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 935 val = (oreg >> reg.lchan_shift) & reg.mask; 936 if (reg.invert) 937 val = reg.mask - val; 938 ucontrol->value.integer.value[0] = val; 939 if (reg.stereo) { 940 val = (oreg >> reg.rchan_shift) & reg.mask; 941 if (reg.invert) 942 val = reg.mask - val; 943 ucontrol->value.integer.value[1] = val; 944 } 945 dev_dbg(chip->card->dev, 946 "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", 947 reg.reg, oreg, 948 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 949 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); 950 return 0; 951} 952 953static int 954snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, 955 struct snd_ctl_elem_value *ucontrol) 956{ 957 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 958 struct azf3328_mixer_reg reg; 959 u16 oreg, nreg, val; 960 961 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 962 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 963 val = ucontrol->value.integer.value[0] & reg.mask; 964 if (reg.invert) 965 val = reg.mask - val; 966 nreg = oreg & ~(reg.mask << reg.lchan_shift); 967 nreg |= (val << reg.lchan_shift); 968 if (reg.stereo) { 969 val = ucontrol->value.integer.value[1] & reg.mask; 970 if (reg.invert) 971 val = reg.mask - val; 972 nreg &= ~(reg.mask << reg.rchan_shift); 973 nreg |= (val << reg.rchan_shift); 974 } 975 if (reg.mask >= 0x07) /* it's a volume control, so better take care */ 976 snd_azf3328_mixer_write_volume_gradually( 977 chip, reg.reg, nreg >> 8, nreg & 0xff, 978 /* just set both channels, doesn't matter */ 979 SET_CHAN_LEFT|SET_CHAN_RIGHT, 980 0); 981 else 982 snd_azf3328_mixer_outw(chip, reg.reg, nreg); 983 984 dev_dbg(chip->card->dev, 985 "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", 986 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 987 oreg, reg.lchan_shift, reg.rchan_shift, 988 nreg, snd_azf3328_mixer_inw(chip, reg.reg)); 989 return (nreg != oreg); 990} 991 992static int 993snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, 994 struct snd_ctl_elem_info *uinfo) 995{ 996 static const char * const texts1[] = { 997 "Mic1", "Mic2" 998 }; 999 static const char * const texts2[] = { 1000 "Mix", "Mic" 1001 }; 1002 static const char * const texts3[] = { 1003 "Mic", "CD", "Video", "Aux", 1004 "Line", "Mix", "Mix Mono", "Phone" 1005 }; 1006 static const char * const texts4[] = { 1007 "pre 3D", "post 3D" 1008 }; 1009 struct azf3328_mixer_reg reg; 1010 const char * const *p = NULL; 1011 1012 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1013 if (reg.reg == IDX_MIXER_ADVCTL2) { 1014 switch(reg.lchan_shift) { 1015 case 8: /* modem out sel */ 1016 p = texts1; 1017 break; 1018 case 9: /* mono sel source */ 1019 p = texts2; 1020 break; 1021 case 15: /* PCM Out Path */ 1022 p = texts4; 1023 break; 1024 } 1025 } else if (reg.reg == IDX_MIXER_REC_SELECT) 1026 p = texts3; 1027 1028 return snd_ctl_enum_info(uinfo, 1029 (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, 1030 reg.enum_c, p); 1031} 1032 1033static int 1034snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, 1035 struct snd_ctl_elem_value *ucontrol) 1036{ 1037 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1038 struct azf3328_mixer_reg reg; 1039 unsigned short val; 1040 1041 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1042 val = snd_azf3328_mixer_inw(chip, reg.reg); 1043 if (reg.reg == IDX_MIXER_REC_SELECT) { 1044 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); 1045 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); 1046 } else 1047 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); 1048 1049 dev_dbg(chip->card->dev, 1050 "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", 1051 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], 1052 reg.lchan_shift, reg.enum_c); 1053 return 0; 1054} 1055 1056static int 1057snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, 1058 struct snd_ctl_elem_value *ucontrol) 1059{ 1060 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1061 struct azf3328_mixer_reg reg; 1062 u16 oreg, nreg, val; 1063 1064 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1065 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 1066 val = oreg; 1067 if (reg.reg == IDX_MIXER_REC_SELECT) { 1068 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || 1069 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) 1070 return -EINVAL; 1071 val = (ucontrol->value.enumerated.item[0] << 8) | 1072 (ucontrol->value.enumerated.item[1] << 0); 1073 } else { 1074 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) 1075 return -EINVAL; 1076 val &= ~((reg.enum_c - 1) << reg.lchan_shift); 1077 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); 1078 } 1079 snd_azf3328_mixer_outw(chip, reg.reg, val); 1080 nreg = val; 1081 1082 dev_dbg(chip->card->dev, 1083 "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); 1084 return (nreg != oreg); 1085} 1086 1087static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = { 1088 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), 1089 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), 1090 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), 1091 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", 1092 IDX_MIXER_WAVEOUT, 0x1f, 1), 1093 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", 1094 IDX_MIXER_ADVCTL2, 7, 1), 1095 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), 1096 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), 1097 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), 1098 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), 1099 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), 1100 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), 1101 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), 1102 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), 1103 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), 1104 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), 1105 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), 1106 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), 1107 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), 1108 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), 1109 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), 1110 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), 1111 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), 1112 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), 1113 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), 1114 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), 1115 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), 1116 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), 1117 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), 1118 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), 1119 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ 1120 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), 1121 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), 1122 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), 1123 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ 1124 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ 1125#if MIXER_TESTING 1126 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), 1127 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), 1128 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), 1129 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), 1130 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), 1131 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), 1132 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), 1133 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), 1134 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), 1135 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), 1136 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), 1137 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), 1138 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), 1139 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), 1140 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), 1141 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), 1142#endif 1143}; 1144 1145static const u16 snd_azf3328_init_values[][2] = { 1146 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, 1147 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, 1148 { IDX_MIXER_BASSTREBLE, 0x0000 }, 1149 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, 1150 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, 1151 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, 1152 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, 1153 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, 1154 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, 1155 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, 1156 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, 1157 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, 1158 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, 1159}; 1160 1161static int 1162snd_azf3328_mixer_new(struct snd_azf3328 *chip) 1163{ 1164 struct snd_card *card; 1165 const struct snd_kcontrol_new *sw; 1166 unsigned int idx; 1167 int err; 1168 1169 if (snd_BUG_ON(!chip || !chip->card)) 1170 return -EINVAL; 1171 1172 card = chip->card; 1173 1174 /* mixer reset */ 1175 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 1176 1177 /* mute and zero volume channels */ 1178 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { 1179 snd_azf3328_mixer_outw(chip, 1180 snd_azf3328_init_values[idx][0], 1181 snd_azf3328_init_values[idx][1]); 1182 } 1183 1184 /* add mixer controls */ 1185 sw = snd_azf3328_mixer_controls; 1186 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); 1187 ++idx, ++sw) { 1188 err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip)); 1189 if (err < 0) 1190 return err; 1191 } 1192 snd_component_add(card, "AZF3328 mixer"); 1193 strcpy(card->mixername, "AZF3328 mixer"); 1194 1195 return 0; 1196} 1197#endif /* AZF_USE_AC97_LAYER */ 1198 1199static void 1200snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, 1201 enum azf_freq_t bitrate, 1202 unsigned int format_width, 1203 unsigned int channels 1204) 1205{ 1206 unsigned long flags; 1207 u16 val = 0xff00; 1208 u8 freq = 0; 1209 1210 switch (bitrate) { 1211 case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break; 1212 case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break; 1213 case AZF_FREQ_5512: 1214 /* the AZF3328 names it "5510" for some strange reason */ 1215 freq = SOUNDFORMAT_FREQ_5510; break; 1216 case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break; 1217 case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break; 1218 case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break; 1219 case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break; 1220 case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break; 1221 case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break; 1222 case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break; 1223 case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break; 1224 default: 1225 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); 1226 fallthrough; 1227 case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break; 1228 case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break; 1229 case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break; 1230 } 1231 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ 1232 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ 1233 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ 1234 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ 1235 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ 1236 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ 1237 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ 1238 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ 1239 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ 1240 1241 val |= freq; 1242 1243 if (channels == 2) 1244 val |= SOUNDFORMAT_FLAG_2CHANNELS; 1245 1246 if (format_width == 16) 1247 val |= SOUNDFORMAT_FLAG_16BIT; 1248 1249 spin_lock_irqsave(codec->lock, flags); 1250 1251 /* set bitrate/format */ 1252 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); 1253 1254 /* changing the bitrate/format settings switches off the 1255 * audio output with an annoying click in case of 8/16bit format change 1256 * (maybe shutting down DAC/ADC?), thus immediately 1257 * do some tweaking to reenable it and get rid of the clicking 1258 * (FIXME: yes, it works, but what exactly am I doing here?? :) 1259 * FIXME: does this have some side effects for full-duplex 1260 * or other dramatic side effects? */ 1261 /* do it for non-capture codecs only */ 1262 if (codec->type != AZF_CODEC_CAPTURE) 1263 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1264 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | 1265 DMA_RUN_SOMETHING1 | 1266 DMA_RUN_SOMETHING2 | 1267 SOMETHING_ALMOST_ALWAYS_SET | 1268 DMA_EPILOGUE_SOMETHING | 1269 DMA_SOMETHING_ELSE 1270 ); 1271 1272 spin_unlock_irqrestore(codec->lock, flags); 1273} 1274 1275static inline void 1276snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec 1277) 1278{ 1279 /* choose lowest frequency for low power consumption. 1280 * While this will cause louder noise due to rather coarse frequency, 1281 * it should never matter since output should always 1282 * get disabled properly when idle anyway. */ 1283 snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); 1284} 1285 1286static void 1287snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, 1288 unsigned bitmask, 1289 bool enable 1290) 1291{ 1292 bool do_mask = !enable; 1293 if (do_mask) 1294 chip->shadow_reg_ctrl_6AH |= bitmask; 1295 else 1296 chip->shadow_reg_ctrl_6AH &= ~bitmask; 1297 dev_dbg(chip->card->dev, 1298 "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", 1299 bitmask, do_mask, chip->shadow_reg_ctrl_6AH); 1300 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); 1301} 1302 1303static inline void 1304snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) 1305{ 1306 dev_dbg(chip->card->dev, "codec_enable %d\n", enable); 1307 /* no idea what exactly is being done here, but I strongly assume it's 1308 * PM related */ 1309 snd_azf3328_ctrl_reg_6AH_update( 1310 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable 1311 ); 1312} 1313 1314static void 1315snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, 1316 enum snd_azf3328_codec_type codec_type, 1317 bool enable 1318) 1319{ 1320 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 1321 bool need_change = (codec->running != enable); 1322 1323 dev_dbg(chip->card->dev, 1324 "codec_activity: %s codec, enable %d, need_change %d\n", 1325 codec->name, enable, need_change 1326 ); 1327 if (need_change) { 1328 static const struct { 1329 enum snd_azf3328_codec_type other1; 1330 enum snd_azf3328_codec_type other2; 1331 } peer_codecs[3] = 1332 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, 1333 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, 1334 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; 1335 bool call_function; 1336 1337 if (enable) 1338 /* if enable codec, call enable_codecs func 1339 to enable codec supply... */ 1340 call_function = 1; 1341 else { 1342 /* ...otherwise call enable_codecs func 1343 (which globally shuts down operation of codecs) 1344 only in case the other codecs are currently 1345 not active either! */ 1346 call_function = 1347 ((!chip->codecs[peer_codecs[codec_type].other1] 1348 .running) 1349 && (!chip->codecs[peer_codecs[codec_type].other2] 1350 .running)); 1351 } 1352 if (call_function) 1353 snd_azf3328_ctrl_enable_codecs(chip, enable); 1354 1355 /* ...and adjust clock, too 1356 * (reduce noise and power consumption) */ 1357 if (!enable) 1358 snd_azf3328_codec_setfmt_lowpower(codec); 1359 codec->running = enable; 1360 } 1361} 1362 1363static void 1364snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip, 1365 struct snd_azf3328_codec_data *codec, 1366 unsigned long addr, 1367 unsigned int period_bytes, 1368 unsigned int buffer_bytes 1369) 1370{ 1371 WARN_ONCE(period_bytes & 1, "odd period length!?\n"); 1372 WARN_ONCE(buffer_bytes != 2 * period_bytes, 1373 "missed our input expectations! %u vs. %u\n", 1374 buffer_bytes, period_bytes); 1375 if (!codec->running) { 1376 /* AZF3328 uses a two buffer pointer DMA transfer approach */ 1377 1378 unsigned long flags; 1379 1380 /* width 32bit (prevent overflow): */ 1381 u32 area_length; 1382 struct codec_setup_io { 1383 u32 dma_start_1; 1384 u32 dma_start_2; 1385 u32 dma_lengths; 1386 } __attribute__((packed)) setup_io; 1387 1388 area_length = buffer_bytes/2; 1389 1390 setup_io.dma_start_1 = addr; 1391 setup_io.dma_start_2 = addr+area_length; 1392 1393 dev_dbg(chip->card->dev, 1394 "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n", 1395 setup_io.dma_start_1, area_length, 1396 setup_io.dma_start_2, area_length, 1397 period_bytes, buffer_bytes); 1398 1399 /* Hmm, are we really supposed to decrement this by 1?? 1400 Most definitely certainly not: configuring full length does 1401 work properly (i.e. likely better), and BTW we 1402 violated possibly differing frame sizes with this... 1403 1404 area_length--; |* max. index *| 1405 */ 1406 1407 /* build combined I/O buffer length word */ 1408 setup_io.dma_lengths = (area_length << 16) | (area_length); 1409 1410 spin_lock_irqsave(codec->lock, flags); 1411 snd_azf3328_codec_outl_multi( 1412 codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3 1413 ); 1414 spin_unlock_irqrestore(codec->lock, flags); 1415 } 1416} 1417 1418static int 1419snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) 1420{ 1421 struct snd_pcm_runtime *runtime = substream->runtime; 1422 struct snd_azf3328_codec_data *codec = runtime->private_data; 1423#if 0 1424 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 1425 unsigned int count = snd_pcm_lib_period_bytes(substream); 1426#endif 1427 1428 codec->dma_base = runtime->dma_addr; 1429 1430#if 0 1431 snd_azf3328_codec_setfmt(codec, 1432 runtime->rate, 1433 snd_pcm_format_width(runtime->format), 1434 runtime->channels); 1435 snd_azf3328_codec_setdmaa(chip, codec, 1436 runtime->dma_addr, count, size); 1437#endif 1438 return 0; 1439} 1440 1441static int 1442snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1443{ 1444 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1445 struct snd_pcm_runtime *runtime = substream->runtime; 1446 struct snd_azf3328_codec_data *codec = runtime->private_data; 1447 int result = 0; 1448 u16 flags1; 1449 bool previously_muted = false; 1450 bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); 1451 1452 switch (cmd) { 1453 case SNDRV_PCM_TRIGGER_START: 1454 dev_dbg(chip->card->dev, "START PCM %s\n", codec->name); 1455 1456 if (is_main_mixer_playback_codec) { 1457 /* mute WaveOut (avoid clicking during setup) */ 1458 previously_muted = 1459 snd_azf3328_mixer_mute_control_pcm( 1460 chip, 1 1461 ); 1462 } 1463 1464 snd_azf3328_codec_setfmt(codec, 1465 runtime->rate, 1466 snd_pcm_format_width(runtime->format), 1467 runtime->channels); 1468 1469 spin_lock(codec->lock); 1470 /* first, remember current value: */ 1471 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1472 1473 /* stop transfer */ 1474 flags1 &= ~DMA_RESUME; 1475 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1476 1477 /* FIXME: clear interrupts or what??? */ 1478 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); 1479 spin_unlock(codec->lock); 1480 1481 snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, 1482 snd_pcm_lib_period_bytes(substream), 1483 snd_pcm_lib_buffer_bytes(substream) 1484 ); 1485 1486 spin_lock(codec->lock); 1487#ifdef WIN9X 1488 /* FIXME: enable playback/recording??? */ 1489 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; 1490 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1491 1492 /* start transfer again */ 1493 /* FIXME: what is this value (0x0010)??? */ 1494 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 1495 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1496#else /* NT4 */ 1497 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1498 0x0000); 1499 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1500 DMA_RUN_SOMETHING1); 1501 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1502 DMA_RUN_SOMETHING1 | 1503 DMA_RUN_SOMETHING2); 1504 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1505 DMA_RESUME | 1506 SOMETHING_ALMOST_ALWAYS_SET | 1507 DMA_EPILOGUE_SOMETHING | 1508 DMA_SOMETHING_ELSE); 1509#endif 1510 spin_unlock(codec->lock); 1511 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); 1512 1513 if (is_main_mixer_playback_codec) { 1514 /* now unmute WaveOut */ 1515 if (!previously_muted) 1516 snd_azf3328_mixer_mute_control_pcm( 1517 chip, 0 1518 ); 1519 } 1520 1521 dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name); 1522 break; 1523 case SNDRV_PCM_TRIGGER_RESUME: 1524 dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name); 1525 /* resume codec if we were active */ 1526 spin_lock(codec->lock); 1527 if (codec->running) 1528 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1529 snd_azf3328_codec_inw( 1530 codec, IDX_IO_CODEC_DMA_FLAGS 1531 ) | DMA_RESUME 1532 ); 1533 spin_unlock(codec->lock); 1534 break; 1535 case SNDRV_PCM_TRIGGER_STOP: 1536 dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name); 1537 1538 if (is_main_mixer_playback_codec) { 1539 /* mute WaveOut (avoid clicking during setup) */ 1540 previously_muted = 1541 snd_azf3328_mixer_mute_control_pcm( 1542 chip, 1 1543 ); 1544 } 1545 1546 spin_lock(codec->lock); 1547 /* first, remember current value: */ 1548 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1549 1550 /* stop transfer */ 1551 flags1 &= ~DMA_RESUME; 1552 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1553 1554 /* hmm, is this really required? we're resetting the same bit 1555 * immediately thereafter... */ 1556 flags1 |= DMA_RUN_SOMETHING1; 1557 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1558 1559 flags1 &= ~DMA_RUN_SOMETHING1; 1560 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1561 spin_unlock(codec->lock); 1562 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); 1563 1564 if (is_main_mixer_playback_codec) { 1565 /* now unmute WaveOut */ 1566 if (!previously_muted) 1567 snd_azf3328_mixer_mute_control_pcm( 1568 chip, 0 1569 ); 1570 } 1571 1572 dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name); 1573 break; 1574 case SNDRV_PCM_TRIGGER_SUSPEND: 1575 dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name); 1576 /* make sure codec is stopped */ 1577 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1578 snd_azf3328_codec_inw( 1579 codec, IDX_IO_CODEC_DMA_FLAGS 1580 ) & ~DMA_RESUME 1581 ); 1582 break; 1583 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1584 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 1585 break; 1586 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1587 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 1588 break; 1589 default: 1590 WARN(1, "FIXME: unknown trigger mode!\n"); 1591 return -EINVAL; 1592 } 1593 1594 return result; 1595} 1596 1597static snd_pcm_uframes_t 1598snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream 1599) 1600{ 1601 const struct snd_azf3328_codec_data *codec = 1602 substream->runtime->private_data; 1603 unsigned long result; 1604 snd_pcm_uframes_t frmres; 1605 1606 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); 1607 1608 /* calculate offset */ 1609#ifdef QUERY_HARDWARE 1610 result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); 1611#else 1612 result -= codec->dma_base; 1613#endif 1614 frmres = bytes_to_frames( substream->runtime, result); 1615 dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n", 1616 jiffies, codec->name, result, frmres); 1617 return frmres; 1618} 1619 1620/******************************************************************/ 1621 1622#ifdef SUPPORT_GAMEPORT 1623static inline void 1624snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, 1625 bool enable 1626) 1627{ 1628 snd_azf3328_io_reg_setb( 1629 chip->game_io+IDX_GAME_HWCONFIG, 1630 GAME_HWCFG_IRQ_ENABLE, 1631 enable 1632 ); 1633} 1634 1635static inline void 1636snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, 1637 bool enable 1638) 1639{ 1640 snd_azf3328_io_reg_setb( 1641 chip->game_io+IDX_GAME_HWCONFIG, 1642 GAME_HWCFG_LEGACY_ADDRESS_ENABLE, 1643 enable 1644 ); 1645} 1646 1647static void 1648snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, 1649 unsigned int freq_cfg 1650) 1651{ 1652 snd_azf3328_io_reg_setb( 1653 chip->game_io+IDX_GAME_HWCONFIG, 1654 0x02, 1655 (freq_cfg & 1) != 0 1656 ); 1657 snd_azf3328_io_reg_setb( 1658 chip->game_io+IDX_GAME_HWCONFIG, 1659 0x04, 1660 (freq_cfg & 2) != 0 1661 ); 1662} 1663 1664static inline void 1665snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) 1666{ 1667 snd_azf3328_ctrl_reg_6AH_update( 1668 chip, IO_6A_SOMETHING2_GAMEPORT, enable 1669 ); 1670} 1671 1672static inline void 1673snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1674{ 1675 /* 1676 * skeleton handler only 1677 * (we do not want axis reading in interrupt handler - too much load!) 1678 */ 1679 dev_dbg(chip->card->dev, "gameport irq\n"); 1680 1681 /* this should ACK the gameport IRQ properly, hopefully. */ 1682 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); 1683} 1684 1685static int 1686snd_azf3328_gameport_open(struct gameport *gameport, int mode) 1687{ 1688 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1689 int res; 1690 1691 dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode); 1692 switch (mode) { 1693 case GAMEPORT_MODE_COOKED: 1694 case GAMEPORT_MODE_RAW: 1695 res = 0; 1696 break; 1697 default: 1698 res = -1; 1699 break; 1700 } 1701 1702 snd_azf3328_gameport_set_counter_frequency(chip, 1703 GAME_HWCFG_ADC_COUNTER_FREQ_STD); 1704 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); 1705 1706 return res; 1707} 1708 1709static void 1710snd_azf3328_gameport_close(struct gameport *gameport) 1711{ 1712 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1713 1714 dev_dbg(chip->card->dev, "gameport_close\n"); 1715 snd_azf3328_gameport_set_counter_frequency(chip, 1716 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1717 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1718} 1719 1720static int 1721snd_azf3328_gameport_cooked_read(struct gameport *gameport, 1722 int *axes, 1723 int *buttons 1724) 1725{ 1726 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1727 int i; 1728 u8 val; 1729 unsigned long flags; 1730 1731 if (snd_BUG_ON(!chip)) 1732 return 0; 1733 1734 spin_lock_irqsave(&chip->reg_lock, flags); 1735 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); 1736 *buttons = (~(val) >> 4) & 0xf; 1737 1738 /* ok, this one is a bit dirty: cooked_read is being polled by a timer, 1739 * thus we're atomic and cannot actively wait in here 1740 * (which would be useful for us since it probably would be better 1741 * to trigger a measurement in here, then wait a short amount of 1742 * time until it's finished, then read values of _this_ measurement). 1743 * 1744 * Thus we simply resort to reading values if they're available already 1745 * and trigger the next measurement. 1746 */ 1747 1748 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); 1749 if (val & GAME_AXES_SAMPLING_READY) { 1750 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { 1751 /* configure the axis to read */ 1752 val = (i << 4) | 0x0f; 1753 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1754 1755 chip->axes[i] = snd_azf3328_game_inw( 1756 chip, IDX_GAME_AXIS_VALUE 1757 ); 1758 } 1759 } 1760 1761 /* trigger next sampling of axes, to be evaluated the next time we 1762 * enter this function */ 1763 1764 /* for some very, very strange reason we cannot enable 1765 * Measurement Ready monitoring for all axes here, 1766 * at least not when only one joystick connected */ 1767 val = 0x03; /* we're able to monitor axes 1 and 2 only */ 1768 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1769 1770 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); 1771 spin_unlock_irqrestore(&chip->reg_lock, flags); 1772 1773 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { 1774 axes[i] = chip->axes[i]; 1775 if (axes[i] == 0xffff) 1776 axes[i] = -1; 1777 } 1778 1779 dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n", 1780 axes[0], axes[1], axes[2], axes[3], *buttons); 1781 1782 return 0; 1783} 1784 1785static int 1786snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) 1787{ 1788 struct gameport *gp; 1789 1790 chip->gameport = gp = gameport_allocate_port(); 1791 if (!gp) { 1792 dev_err(chip->card->dev, "cannot alloc memory for gameport\n"); 1793 return -ENOMEM; 1794 } 1795 1796 gameport_set_name(gp, "AZF3328 Gameport"); 1797 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1798 gameport_set_dev_parent(gp, &chip->pci->dev); 1799 gp->io = chip->game_io; 1800 gameport_set_port_data(gp, chip); 1801 1802 gp->open = snd_azf3328_gameport_open; 1803 gp->close = snd_azf3328_gameport_close; 1804 gp->fuzz = 16; /* seems ok */ 1805 gp->cooked_read = snd_azf3328_gameport_cooked_read; 1806 1807 /* DISABLE legacy address: we don't need it! */ 1808 snd_azf3328_gameport_legacy_address_enable(chip, 0); 1809 1810 snd_azf3328_gameport_set_counter_frequency(chip, 1811 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1812 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1813 1814 gameport_register_port(chip->gameport); 1815 1816 return 0; 1817} 1818 1819static void 1820snd_azf3328_gameport_free(struct snd_azf3328 *chip) 1821{ 1822 if (chip->gameport) { 1823 gameport_unregister_port(chip->gameport); 1824 chip->gameport = NULL; 1825 } 1826 snd_azf3328_gameport_irq_enable(chip, 0); 1827} 1828#else 1829static inline int 1830snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } 1831static inline void 1832snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } 1833static inline void 1834snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1835{ 1836 dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n"); 1837} 1838#endif /* SUPPORT_GAMEPORT */ 1839 1840/******************************************************************/ 1841 1842static inline void 1843snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which) 1844{ 1845 dev_dbg(chip->card->dev, 1846 "unknown IRQ type (%x) occurred, please report!\n", 1847 which); 1848} 1849 1850static inline void 1851snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip, 1852 const struct snd_azf3328_codec_data *first_codec, 1853 u8 status 1854) 1855{ 1856 u8 which; 1857 enum snd_azf3328_codec_type codec_type; 1858 const struct snd_azf3328_codec_data *codec = first_codec; 1859 1860 for (codec_type = AZF_CODEC_PLAYBACK; 1861 codec_type <= AZF_CODEC_I2S_OUT; 1862 ++codec_type, ++codec) { 1863 1864 /* skip codec if there's no interrupt for it */ 1865 if (!(status & (1 << codec_type))) 1866 continue; 1867 1868 spin_lock(codec->lock); 1869 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); 1870 /* ack all IRQ types immediately */ 1871 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); 1872 spin_unlock(codec->lock); 1873 1874 if (codec->substream) { 1875 snd_pcm_period_elapsed(codec->substream); 1876 dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n", 1877 codec->name, 1878 which, 1879 snd_azf3328_codec_inl( 1880 codec, IDX_IO_CODEC_DMA_CURRPOS)); 1881 } else 1882 dev_warn(chip->card->dev, "irq handler problem!\n"); 1883 if (which & IRQ_SOMETHING) 1884 snd_azf3328_irq_log_unknown_type(chip, which); 1885 } 1886} 1887 1888static irqreturn_t 1889snd_azf3328_interrupt(int irq, void *dev_id) 1890{ 1891 struct snd_azf3328 *chip = dev_id; 1892 u8 status; 1893 static unsigned long irq_count; 1894 1895 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); 1896 1897 /* fast path out, to ease interrupt sharing */ 1898 if (!(status & 1899 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT 1900 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) 1901 )) 1902 return IRQ_NONE; /* must be interrupt for another device */ 1903 1904 dev_dbg(chip->card->dev, 1905 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", 1906 irq_count++ /* debug-only */, 1907 status); 1908 1909 if (status & IRQ_TIMER) { 1910 /* dev_dbg(chip->card->dev, "timer %ld\n", 1911 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) 1912 & TIMER_VALUE_MASK 1913 ); */ 1914 if (chip->timer) 1915 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1916 /* ACK timer */ 1917 spin_lock(&chip->reg_lock); 1918 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); 1919 spin_unlock(&chip->reg_lock); 1920 dev_dbg(chip->card->dev, "timer IRQ\n"); 1921 } 1922 1923 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) 1924 snd_azf3328_pcm_interrupt(chip, chip->codecs, status); 1925 1926 if (status & IRQ_GAMEPORT) 1927 snd_azf3328_gameport_interrupt(chip); 1928 1929 /* MPU401 has less critical IRQ requirements 1930 * than timer and playback/recording, right? */ 1931 if (status & IRQ_MPU401) { 1932 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1933 1934 /* hmm, do we have to ack the IRQ here somehow? 1935 * If so, then I don't know how yet... */ 1936 dev_dbg(chip->card->dev, "MPU401 IRQ\n"); 1937 } 1938 return IRQ_HANDLED; 1939} 1940 1941/*****************************************************************/ 1942 1943/* as long as we think we have identical snd_pcm_hardware parameters 1944 for playback, capture and i2s out, we can use the same physical struct 1945 since the struct is simply being copied into a member. 1946*/ 1947static const struct snd_pcm_hardware snd_azf3328_hardware = 1948{ 1949 /* FIXME!! Correct? */ 1950 .info = SNDRV_PCM_INFO_MMAP | 1951 SNDRV_PCM_INFO_INTERLEAVED | 1952 SNDRV_PCM_INFO_MMAP_VALID, 1953 .formats = SNDRV_PCM_FMTBIT_S8 | 1954 SNDRV_PCM_FMTBIT_U8 | 1955 SNDRV_PCM_FMTBIT_S16_LE | 1956 SNDRV_PCM_FMTBIT_U16_LE, 1957 .rates = SNDRV_PCM_RATE_5512 | 1958 SNDRV_PCM_RATE_8000_48000 | 1959 SNDRV_PCM_RATE_KNOT, 1960 .rate_min = AZF_FREQ_4000, 1961 .rate_max = AZF_FREQ_66200, 1962 .channels_min = 1, 1963 .channels_max = 2, 1964 .buffer_bytes_max = (64*1024), 1965 .period_bytes_min = 1024, 1966 .period_bytes_max = (32*1024), 1967 /* We simply have two DMA areas (instead of a list of descriptors 1968 such as other cards); I believe that this is a fixed hardware 1969 attribute and there isn't much driver magic to be done to expand it. 1970 Thus indicate that we have at least and at most 2 periods. */ 1971 .periods_min = 2, 1972 .periods_max = 2, 1973 /* FIXME: maybe that card actually has a FIFO? 1974 * Hmm, it seems newer revisions do have one, but we still don't know 1975 * its size... */ 1976 .fifo_size = 0, 1977}; 1978 1979 1980static const unsigned int snd_azf3328_fixed_rates[] = { 1981 AZF_FREQ_4000, 1982 AZF_FREQ_4800, 1983 AZF_FREQ_5512, 1984 AZF_FREQ_6620, 1985 AZF_FREQ_8000, 1986 AZF_FREQ_9600, 1987 AZF_FREQ_11025, 1988 AZF_FREQ_13240, 1989 AZF_FREQ_16000, 1990 AZF_FREQ_22050, 1991 AZF_FREQ_32000, 1992 AZF_FREQ_44100, 1993 AZF_FREQ_48000, 1994 AZF_FREQ_66200 1995}; 1996 1997static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { 1998 .count = ARRAY_SIZE(snd_azf3328_fixed_rates), 1999 .list = snd_azf3328_fixed_rates, 2000 .mask = 0, 2001}; 2002 2003/*****************************************************************/ 2004 2005static int 2006snd_azf3328_pcm_open(struct snd_pcm_substream *substream, 2007 enum snd_azf3328_codec_type codec_type 2008) 2009{ 2010 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 2011 struct snd_pcm_runtime *runtime = substream->runtime; 2012 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 2013 2014 codec->substream = substream; 2015 2016 /* same parameters for all our codecs - at least we think so... */ 2017 runtime->hw = snd_azf3328_hardware; 2018 2019 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 2020 &snd_azf3328_hw_constraints_rates); 2021 runtime->private_data = codec; 2022 return 0; 2023} 2024 2025static int 2026snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) 2027{ 2028 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); 2029} 2030 2031static int 2032snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) 2033{ 2034 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); 2035} 2036 2037static int 2038snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) 2039{ 2040 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); 2041} 2042 2043static int 2044snd_azf3328_pcm_close(struct snd_pcm_substream *substream 2045) 2046{ 2047 struct snd_azf3328_codec_data *codec = 2048 substream->runtime->private_data; 2049 2050 codec->substream = NULL; 2051 return 0; 2052} 2053 2054/******************************************************************/ 2055 2056static const struct snd_pcm_ops snd_azf3328_playback_ops = { 2057 .open = snd_azf3328_pcm_playback_open, 2058 .close = snd_azf3328_pcm_close, 2059 .prepare = snd_azf3328_pcm_prepare, 2060 .trigger = snd_azf3328_pcm_trigger, 2061 .pointer = snd_azf3328_pcm_pointer 2062}; 2063 2064static const struct snd_pcm_ops snd_azf3328_capture_ops = { 2065 .open = snd_azf3328_pcm_capture_open, 2066 .close = snd_azf3328_pcm_close, 2067 .prepare = snd_azf3328_pcm_prepare, 2068 .trigger = snd_azf3328_pcm_trigger, 2069 .pointer = snd_azf3328_pcm_pointer 2070}; 2071 2072static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = { 2073 .open = snd_azf3328_pcm_i2s_out_open, 2074 .close = snd_azf3328_pcm_close, 2075 .prepare = snd_azf3328_pcm_prepare, 2076 .trigger = snd_azf3328_pcm_trigger, 2077 .pointer = snd_azf3328_pcm_pointer 2078}; 2079 2080static int 2081snd_azf3328_pcm(struct snd_azf3328 *chip) 2082{ 2083 /* pcm devices */ 2084 enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; 2085 2086 struct snd_pcm *pcm; 2087 int err; 2088 2089 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, 2090 1, 1, &pcm); 2091 if (err < 0) 2092 return err; 2093 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2094 &snd_azf3328_playback_ops); 2095 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 2096 &snd_azf3328_capture_ops); 2097 2098 pcm->private_data = chip; 2099 pcm->info_flags = 0; 2100 strcpy(pcm->name, chip->card->shortname); 2101 /* same pcm object for playback/capture (see snd_pcm_new() above) */ 2102 chip->pcm[AZF_CODEC_PLAYBACK] = pcm; 2103 chip->pcm[AZF_CODEC_CAPTURE] = pcm; 2104 2105 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2106 64*1024, 64*1024); 2107 2108 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, 2109 1, 0, &pcm); 2110 if (err < 0) 2111 return err; 2112 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2113 &snd_azf3328_i2s_out_ops); 2114 2115 pcm->private_data = chip; 2116 pcm->info_flags = 0; 2117 strcpy(pcm->name, chip->card->shortname); 2118 chip->pcm[AZF_CODEC_I2S_OUT] = pcm; 2119 2120 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2121 64*1024, 64*1024); 2122 2123 return 0; 2124} 2125 2126/******************************************************************/ 2127 2128/*** NOTE: the physical timer resolution actually is 1024000 ticks per second 2129 *** (probably derived from main crystal via a divider of 24), 2130 *** but announcing those attributes to user-space would make programs 2131 *** configure the timer to a 1 tick value, resulting in an absolutely fatal 2132 *** timer IRQ storm. 2133 *** Thus I chose to announce a down-scaled virtual timer to the outside and 2134 *** calculate real timer countdown values internally. 2135 *** (the scale factor can be set via module parameter "seqtimer_scaling"). 2136 ***/ 2137 2138static int 2139snd_azf3328_timer_start(struct snd_timer *timer) 2140{ 2141 struct snd_azf3328 *chip; 2142 unsigned long flags; 2143 unsigned int delay; 2144 2145 chip = snd_timer_chip(timer); 2146 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; 2147 if (delay < 49) { 2148 /* uhoh, that's not good, since user-space won't know about 2149 * this timing tweak 2150 * (we need to do it to avoid a lockup, though) */ 2151 2152 dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay); 2153 delay = 49; /* minimum time is 49 ticks */ 2154 } 2155 dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay); 2156 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; 2157 spin_lock_irqsave(&chip->reg_lock, flags); 2158 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); 2159 spin_unlock_irqrestore(&chip->reg_lock, flags); 2160 return 0; 2161} 2162 2163static int 2164snd_azf3328_timer_stop(struct snd_timer *timer) 2165{ 2166 struct snd_azf3328 *chip; 2167 unsigned long flags; 2168 2169 chip = snd_timer_chip(timer); 2170 spin_lock_irqsave(&chip->reg_lock, flags); 2171 /* disable timer countdown and interrupt */ 2172 /* Hmm, should we write TIMER_IRQ_ACK here? 2173 YES indeed, otherwise a rogue timer operation - which prompts 2174 ALSA(?) to call repeated stop() in vain, but NOT start() - 2175 will never end (value 0x03 is kept shown in control byte). 2176 Simply manually poking 0x04 _once_ immediately successfully stops 2177 the hardware/ALSA interrupt activity. */ 2178 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); 2179 spin_unlock_irqrestore(&chip->reg_lock, flags); 2180 return 0; 2181} 2182 2183 2184static int 2185snd_azf3328_timer_precise_resolution(struct snd_timer *timer, 2186 unsigned long *num, unsigned long *den) 2187{ 2188 *num = 1; 2189 *den = 1024000 / seqtimer_scaling; 2190 return 0; 2191} 2192 2193static struct snd_timer_hardware snd_azf3328_timer_hw = { 2194 .flags = SNDRV_TIMER_HW_AUTO, 2195 .resolution = 977, /* 1000000/1024000 = 0.9765625us */ 2196 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ 2197 .start = snd_azf3328_timer_start, 2198 .stop = snd_azf3328_timer_stop, 2199 .precise_resolution = snd_azf3328_timer_precise_resolution, 2200}; 2201 2202static int 2203snd_azf3328_timer(struct snd_azf3328 *chip, int device) 2204{ 2205 struct snd_timer *timer = NULL; 2206 struct snd_timer_id tid; 2207 int err; 2208 2209 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 2210 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 2211 tid.card = chip->card->number; 2212 tid.device = device; 2213 tid.subdevice = 0; 2214 2215 snd_azf3328_timer_hw.resolution *= seqtimer_scaling; 2216 snd_azf3328_timer_hw.ticks /= seqtimer_scaling; 2217 2218 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); 2219 if (err < 0) 2220 goto out; 2221 2222 strcpy(timer->name, "AZF3328 timer"); 2223 timer->private_data = chip; 2224 timer->hw = snd_azf3328_timer_hw; 2225 2226 chip->timer = timer; 2227 2228 snd_azf3328_timer_stop(timer); 2229 2230 err = 0; 2231 2232out: 2233 return err; 2234} 2235 2236/******************************************************************/ 2237 2238static void 2239snd_azf3328_free(struct snd_card *card) 2240{ 2241 struct snd_azf3328 *chip = card->private_data; 2242 2243 snd_azf3328_mixer_reset(chip); 2244 2245 snd_azf3328_timer_stop(chip->timer); 2246 snd_azf3328_gameport_free(chip); 2247} 2248 2249#if 0 2250/* check whether a bit can be modified */ 2251static void 2252snd_azf3328_test_bit(unsigned unsigned reg, int bit) 2253{ 2254 unsigned char val, valoff, valon; 2255 2256 val = inb(reg); 2257 2258 outb(val & ~(1 << bit), reg); 2259 valoff = inb(reg); 2260 2261 outb(val|(1 << bit), reg); 2262 valon = inb(reg); 2263 2264 outb(val, reg); 2265 2266 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", 2267 reg, bit, val, valoff, valon 2268 ); 2269} 2270#endif 2271 2272static inline void 2273snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) 2274{ 2275 u16 tmp; 2276 2277 dev_dbg(chip->card->dev, 2278 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " 2279 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", 2280 chip->ctrl_io, chip->game_io, chip->mpu_io, 2281 chip->opl3_io, chip->mixer_io, chip->irq); 2282 2283 dev_dbg(chip->card->dev, 2284 "game %02x %02x %02x %02x %02x %02x\n", 2285 snd_azf3328_game_inb(chip, 0), 2286 snd_azf3328_game_inb(chip, 1), 2287 snd_azf3328_game_inb(chip, 2), 2288 snd_azf3328_game_inb(chip, 3), 2289 snd_azf3328_game_inb(chip, 4), 2290 snd_azf3328_game_inb(chip, 5)); 2291 2292 for (tmp = 0; tmp < 0x07; tmp += 1) 2293 dev_dbg(chip->card->dev, 2294 "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); 2295 2296 for (tmp = 0; tmp <= 0x07; tmp += 1) 2297 dev_dbg(chip->card->dev, 2298 "0x%02x: game200 0x%04x, game208 0x%04x\n", 2299 tmp, inb(0x200 + tmp), inb(0x208 + tmp)); 2300 2301 for (tmp = 0; tmp <= 0x01; tmp += 1) 2302 dev_dbg(chip->card->dev, 2303 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " 2304 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", 2305 tmp, 2306 inb(0x300 + tmp), 2307 inb(0x310 + tmp), 2308 inb(0x320 + tmp), 2309 inb(0x330 + tmp), 2310 inb(0x388 + tmp), 2311 inb(0x38c + tmp)); 2312 2313 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) 2314 dev_dbg(chip->card->dev, 2315 "ctrl 0x%02x: 0x%04x\n", 2316 tmp, snd_azf3328_ctrl_inw(chip, tmp)); 2317 2318 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) 2319 dev_dbg(chip->card->dev, 2320 "mixer 0x%02x: 0x%04x\n", 2321 tmp, snd_azf3328_mixer_inw(chip, tmp)); 2322} 2323 2324static int 2325snd_azf3328_create(struct snd_card *card, 2326 struct pci_dev *pci, 2327 unsigned long device_type) 2328{ 2329 struct snd_azf3328 *chip = card->private_data; 2330 int err; 2331 u8 dma_init; 2332 enum snd_azf3328_codec_type codec_type; 2333 struct snd_azf3328_codec_data *codec_setup; 2334 2335 err = pcim_enable_device(pci); 2336 if (err < 0) 2337 return err; 2338 2339 spin_lock_init(&chip->reg_lock); 2340 chip->card = card; 2341 chip->pci = pci; 2342 chip->irq = -1; 2343 2344 /* check if we can restrict PCI DMA transfers to 24 bits */ 2345 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { 2346 dev_err(card->dev, 2347 "architecture does not support 24bit PCI busmaster DMA\n" 2348 ); 2349 return -ENXIO; 2350 } 2351 2352 err = pci_request_regions(pci, "Aztech AZF3328"); 2353 if (err < 0) 2354 return err; 2355 2356 chip->ctrl_io = pci_resource_start(pci, 0); 2357 chip->game_io = pci_resource_start(pci, 1); 2358 chip->mpu_io = pci_resource_start(pci, 2); 2359 chip->opl3_io = pci_resource_start(pci, 3); 2360 chip->mixer_io = pci_resource_start(pci, 4); 2361 2362 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; 2363 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; 2364 codec_setup->lock = &chip->reg_lock; 2365 codec_setup->type = AZF_CODEC_PLAYBACK; 2366 codec_setup->name = "PLAYBACK"; 2367 2368 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; 2369 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; 2370 codec_setup->lock = &chip->reg_lock; 2371 codec_setup->type = AZF_CODEC_CAPTURE; 2372 codec_setup->name = "CAPTURE"; 2373 2374 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; 2375 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; 2376 codec_setup->lock = &chip->reg_lock; 2377 codec_setup->type = AZF_CODEC_I2S_OUT; 2378 codec_setup->name = "I2S_OUT"; 2379 2380 if (devm_request_irq(&pci->dev, pci->irq, snd_azf3328_interrupt, 2381 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2382 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2383 return -EBUSY; 2384 } 2385 chip->irq = pci->irq; 2386 card->sync_irq = chip->irq; 2387 card->private_free = snd_azf3328_free; 2388 pci_set_master(pci); 2389 2390 snd_azf3328_debug_show_ports(chip); 2391 2392 /* create mixer interface & switches */ 2393 err = snd_azf3328_mixer_new(chip); 2394 if (err < 0) 2395 return err; 2396 2397 /* standard codec init stuff */ 2398 /* default DMA init value */ 2399 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; 2400 2401 for (codec_type = AZF_CODEC_PLAYBACK; 2402 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { 2403 struct snd_azf3328_codec_data *codec = 2404 &chip->codecs[codec_type]; 2405 2406 /* shutdown codecs to reduce power / noise */ 2407 /* have ...ctrl_codec_activity() act properly */ 2408 codec->running = true; 2409 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); 2410 2411 spin_lock_irq(codec->lock); 2412 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, 2413 dma_init); 2414 spin_unlock_irq(codec->lock); 2415 } 2416 2417 return 0; 2418} 2419 2420static int 2421__snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2422{ 2423 static int dev; 2424 struct snd_card *card; 2425 struct snd_azf3328 *chip; 2426 struct snd_opl3 *opl3; 2427 int err; 2428 2429 if (dev >= SNDRV_CARDS) 2430 return -ENODEV; 2431 if (!enable[dev]) { 2432 dev++; 2433 return -ENOENT; 2434 } 2435 2436 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2437 sizeof(*chip), &card); 2438 if (err < 0) 2439 return err; 2440 chip = card->private_data; 2441 2442 strcpy(card->driver, "AZF3328"); 2443 strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); 2444 2445 err = snd_azf3328_create(card, pci, pci_id->driver_data); 2446 if (err < 0) 2447 return err; 2448 2449 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, 2450 since our hardware ought to be similar, thus use same ID. */ 2451 err = snd_mpu401_uart_new( 2452 card, 0, 2453 MPU401_HW_AZT2320, chip->mpu_io, 2454 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, 2455 -1, &chip->rmidi 2456 ); 2457 if (err < 0) { 2458 dev_err(card->dev, "no MPU-401 device at 0x%lx?\n", 2459 chip->mpu_io 2460 ); 2461 return err; 2462 } 2463 2464 err = snd_azf3328_timer(chip, 0); 2465 if (err < 0) 2466 return err; 2467 2468 err = snd_azf3328_pcm(chip); 2469 if (err < 0) 2470 return err; 2471 2472 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, 2473 OPL3_HW_AUTO, 1, &opl3) < 0) { 2474 dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n", 2475 chip->opl3_io, chip->opl3_io+2 2476 ); 2477 } else { 2478 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ 2479 err = snd_opl3_timer_new(opl3, 1, 2); 2480 if (err < 0) 2481 return err; 2482 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); 2483 if (err < 0) 2484 return err; 2485 opl3->private_data = chip; 2486 } 2487 2488 sprintf(card->longname, "%s at 0x%lx, irq %i", 2489 card->shortname, chip->ctrl_io, chip->irq); 2490 2491 err = snd_card_register(card); 2492 if (err < 0) 2493 return err; 2494 2495#ifdef MODULE 2496 dev_info(card->dev, 2497 "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"); 2498 dev_info(card->dev, 2499 "Hardware was completely undocumented, unfortunately.\n"); 2500 dev_info(card->dev, 2501 "Feel free to contact andi AT lisas.de for bug reports etc.!\n"); 2502 dev_info(card->dev, 2503 "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 2504 1024000 / seqtimer_scaling, seqtimer_scaling); 2505#endif 2506 2507 snd_azf3328_gameport(chip, dev); 2508 2509 pci_set_drvdata(pci, card); 2510 dev++; 2511 return 0; 2512} 2513 2514static int 2515snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2516{ 2517 return snd_card_free_on_error(&pci->dev, __snd_azf3328_probe(pci, pci_id)); 2518} 2519 2520#ifdef CONFIG_PM_SLEEP 2521static inline void 2522snd_azf3328_suspend_regs(const struct snd_azf3328 *chip, 2523 unsigned long io_addr, unsigned count, u32 *saved_regs) 2524{ 2525 unsigned reg; 2526 2527 for (reg = 0; reg < count; ++reg) { 2528 *saved_regs = inl(io_addr); 2529 dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n", 2530 io_addr, *saved_regs); 2531 ++saved_regs; 2532 io_addr += sizeof(*saved_regs); 2533 } 2534} 2535 2536static inline void 2537snd_azf3328_resume_regs(const struct snd_azf3328 *chip, 2538 const u32 *saved_regs, 2539 unsigned long io_addr, 2540 unsigned count 2541) 2542{ 2543 unsigned reg; 2544 2545 for (reg = 0; reg < count; ++reg) { 2546 outl(*saved_regs, io_addr); 2547 dev_dbg(chip->card->dev, 2548 "resume: io 0x%04lx: 0x%08x --> 0x%08x\n", 2549 io_addr, *saved_regs, inl(io_addr)); 2550 ++saved_regs; 2551 io_addr += sizeof(*saved_regs); 2552 } 2553} 2554 2555static inline void 2556snd_azf3328_suspend_ac97(struct snd_azf3328 *chip) 2557{ 2558#ifdef AZF_USE_AC97_LAYER 2559 snd_ac97_suspend(chip->ac97); 2560#else 2561 snd_azf3328_suspend_regs(chip, chip->mixer_io, 2562 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); 2563 2564 /* make sure to disable master volume etc. to prevent looping sound */ 2565 snd_azf3328_mixer_mute_control_master(chip, 1); 2566 snd_azf3328_mixer_mute_control_pcm(chip, 1); 2567#endif /* AZF_USE_AC97_LAYER */ 2568} 2569 2570static inline void 2571snd_azf3328_resume_ac97(const struct snd_azf3328 *chip) 2572{ 2573#ifdef AZF_USE_AC97_LAYER 2574 snd_ac97_resume(chip->ac97); 2575#else 2576 snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io, 2577 ARRAY_SIZE(chip->saved_regs_mixer)); 2578 2579 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) 2580 and IDX_MIXER_RESET (offset 0x00) get touched at the same time, 2581 resulting in a mixer reset condition persisting until _after_ 2582 master vol was restored. Thus master vol needs an extra restore. */ 2583 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); 2584#endif /* AZF_USE_AC97_LAYER */ 2585} 2586 2587static int 2588snd_azf3328_suspend(struct device *dev) 2589{ 2590 struct snd_card *card = dev_get_drvdata(dev); 2591 struct snd_azf3328 *chip = card->private_data; 2592 u16 *saved_regs_ctrl_u16; 2593 2594 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2595 2596 snd_azf3328_suspend_ac97(chip); 2597 2598 snd_azf3328_suspend_regs(chip, chip->ctrl_io, 2599 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); 2600 2601 /* manually store the one currently relevant write-only reg, too */ 2602 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; 2603 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; 2604 2605 snd_azf3328_suspend_regs(chip, chip->game_io, 2606 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); 2607 snd_azf3328_suspend_regs(chip, chip->mpu_io, 2608 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); 2609 snd_azf3328_suspend_regs(chip, chip->opl3_io, 2610 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); 2611 return 0; 2612} 2613 2614static int 2615snd_azf3328_resume(struct device *dev) 2616{ 2617 struct snd_card *card = dev_get_drvdata(dev); 2618 const struct snd_azf3328 *chip = card->private_data; 2619 2620 snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io, 2621 ARRAY_SIZE(chip->saved_regs_game)); 2622 snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io, 2623 ARRAY_SIZE(chip->saved_regs_mpu)); 2624 snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io, 2625 ARRAY_SIZE(chip->saved_regs_opl3)); 2626 2627 snd_azf3328_resume_ac97(chip); 2628 2629 snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io, 2630 ARRAY_SIZE(chip->saved_regs_ctrl)); 2631 2632 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2633 return 0; 2634} 2635 2636static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume); 2637#define SND_AZF3328_PM_OPS &snd_azf3328_pm 2638#else 2639#define SND_AZF3328_PM_OPS NULL 2640#endif /* CONFIG_PM_SLEEP */ 2641 2642static struct pci_driver azf3328_driver = { 2643 .name = KBUILD_MODNAME, 2644 .id_table = snd_azf3328_ids, 2645 .probe = snd_azf3328_probe, 2646 .driver = { 2647 .pm = SND_AZF3328_PM_OPS, 2648 }, 2649}; 2650 2651module_pci_driver(azf3328_driver); 2652