162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0 OR MIT) 262306a36Sopenharmony_ci/* Copyright (c) 2020-2021 Microchip Technology Inc */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/ { 562306a36Sopenharmony_ci compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", 662306a36Sopenharmony_ci "microchip,mpfs"; 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci core_pwm0: pwm@40000000 { 962306a36Sopenharmony_ci compatible = "microchip,corepwm-rtl-v4"; 1062306a36Sopenharmony_ci reg = <0x0 0x40000000 0x0 0xF0>; 1162306a36Sopenharmony_ci microchip,sync-update-mask = /bits/ 32 <0>; 1262306a36Sopenharmony_ci #pwm-cells = <3>; 1362306a36Sopenharmony_ci clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; 1462306a36Sopenharmony_ci status = "disabled"; 1562306a36Sopenharmony_ci }; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci i2c2: i2c@40000200 { 1862306a36Sopenharmony_ci compatible = "microchip,corei2c-rtl-v7"; 1962306a36Sopenharmony_ci reg = <0x0 0x40000200 0x0 0x100>; 2062306a36Sopenharmony_ci #address-cells = <1>; 2162306a36Sopenharmony_ci #size-cells = <0>; 2262306a36Sopenharmony_ci clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; 2362306a36Sopenharmony_ci interrupt-parent = <&plic>; 2462306a36Sopenharmony_ci interrupts = <122>; 2562306a36Sopenharmony_ci clock-frequency = <100000>; 2662306a36Sopenharmony_ci status = "disabled"; 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci pcie: pcie@3000000000 { 3062306a36Sopenharmony_ci compatible = "microchip,pcie-host-1.0"; 3162306a36Sopenharmony_ci #address-cells = <0x3>; 3262306a36Sopenharmony_ci #interrupt-cells = <0x1>; 3362306a36Sopenharmony_ci #size-cells = <0x2>; 3462306a36Sopenharmony_ci device_type = "pci"; 3562306a36Sopenharmony_ci reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 3662306a36Sopenharmony_ci reg-names = "cfg", "apb"; 3762306a36Sopenharmony_ci bus-range = <0x0 0x7f>; 3862306a36Sopenharmony_ci interrupt-parent = <&plic>; 3962306a36Sopenharmony_ci interrupts = <119>; 4062306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie_intc 0>, 4162306a36Sopenharmony_ci <0 0 0 2 &pcie_intc 1>, 4262306a36Sopenharmony_ci <0 0 0 3 &pcie_intc 2>, 4362306a36Sopenharmony_ci <0 0 0 4 &pcie_intc 3>; 4462306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 4562306a36Sopenharmony_ci clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; 4662306a36Sopenharmony_ci clock-names = "fic1", "fic3"; 4762306a36Sopenharmony_ci ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; 4862306a36Sopenharmony_ci dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; 4962306a36Sopenharmony_ci msi-parent = <&pcie>; 5062306a36Sopenharmony_ci msi-controller; 5162306a36Sopenharmony_ci status = "disabled"; 5262306a36Sopenharmony_ci pcie_intc: interrupt-controller { 5362306a36Sopenharmony_ci #address-cells = <0>; 5462306a36Sopenharmony_ci #interrupt-cells = <1>; 5562306a36Sopenharmony_ci interrupt-controller; 5662306a36Sopenharmony_ci }; 5762306a36Sopenharmony_ci }; 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci refclk_ccc: cccrefclk { 6062306a36Sopenharmony_ci compatible = "fixed-clock"; 6162306a36Sopenharmony_ci #clock-cells = <0>; 6262306a36Sopenharmony_ci }; 6362306a36Sopenharmony_ci}; 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci&ccc_nw { 6662306a36Sopenharmony_ci clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, 6762306a36Sopenharmony_ci <&refclk_ccc>, <&refclk_ccc>; 6862306a36Sopenharmony_ci clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", 6962306a36Sopenharmony_ci "dll0_ref", "dll1_ref"; 7062306a36Sopenharmony_ci status = "okay"; 7162306a36Sopenharmony_ci}; 72