162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright 2022 Cirrus Logic, Inc.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#ifndef DT_CS35L45_H
962306a36Sopenharmony_ci#define DT_CS35L45_H
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci/*
1262306a36Sopenharmony_ci * cirrus,asp-sdout-hiz-ctrl
1362306a36Sopenharmony_ci *
1462306a36Sopenharmony_ci * TX_HIZ_UNUSED:   TX pin high-impedance during unused slots.
1562306a36Sopenharmony_ci * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
1662306a36Sopenharmony_ci */
1762306a36Sopenharmony_ci#define CS35L45_ASP_TX_HIZ_UNUSED	0x1
1862306a36Sopenharmony_ci#define CS35L45_ASP_TX_HIZ_DISABLED	0x2
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci/*
2162306a36Sopenharmony_ci * Optional GPIOX Sub-nodes:
2262306a36Sopenharmony_ci *  The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
2362306a36Sopenharmony_ci *  sub-nodes for configuring the GPIO pins.
2462306a36Sopenharmony_ci *
2562306a36Sopenharmony_ci * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
2662306a36Sopenharmony_ci *   is 1.
2762306a36Sopenharmony_ci *    0 = Output
2862306a36Sopenharmony_ci *    1 = Input (Default)
2962306a36Sopenharmony_ci *
3062306a36Sopenharmony_ci * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
3162306a36Sopenharmony_ci *
3262306a36Sopenharmony_ci *    0 = Low (Default)
3362306a36Sopenharmony_ci *    1 = High
3462306a36Sopenharmony_ci *
3562306a36Sopenharmony_ci * - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1
3662306a36Sopenharmony_ci *   and 'gpio-dir' is 0.
3762306a36Sopenharmony_ci *
3862306a36Sopenharmony_ci *    0 = CMOS (Default)
3962306a36Sopenharmony_ci *    1 = Open Drain
4062306a36Sopenharmony_ci *
4162306a36Sopenharmony_ci * - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1
4262306a36Sopenharmony_ci *   and 'gpio-dir' is 0.
4362306a36Sopenharmony_ci *
4462306a36Sopenharmony_ci *    0 = Non-inverted, Active High (Default)
4562306a36Sopenharmony_ci *    1 = Inverted, Active Low
4662306a36Sopenharmony_ci *
4762306a36Sopenharmony_ci * - gpio-invert : Defines the polarity of the GPIO pin if configured
4862306a36Sopenharmony_ci *   as input.
4962306a36Sopenharmony_ci *
5062306a36Sopenharmony_ci *    0 = Not inverted (Default)
5162306a36Sopenharmony_ci *    1 = Inverted
5262306a36Sopenharmony_ci *
5362306a36Sopenharmony_ci * - gpio-ctrl : Defines the function of the GPIO pin.
5462306a36Sopenharmony_ci *
5562306a36Sopenharmony_ci * GPIO1:
5662306a36Sopenharmony_ci *   0 = High impedance input (Default)
5762306a36Sopenharmony_ci *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
5862306a36Sopenharmony_ci *   2 = Pin acts as MDSYNC, direction controlled by MDSYNC
5962306a36Sopenharmony_ci *   3-7 = Reserved
6062306a36Sopenharmony_ci *
6162306a36Sopenharmony_ci * GPIO2:
6262306a36Sopenharmony_ci *   0 = High impedance input (Default)
6362306a36Sopenharmony_ci *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
6462306a36Sopenharmony_ci *   2 = Pin acts as open drain INT
6562306a36Sopenharmony_ci *   3 = Reserved
6662306a36Sopenharmony_ci *   4 = Pin acts as push-pull output INT. Active low.
6762306a36Sopenharmony_ci *   5 = Pin acts as push-pull output INT. Active high.
6862306a36Sopenharmony_ci *   6,7 = Reserved
6962306a36Sopenharmony_ci *
7062306a36Sopenharmony_ci * GPIO3:
7162306a36Sopenharmony_ci *   0 = High impedance input (Default)
7262306a36Sopenharmony_ci *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
7362306a36Sopenharmony_ci *   2-7 = Reserved
7462306a36Sopenharmony_ci */
7562306a36Sopenharmony_ci#define CS35L45_NUM_GPIOS	0x3
7662306a36Sopenharmony_ci
7762306a36Sopenharmony_ci#endif /* DT_CS35L45_H */
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