162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2016 Intel Corporation. All rights reserved 462306a36Sopenharmony_ci * Copyright (C) 2016 Altera Corporation. All rights reserved 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 1062306a36Sopenharmony_ci#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* MPUMODRST */ 1362306a36Sopenharmony_ci#define CPU0_RESET 0 1462306a36Sopenharmony_ci#define CPU1_RESET 1 1562306a36Sopenharmony_ci#define CPU2_RESET 2 1662306a36Sopenharmony_ci#define CPU3_RESET 3 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* PER0MODRST */ 1962306a36Sopenharmony_ci#define EMAC0_RESET 32 2062306a36Sopenharmony_ci#define EMAC1_RESET 33 2162306a36Sopenharmony_ci#define EMAC2_RESET 34 2262306a36Sopenharmony_ci#define USB0_RESET 35 2362306a36Sopenharmony_ci#define USB1_RESET 36 2462306a36Sopenharmony_ci#define NAND_RESET 37 2562306a36Sopenharmony_ci/* 38 is empty */ 2662306a36Sopenharmony_ci#define SDMMC_RESET 39 2762306a36Sopenharmony_ci#define EMAC0_OCP_RESET 40 2862306a36Sopenharmony_ci#define EMAC1_OCP_RESET 41 2962306a36Sopenharmony_ci#define EMAC2_OCP_RESET 42 3062306a36Sopenharmony_ci#define USB0_OCP_RESET 43 3162306a36Sopenharmony_ci#define USB1_OCP_RESET 44 3262306a36Sopenharmony_ci#define NAND_OCP_RESET 45 3362306a36Sopenharmony_ci/* 46 is empty */ 3462306a36Sopenharmony_ci#define SDMMC_OCP_RESET 47 3562306a36Sopenharmony_ci#define DMA_RESET 48 3662306a36Sopenharmony_ci#define SPIM0_RESET 49 3762306a36Sopenharmony_ci#define SPIM1_RESET 50 3862306a36Sopenharmony_ci#define SPIS0_RESET 51 3962306a36Sopenharmony_ci#define SPIS1_RESET 52 4062306a36Sopenharmony_ci#define DMA_OCP_RESET 53 4162306a36Sopenharmony_ci#define EMAC_PTP_RESET 54 4262306a36Sopenharmony_ci/* 55 is empty*/ 4362306a36Sopenharmony_ci#define DMAIF0_RESET 56 4462306a36Sopenharmony_ci#define DMAIF1_RESET 57 4562306a36Sopenharmony_ci#define DMAIF2_RESET 58 4662306a36Sopenharmony_ci#define DMAIF3_RESET 59 4762306a36Sopenharmony_ci#define DMAIF4_RESET 60 4862306a36Sopenharmony_ci#define DMAIF5_RESET 61 4962306a36Sopenharmony_ci#define DMAIF6_RESET 62 5062306a36Sopenharmony_ci#define DMAIF7_RESET 63 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci/* PER1MODRST */ 5362306a36Sopenharmony_ci#define WATCHDOG0_RESET 64 5462306a36Sopenharmony_ci#define WATCHDOG1_RESET 65 5562306a36Sopenharmony_ci#define WATCHDOG2_RESET 66 5662306a36Sopenharmony_ci#define WATCHDOG3_RESET 67 5762306a36Sopenharmony_ci#define L4SYSTIMER0_RESET 68 5862306a36Sopenharmony_ci#define L4SYSTIMER1_RESET 69 5962306a36Sopenharmony_ci#define SPTIMER0_RESET 70 6062306a36Sopenharmony_ci#define SPTIMER1_RESET 71 6162306a36Sopenharmony_ci#define I2C0_RESET 72 6262306a36Sopenharmony_ci#define I2C1_RESET 73 6362306a36Sopenharmony_ci#define I2C2_RESET 74 6462306a36Sopenharmony_ci#define I2C3_RESET 75 6562306a36Sopenharmony_ci#define I2C4_RESET 76 6662306a36Sopenharmony_ci#define I3C0_RESET 77 6762306a36Sopenharmony_ci#define I3C1_RESET 78 6862306a36Sopenharmony_ci/* 79 is empty */ 6962306a36Sopenharmony_ci#define UART0_RESET 80 7062306a36Sopenharmony_ci#define UART1_RESET 81 7162306a36Sopenharmony_ci/* 82-87 is empty */ 7262306a36Sopenharmony_ci#define GPIO0_RESET 88 7362306a36Sopenharmony_ci#define GPIO1_RESET 89 7462306a36Sopenharmony_ci#define WATCHDOG4_RESET 90 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_ci/* BRGMODRST */ 7762306a36Sopenharmony_ci#define SOC2FPGA_RESET 96 7862306a36Sopenharmony_ci#define LWHPS2FPGA_RESET 97 7962306a36Sopenharmony_ci#define FPGA2SOC_RESET 98 8062306a36Sopenharmony_ci#define F2SSDRAM0_RESET 99 8162306a36Sopenharmony_ci#define F2SSDRAM1_RESET 100 8262306a36Sopenharmony_ci#define F2SSDRAM2_RESET 101 8362306a36Sopenharmony_ci#define DDRSCH_RESET 102 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci/* COLDMODRST */ 8662306a36Sopenharmony_ci#define CPUPO0_RESET 160 8762306a36Sopenharmony_ci#define CPUPO1_RESET 161 8862306a36Sopenharmony_ci#define CPUPO2_RESET 162 8962306a36Sopenharmony_ci#define CPUPO3_RESET 163 9062306a36Sopenharmony_ci/* 164-167 is empty */ 9162306a36Sopenharmony_ci#define L2_RESET 168 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci/* DBGMODRST */ 9462306a36Sopenharmony_ci#define DBG_RESET 224 9562306a36Sopenharmony_ci#define CSDAP_RESET 225 9662306a36Sopenharmony_ci 9762306a36Sopenharmony_ci/* TAPMODRST */ 9862306a36Sopenharmony_ci#define TAP_RESET 256 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci#endif 101