162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
262306a36Sopenharmony_ci//
362306a36Sopenharmony_ci// Device Tree binding constants for Actions Semi S900 Reset Management Unit
462306a36Sopenharmony_ci//
562306a36Sopenharmony_ci// Copyright (c) 2018 Linaro Ltd.
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
862306a36Sopenharmony_ci#define __DT_BINDINGS_ACTIONS_S900_RESET_H
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#define RESET_CHIPID				0
1162306a36Sopenharmony_ci#define RESET_CPU_SCNT				1
1262306a36Sopenharmony_ci#define RESET_SRAMI				2
1362306a36Sopenharmony_ci#define RESET_DDR_CTL_PHY			3
1462306a36Sopenharmony_ci#define RESET_DMAC				4
1562306a36Sopenharmony_ci#define RESET_GPIO				5
1662306a36Sopenharmony_ci#define RESET_BISP_AXI				6
1762306a36Sopenharmony_ci#define RESET_CSI0				7
1862306a36Sopenharmony_ci#define RESET_CSI1				8
1962306a36Sopenharmony_ci#define RESET_DE				9
2062306a36Sopenharmony_ci#define RESET_DSI				10
2162306a36Sopenharmony_ci#define RESET_GPU3D_PA				11
2262306a36Sopenharmony_ci#define RESET_GPU3D_PB				12
2362306a36Sopenharmony_ci#define RESET_HDE				13
2462306a36Sopenharmony_ci#define RESET_I2C0				14
2562306a36Sopenharmony_ci#define RESET_I2C1				15
2662306a36Sopenharmony_ci#define RESET_I2C2				16
2762306a36Sopenharmony_ci#define RESET_I2C3				17
2862306a36Sopenharmony_ci#define RESET_I2C4				18
2962306a36Sopenharmony_ci#define RESET_I2C5				19
3062306a36Sopenharmony_ci#define RESET_IMX				20
3162306a36Sopenharmony_ci#define RESET_NANDC0				21
3262306a36Sopenharmony_ci#define RESET_NANDC1				22
3362306a36Sopenharmony_ci#define RESET_SD0				23
3462306a36Sopenharmony_ci#define RESET_SD1				24
3562306a36Sopenharmony_ci#define RESET_SD2				25
3662306a36Sopenharmony_ci#define RESET_SD3				26
3762306a36Sopenharmony_ci#define RESET_SPI0				27
3862306a36Sopenharmony_ci#define RESET_SPI1				28
3962306a36Sopenharmony_ci#define RESET_SPI2				29
4062306a36Sopenharmony_ci#define RESET_SPI3				30
4162306a36Sopenharmony_ci#define RESET_UART0				31
4262306a36Sopenharmony_ci#define RESET_UART1				32
4362306a36Sopenharmony_ci#define RESET_UART2				33
4462306a36Sopenharmony_ci#define RESET_UART3				34
4562306a36Sopenharmony_ci#define RESET_UART4				35
4662306a36Sopenharmony_ci#define RESET_UART5				36
4762306a36Sopenharmony_ci#define RESET_UART6				37
4862306a36Sopenharmony_ci#define RESET_HDMI				38
4962306a36Sopenharmony_ci#define RESET_LVDS				39
5062306a36Sopenharmony_ci#define RESET_EDP				40
5162306a36Sopenharmony_ci#define RESET_USB2HUB				41
5262306a36Sopenharmony_ci#define RESET_USB2HSIC				42
5362306a36Sopenharmony_ci#define RESET_USB3				43
5462306a36Sopenharmony_ci#define RESET_PCM1				44
5562306a36Sopenharmony_ci#define RESET_AUDIO				45
5662306a36Sopenharmony_ci#define RESET_PCM0				46
5762306a36Sopenharmony_ci#define RESET_SE				47
5862306a36Sopenharmony_ci#define RESET_GIC				48
5962306a36Sopenharmony_ci#define RESET_DDR_CTL_PHY_AXI			49
6062306a36Sopenharmony_ci#define RESET_CMU_DDR				50
6162306a36Sopenharmony_ci#define RESET_DMM				51
6262306a36Sopenharmony_ci#define RESET_HDCP2TX				52
6362306a36Sopenharmony_ci#define RESET_ETHERNET				53
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */
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