1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Samsung's Exynos pinctrl bindings 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Author: Krzysztof Kozlowski <krzk@kernel.org> 8 */ 9 10#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 11#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 12 13/* 14 * These bindings are deprecated, because they do not match the actual 15 * concept of bindings but rather contain pure register values. 16 * Instead include the header in the DTS source directory. 17 */ 18#warning "These bindings are deprecated. Instead use the header in the DTS source directory." 19 20#define EXYNOS_PIN_PULL_NONE 0 21#define EXYNOS_PIN_PULL_DOWN 1 22#define EXYNOS_PIN_PULL_UP 3 23 24#define S3C64XX_PIN_PULL_NONE 0 25#define S3C64XX_PIN_PULL_DOWN 1 26#define S3C64XX_PIN_PULL_UP 2 27 28/* Pin function in power down mode */ 29#define EXYNOS_PIN_PDN_OUT0 0 30#define EXYNOS_PIN_PDN_OUT1 1 31#define EXYNOS_PIN_PDN_INPUT 2 32#define EXYNOS_PIN_PDN_PREV 3 33 34/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 35#define EXYNOS4_PIN_DRV_LV1 0 36#define EXYNOS4_PIN_DRV_LV2 2 37#define EXYNOS4_PIN_DRV_LV3 1 38#define EXYNOS4_PIN_DRV_LV4 3 39 40/* Drive strengths for Exynos5260 */ 41#define EXYNOS5260_PIN_DRV_LV1 0 42#define EXYNOS5260_PIN_DRV_LV2 1 43#define EXYNOS5260_PIN_DRV_LV4 2 44#define EXYNOS5260_PIN_DRV_LV6 3 45 46/* 47 * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except 48 * GPIO_HSI block) 49 */ 50#define EXYNOS5420_PIN_DRV_LV1 0 51#define EXYNOS5420_PIN_DRV_LV2 1 52#define EXYNOS5420_PIN_DRV_LV3 2 53#define EXYNOS5420_PIN_DRV_LV4 3 54 55/* Drive strengths for Exynos5433 */ 56#define EXYNOS5433_PIN_DRV_FAST_SR1 0 57#define EXYNOS5433_PIN_DRV_FAST_SR2 1 58#define EXYNOS5433_PIN_DRV_FAST_SR3 2 59#define EXYNOS5433_PIN_DRV_FAST_SR4 3 60#define EXYNOS5433_PIN_DRV_FAST_SR5 4 61#define EXYNOS5433_PIN_DRV_FAST_SR6 5 62#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 63#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 64#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 65#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 66#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 67#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 68 69/* Drive strengths for Exynos850 GPIO_HSI block */ 70#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ 71#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ 72#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ 73#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ 74#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ 75#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ 76 77#define EXYNOS_PIN_FUNC_INPUT 0 78#define EXYNOS_PIN_FUNC_OUTPUT 1 79#define EXYNOS_PIN_FUNC_2 2 80#define EXYNOS_PIN_FUNC_3 3 81#define EXYNOS_PIN_FUNC_4 4 82#define EXYNOS_PIN_FUNC_5 5 83#define EXYNOS_PIN_FUNC_6 6 84#define EXYNOS_PIN_FUNC_EINT 0xf 85#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 86 87/* Drive strengths for Exynos7 FSYS1 block */ 88#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 89#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 90#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 91#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 92#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 93#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 94 95#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ 96