162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * MIO pin configuration defines for Xilinx ZynqMP
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2020 Xilinx, Inc.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
962306a36Sopenharmony_ci#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci/* Bit value for different voltage levels */
1262306a36Sopenharmony_ci#define IO_STANDARD_LVCMOS33	0
1362306a36Sopenharmony_ci#define IO_STANDARD_LVCMOS18	1
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci/* Bit values for Slew Rates */
1662306a36Sopenharmony_ci#define SLEW_RATE_FAST		0
1762306a36Sopenharmony_ci#define SLEW_RATE_SLOW		1
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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