162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * MIO pin configuration defines for Xilinx Zynq 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2021 Xilinx, Inc. 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H 962306a36Sopenharmony_ci#define _DT_BINDINGS_PINCTRL_ZYNQ_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* Configuration options for different power supplies */ 1262306a36Sopenharmony_ci#define IO_STANDARD_LVCMOS18 1 1362306a36Sopenharmony_ci#define IO_STANDARD_LVCMOS25 2 1462306a36Sopenharmony_ci#define IO_STANDARD_LVCMOS33 3 1562306a36Sopenharmony_ci#define IO_STANDARD_HSTL 4 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ 18