162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * This header provides constants for Tegra pinctrl bindings. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Author: Laxman Dewangan <ldewangan@nvidia.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 1162306a36Sopenharmony_ci#define _DT_BINDINGS_PINCTRL_TEGRA_H 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* 1462306a36Sopenharmony_ci * Enable/disable for diffeent dt properties. This is applicable for 1562306a36Sopenharmony_ci * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 1662306a36Sopenharmony_ci * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 1762306a36Sopenharmony_ci */ 1862306a36Sopenharmony_ci#define TEGRA_PIN_DISABLE 0 1962306a36Sopenharmony_ci#define TEGRA_PIN_ENABLE 1 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define TEGRA_PIN_PULL_NONE 0 2262306a36Sopenharmony_ci#define TEGRA_PIN_PULL_DOWN 1 2362306a36Sopenharmony_ci#define TEGRA_PIN_PULL_UP 2 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci/* Low power mode driver */ 2662306a36Sopenharmony_ci#define TEGRA_PIN_LP_DRIVE_DIV_8 0 2762306a36Sopenharmony_ci#define TEGRA_PIN_LP_DRIVE_DIV_4 1 2862306a36Sopenharmony_ci#define TEGRA_PIN_LP_DRIVE_DIV_2 2 2962306a36Sopenharmony_ci#define TEGRA_PIN_LP_DRIVE_DIV_1 3 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci/* Rising/Falling slew rate */ 3262306a36Sopenharmony_ci#define TEGRA_PIN_SLEW_RATE_FASTEST 0 3362306a36Sopenharmony_ci#define TEGRA_PIN_SLEW_RATE_FAST 1 3462306a36Sopenharmony_ci#define TEGRA_PIN_SLEW_RATE_SLOW 2 3562306a36Sopenharmony_ci#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci#endif 38