162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * This header provides macros for at91 dma bindings. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef __DT_BINDINGS_AT91_DMA_H__ 962306a36Sopenharmony_ci#define __DT_BINDINGS_AT91_DMA_H__ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* ---------- HDMAC ---------- */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* 1462306a36Sopenharmony_ci * Source and/or destination peripheral ID 1562306a36Sopenharmony_ci */ 1662306a36Sopenharmony_ci#define AT91_DMA_CFG_PER_ID_MASK (0xff) 1762306a36Sopenharmony_ci#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci/* 2062306a36Sopenharmony_ci * FIFO configuration: it defines when a request is serviced. 2162306a36Sopenharmony_ci */ 2262306a36Sopenharmony_ci#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 2362306a36Sopenharmony_ci#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 2462306a36Sopenharmony_ci#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 2562306a36Sopenharmony_ci#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 2662306a36Sopenharmony_ci#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci/* ---------- XDMAC ---------- */ 3062306a36Sopenharmony_ci#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 3162306a36Sopenharmony_ci#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 3262306a36Sopenharmony_ci#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 3362306a36Sopenharmony_ci << AT91_XDMAC_DT_MEM_IF_OFFSET) 3462306a36Sopenharmony_ci#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 3562306a36Sopenharmony_ci & AT91_XDMAC_DT_MEM_IF_MASK) 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci#define AT91_XDMAC_DT_PER_IF_MASK (0x1) 3862306a36Sopenharmony_ci#define AT91_XDMAC_DT_PER_IF_OFFSET (14) 3962306a36Sopenharmony_ci#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 4062306a36Sopenharmony_ci << AT91_XDMAC_DT_PER_IF_OFFSET) 4162306a36Sopenharmony_ci#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 4262306a36Sopenharmony_ci & AT91_XDMAC_DT_PER_IF_MASK) 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci#define AT91_XDMAC_DT_PERID_MASK (0x7f) 4562306a36Sopenharmony_ci#define AT91_XDMAC_DT_PERID_OFFSET (24) 4662306a36Sopenharmony_ci#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 4762306a36Sopenharmony_ci << AT91_XDMAC_DT_PERID_OFFSET) 4862306a36Sopenharmony_ci#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 4962306a36Sopenharmony_ci & AT91_XDMAC_DT_PERID_MASK) 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci#endif /* __DT_BINDINGS_AT91_DMA_H__ */ 52