162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * They are roughly ordered as: 662306a36Sopenharmony_ci * - external clocks 762306a36Sopenharmony_ci * - PLLs 862306a36Sopenharmony_ci * - muxes/dividers in the order they appear in the jz4740 programmers manual 962306a36Sopenharmony_ci * - gates in order of their bit in the CLKGR* registers 1062306a36Sopenharmony_ci */ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 1362306a36Sopenharmony_ci#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define JZ4740_CLK_EXT 0 1662306a36Sopenharmony_ci#define JZ4740_CLK_RTC 1 1762306a36Sopenharmony_ci#define JZ4740_CLK_PLL 2 1862306a36Sopenharmony_ci#define JZ4740_CLK_PLL_HALF 3 1962306a36Sopenharmony_ci#define JZ4740_CLK_CCLK 4 2062306a36Sopenharmony_ci#define JZ4740_CLK_HCLK 5 2162306a36Sopenharmony_ci#define JZ4740_CLK_PCLK 6 2262306a36Sopenharmony_ci#define JZ4740_CLK_MCLK 7 2362306a36Sopenharmony_ci#define JZ4740_CLK_LCD 8 2462306a36Sopenharmony_ci#define JZ4740_CLK_LCD_PCLK 9 2562306a36Sopenharmony_ci#define JZ4740_CLK_I2S 10 2662306a36Sopenharmony_ci#define JZ4740_CLK_SPI 11 2762306a36Sopenharmony_ci#define JZ4740_CLK_MMC 12 2862306a36Sopenharmony_ci#define JZ4740_CLK_UHC 13 2962306a36Sopenharmony_ci#define JZ4740_CLK_UDC 14 3062306a36Sopenharmony_ci#define JZ4740_CLK_UART0 15 3162306a36Sopenharmony_ci#define JZ4740_CLK_UART1 16 3262306a36Sopenharmony_ci#define JZ4740_CLK_DMA 17 3362306a36Sopenharmony_ci#define JZ4740_CLK_IPU 18 3462306a36Sopenharmony_ci#define JZ4740_CLK_ADC 19 3562306a36Sopenharmony_ci#define JZ4740_CLK_I2C 20 3662306a36Sopenharmony_ci#define JZ4740_CLK_AIC 21 3762306a36Sopenharmony_ci#define JZ4740_CLK_TCU 22 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ 40