162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0+ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * dts file for Xilinx ZynqMP ZCU102 Rev1.0 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * (C) Copyright 2016 - 2018, Xilinx, Inc. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Michal Simek <michal.simek@amd.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include "zynqmp-zcu102-revB.dts" 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/ { 1362306a36Sopenharmony_ci model = "ZynqMP ZCU102 Rev1.0"; 1462306a36Sopenharmony_ci compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 1562306a36Sopenharmony_ci}; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci&eeprom { 1862306a36Sopenharmony_ci #address-cells = <1>; 1962306a36Sopenharmony_ci #size-cells = <1>; 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci board_sn: board-sn@0 { 2262306a36Sopenharmony_ci reg = <0x0 0x14>; 2362306a36Sopenharmony_ci }; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci eth_mac: eth-mac@20 { 2662306a36Sopenharmony_ci reg = <0x20 0x6>; 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci board_name: board-name@d0 { 3062306a36Sopenharmony_ci reg = <0xd0 0x6>; 3162306a36Sopenharmony_ci }; 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci board_revision: board-revision@e0 { 3462306a36Sopenharmony_ci reg = <0xe0 0x3>; 3562306a36Sopenharmony_ci }; 3662306a36Sopenharmony_ci}; 37