162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) Siemens AG, 2021 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Authors: 662306a36Sopenharmony_ci * Chao Zeng <chao.zeng@siemens.com> 762306a36Sopenharmony_ci * Jan Kiszka <jan.kiszka@siemens.com> 862306a36Sopenharmony_ci * 962306a36Sopenharmony_ci * Common bits of the IOT2050 Basic and Advanced variants, PG2 1062306a36Sopenharmony_ci */ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci&main_pmx0 { 1362306a36Sopenharmony_ci cp2102n_reset_pin_default: cp2102n-reset-default-pins { 1462306a36Sopenharmony_ci pinctrl-single,pins = < 1562306a36Sopenharmony_ci /* (AF12) GPIO1_24, used as cp2102 reset */ 1662306a36Sopenharmony_ci AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) 1762306a36Sopenharmony_ci >; 1862306a36Sopenharmony_ci }; 1962306a36Sopenharmony_ci}; 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci&main_gpio1 { 2262306a36Sopenharmony_ci pinctrl-names = "default"; 2362306a36Sopenharmony_ci pinctrl-0 = <&cp2102n_reset_pin_default>; 2462306a36Sopenharmony_ci gpio-line-names = 2562306a36Sopenharmony_ci "", "", "", "", "", "", "", "", "", "", 2662306a36Sopenharmony_ci "", "", "", "", "", "", "", "", "", "", 2762306a36Sopenharmony_ci "", "", "", "", "CP2102N-RESET"; 2862306a36Sopenharmony_ci}; 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci&dss { 3162306a36Sopenharmony_ci /* Workaround needed to get DP clock of 154Mhz */ 3262306a36Sopenharmony_ci assigned-clocks = <&k3_clks 67 0>; 3362306a36Sopenharmony_ci}; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci&serdes0 { 3662306a36Sopenharmony_ci assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 3762306a36Sopenharmony_ci assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; 3862306a36Sopenharmony_ci}; 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci&dwc3_0 { 4162306a36Sopenharmony_ci assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 4262306a36Sopenharmony_ci <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ 4362306a36Sopenharmony_ci phys = <&serdes0 PHY_TYPE_USB3 0>; 4462306a36Sopenharmony_ci phy-names = "usb3-phy"; 4562306a36Sopenharmony_ci}; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci&usb0 { 4862306a36Sopenharmony_ci maximum-speed = "super-speed"; 4962306a36Sopenharmony_ci snps,dis-u1-entry-quirk; 5062306a36Sopenharmony_ci snps,dis-u2-entry-quirk; 5162306a36Sopenharmony_ci}; 52