162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Realtek RTD1395 SoC family 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2019 Andreas Färber 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci/memreserve/ 0x0000000000000000 0x000000000002f000; 962306a36Sopenharmony_ci/memreserve/ 0x000000000002f000 0x00000000000d1000; 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <dt-bindings/interrupt-controller/arm-gic.h> 1262306a36Sopenharmony_ci#include <dt-bindings/reset/realtek,rtd1295.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/ { 1562306a36Sopenharmony_ci interrupt-parent = <&gic>; 1662306a36Sopenharmony_ci #address-cells = <1>; 1762306a36Sopenharmony_ci #size-cells = <1>; 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci reserved-memory { 2062306a36Sopenharmony_ci #address-cells = <1>; 2162306a36Sopenharmony_ci #size-cells = <1>; 2262306a36Sopenharmony_ci ranges; 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci rpc_comm: rpc@2f000 { 2562306a36Sopenharmony_ci reg = <0x2f000 0x1000>; 2662306a36Sopenharmony_ci }; 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci rpc_ringbuf: rpc@1ffe000 { 2962306a36Sopenharmony_ci reg = <0x1ffe000 0x4000>; 3062306a36Sopenharmony_ci }; 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci tee: tee@10100000 { 3362306a36Sopenharmony_ci reg = <0x10100000 0xf00000>; 3462306a36Sopenharmony_ci no-map; 3562306a36Sopenharmony_ci }; 3662306a36Sopenharmony_ci }; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci arm_pmu: arm-pmu { 3962306a36Sopenharmony_ci compatible = "arm,cortex-a53-pmu"; 4062306a36Sopenharmony_ci interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 4162306a36Sopenharmony_ci }; 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci osc27M: osc { 4462306a36Sopenharmony_ci compatible = "fixed-clock"; 4562306a36Sopenharmony_ci clock-frequency = <27000000>; 4662306a36Sopenharmony_ci #clock-cells = <0>; 4762306a36Sopenharmony_ci clock-output-names = "osc27M"; 4862306a36Sopenharmony_ci }; 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci soc { 5162306a36Sopenharmony_ci compatible = "simple-bus"; 5262306a36Sopenharmony_ci #address-cells = <1>; 5362306a36Sopenharmony_ci #size-cells = <1>; 5462306a36Sopenharmony_ci ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ 5562306a36Sopenharmony_ci <0x98000000 0x98000000 0x68000000>; 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci rbus: bus@98000000 { 5862306a36Sopenharmony_ci compatible = "simple-bus"; 5962306a36Sopenharmony_ci reg = <0x98000000 0x200000>; 6062306a36Sopenharmony_ci #address-cells = <1>; 6162306a36Sopenharmony_ci #size-cells = <1>; 6262306a36Sopenharmony_ci ranges = <0x0 0x98000000 0x200000>; 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci crt: syscon@0 { 6562306a36Sopenharmony_ci compatible = "syscon", "simple-mfd"; 6662306a36Sopenharmony_ci reg = <0x0 0x1000>; 6762306a36Sopenharmony_ci reg-io-width = <4>; 6862306a36Sopenharmony_ci #address-cells = <1>; 6962306a36Sopenharmony_ci #size-cells = <1>; 7062306a36Sopenharmony_ci ranges = <0x0 0x0 0x1000>; 7162306a36Sopenharmony_ci }; 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci iso: syscon@7000 { 7462306a36Sopenharmony_ci compatible = "syscon", "simple-mfd"; 7562306a36Sopenharmony_ci reg = <0x7000 0x1000>; 7662306a36Sopenharmony_ci reg-io-width = <4>; 7762306a36Sopenharmony_ci #address-cells = <1>; 7862306a36Sopenharmony_ci #size-cells = <1>; 7962306a36Sopenharmony_ci ranges = <0x0 0x7000 0x1000>; 8062306a36Sopenharmony_ci }; 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci sb2: syscon@1a000 { 8362306a36Sopenharmony_ci compatible = "syscon", "simple-mfd"; 8462306a36Sopenharmony_ci reg = <0x1a000 0x1000>; 8562306a36Sopenharmony_ci reg-io-width = <4>; 8662306a36Sopenharmony_ci #address-cells = <1>; 8762306a36Sopenharmony_ci #size-cells = <1>; 8862306a36Sopenharmony_ci ranges = <0x0 0x1a000 0x1000>; 8962306a36Sopenharmony_ci }; 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_ci misc: syscon@1b000 { 9262306a36Sopenharmony_ci compatible = "syscon", "simple-mfd"; 9362306a36Sopenharmony_ci reg = <0x1b000 0x1000>; 9462306a36Sopenharmony_ci reg-io-width = <4>; 9562306a36Sopenharmony_ci #address-cells = <1>; 9662306a36Sopenharmony_ci #size-cells = <1>; 9762306a36Sopenharmony_ci ranges = <0x0 0x1b000 0x1000>; 9862306a36Sopenharmony_ci }; 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci scpu_wrapper: syscon@1d000 { 10162306a36Sopenharmony_ci compatible = "syscon", "simple-mfd"; 10262306a36Sopenharmony_ci reg = <0x1d000 0x2000>; 10362306a36Sopenharmony_ci reg-io-width = <4>; 10462306a36Sopenharmony_ci #address-cells = <1>; 10562306a36Sopenharmony_ci #size-cells = <1>; 10662306a36Sopenharmony_ci ranges = <0x0 0x1d000 0x2000>; 10762306a36Sopenharmony_ci }; 10862306a36Sopenharmony_ci }; 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_ci gic: interrupt-controller@ff011000 { 11162306a36Sopenharmony_ci compatible = "arm,gic-400"; 11262306a36Sopenharmony_ci reg = <0xff011000 0x1000>, 11362306a36Sopenharmony_ci <0xff012000 0x2000>, 11462306a36Sopenharmony_ci <0xff014000 0x2000>, 11562306a36Sopenharmony_ci <0xff016000 0x2000>; 11662306a36Sopenharmony_ci interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 11762306a36Sopenharmony_ci interrupt-controller; 11862306a36Sopenharmony_ci #interrupt-cells = <3>; 11962306a36Sopenharmony_ci }; 12062306a36Sopenharmony_ci }; 12162306a36Sopenharmony_ci}; 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci&crt { 12462306a36Sopenharmony_ci reset1: reset-controller@0 { 12562306a36Sopenharmony_ci compatible = "snps,dw-low-reset"; 12662306a36Sopenharmony_ci reg = <0x0 0x4>; 12762306a36Sopenharmony_ci #reset-cells = <1>; 12862306a36Sopenharmony_ci }; 12962306a36Sopenharmony_ci 13062306a36Sopenharmony_ci reset2: reset-controller@4 { 13162306a36Sopenharmony_ci compatible = "snps,dw-low-reset"; 13262306a36Sopenharmony_ci reg = <0x4 0x4>; 13362306a36Sopenharmony_ci #reset-cells = <1>; 13462306a36Sopenharmony_ci }; 13562306a36Sopenharmony_ci 13662306a36Sopenharmony_ci reset3: reset-controller@8 { 13762306a36Sopenharmony_ci compatible = "snps,dw-low-reset"; 13862306a36Sopenharmony_ci reg = <0x8 0x4>; 13962306a36Sopenharmony_ci #reset-cells = <1>; 14062306a36Sopenharmony_ci }; 14162306a36Sopenharmony_ci 14262306a36Sopenharmony_ci reset4: reset-controller@50 { 14362306a36Sopenharmony_ci compatible = "snps,dw-low-reset"; 14462306a36Sopenharmony_ci reg = <0x50 0x4>; 14562306a36Sopenharmony_ci #reset-cells = <1>; 14662306a36Sopenharmony_ci }; 14762306a36Sopenharmony_ci}; 14862306a36Sopenharmony_ci 14962306a36Sopenharmony_ci&iso { 15062306a36Sopenharmony_ci iso_reset: reset-controller@88 { 15162306a36Sopenharmony_ci compatible = "snps,dw-low-reset"; 15262306a36Sopenharmony_ci reg = <0x88 0x4>; 15362306a36Sopenharmony_ci #reset-cells = <1>; 15462306a36Sopenharmony_ci }; 15562306a36Sopenharmony_ci 15662306a36Sopenharmony_ci wdt: watchdog@680 { 15762306a36Sopenharmony_ci compatible = "realtek,rtd1295-watchdog"; 15862306a36Sopenharmony_ci reg = <0x680 0x100>; 15962306a36Sopenharmony_ci clocks = <&osc27M>; 16062306a36Sopenharmony_ci }; 16162306a36Sopenharmony_ci 16262306a36Sopenharmony_ci uart0: serial@800 { 16362306a36Sopenharmony_ci compatible = "snps,dw-apb-uart"; 16462306a36Sopenharmony_ci reg = <0x800 0x400>; 16562306a36Sopenharmony_ci reg-shift = <2>; 16662306a36Sopenharmony_ci reg-io-width = <4>; 16762306a36Sopenharmony_ci clock-frequency = <27000000>; 16862306a36Sopenharmony_ci resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 16962306a36Sopenharmony_ci status = "disabled"; 17062306a36Sopenharmony_ci }; 17162306a36Sopenharmony_ci}; 17262306a36Sopenharmony_ci 17362306a36Sopenharmony_ci&misc { 17462306a36Sopenharmony_ci uart1: serial@200 { 17562306a36Sopenharmony_ci compatible = "snps,dw-apb-uart"; 17662306a36Sopenharmony_ci reg = <0x200 0x100>; 17762306a36Sopenharmony_ci reg-shift = <2>; 17862306a36Sopenharmony_ci reg-io-width = <4>; 17962306a36Sopenharmony_ci clock-frequency = <432000000>; 18062306a36Sopenharmony_ci resets = <&reset2 RTD1295_RSTN_UR1>; 18162306a36Sopenharmony_ci status = "disabled"; 18262306a36Sopenharmony_ci }; 18362306a36Sopenharmony_ci 18462306a36Sopenharmony_ci uart2: serial@400 { 18562306a36Sopenharmony_ci compatible = "snps,dw-apb-uart"; 18662306a36Sopenharmony_ci reg = <0x400 0x100>; 18762306a36Sopenharmony_ci reg-shift = <2>; 18862306a36Sopenharmony_ci reg-io-width = <4>; 18962306a36Sopenharmony_ci clock-frequency = <432000000>; 19062306a36Sopenharmony_ci resets = <&reset2 RTD1295_RSTN_UR2>; 19162306a36Sopenharmony_ci status = "disabled"; 19262306a36Sopenharmony_ci }; 19362306a36Sopenharmony_ci}; 194